LSM9DS0 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 74
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Module specifications
- 2.1 Sensor characteristics
- 2.2 Temperature sensor characteristics
- 2.3 Electrical characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 Sensor I 2C - inter-IC control interface
- 2.5 Absolute maximum ratings
- 3 Terminology
- 3.1 Set / reset pulse
- 3.2 Sensitivity
- 3.2.1 Linear acceleration sensor sensitivity
- 3.2.2 Magnetic sensor sensitivity
- 3.2.3 Angular rate sensitivity
- 3.2.4 Zero-g level
- 3.2.5 Zero-gauss level
- 3.2.6 Zero-rate level
- 4 Functionality
- 4.1 Self-test
- 4.1.1 Accelerometer
- 4.1.2 Gyroscope
- 4.2 Linear acceleration main digital blocks
- 4.2.1 FIFO
- 4.2.2 Bypass mode
- 4.2.3 FIFO mode
- 4.2.4 Stream mode
- 4.2.5 Stream-to-FIFO mode
Datasheet sections
- 8.9 OUT_X_L_G (28h), OUT_X_H_G (29h)
- 8.10 OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh)
- 8.11 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh)
- 8.12 FIFO_CTRL_REG_G (2Eh)
- 8.13 FIFO_SRC_REG_G (2Fh)
- 8.14 INT1_CFG_G (30h)
- 8.15 INT1_SRC_G (31h)
- 8.16 INT1_THS_XH_G (32h)
- 8.17 INT1_THS_XL_G (33h)
- 8.18 INT1_THS_YH_G (34h)
- 8.19 INT1_THS_YL_G (35h)
- 8.20 INT1_THS_ZH_G (36h)
- 8.21 INT1_THS_ZL_G (37h)
- 8.22 INT1_DURATION_G (38h)
- 8.23 OUT_TEMP_L_XM (05h), OUT_TEMP_H_XM (06h)
- 8.24 STATUS_REG_M (07h)
- 8.25 OUT_X_L_M (08h), OUT_X_H_M (09h)
- 8.26 OUT_Y_L_M (0Ah), OUT_Y_H_M (0Bh)
- 8.27 OUT_Z_L_M (0Ch), OUT_Z_H_M (0Dh)
- 8.28 WHO_AM_I_XM (0Fh)
- 8.29 INT_CTRL_REG_M (12h)
- 8.30 INT_SRC_REG_M (13h)
- 8.31 INT_THS_L_M (14h), INT_THS_H_M (15h)
- 8.32 OFFSET_X_L_M (16h), OFFSET_X_H_M (17h)
- 8.33 OFFSET_Y_L_M (18h), OFFSET_Y_H_M (19h)
- 8.34 OFFSET_Z_L_M (1Ah), OFFSET_Z_H_M (1Bh)
- 8.35 REFERENCE_X (1Ch)
- 8.36 REFERENCE_Y (1Dh)
- 8.37 REFERENCE_Z (1Eh)
- 8.38 CTRL_REG0_XM (1Fh)
- 8.39 CTRL_REG1_XM (20h)
- 8.40 CTRL_REG2_XM (21h)
- 8.41 CTRL_REG3_XM (22h)
Features
3 acceleration channels, 3 angular rate channels, 3 magnetic field channels ±2/±4/±6/±8/±16 g linear acceleration full scale ±2/±4/±8/±12 gauss magnetic full scale ±245/±500/±2000 dps angular rate full scale 16-bit data output SPI / I2C serial interfaces Analog supply voltage 2.4 V to 3.6 V Power-down mode / low-power mode Programmable interrupt generators Embedded self-test Embedded temperature sensor Embedded FIFO Position and motion detection functions Click/double-click recognition Intelligent power saving for handheld devices ECOPACK®, RoHS and “Green” compliant
Applications
Indoor navigation Smart user interfaces Advanced gesture recognition Gaming and virtual reality input devices Display/map orientation and browsing
Description
The LSM9DS0 is a system-in-package featuring a 3D digital linear acceleration sensor, a 3D digital angular rate sensor, and a 3D digital magnetic sensor. The LSM9DS0 has a linear acceleration full scale of ±2g/±4g/±6g/±8g/±16g, a magnetic field full scale of ±2/±4/±8/±12 gauss and an angular rate The LSM9DS0 includes an I 2C serial bus interface supporting standard and fast mode (100 kHz and 400 kHz) and an SPI serial standard interface. The system can be configured to generate interrupt signals on dedicated pins and is capable of motion and magnetic field detection. Thresholds and timing of interrupt generators are programmable by the end user. Magnetic, accelerometer and gyroscope sensing can be enabled or set in power-down mode separately for smart power management. The LSM9DS0 is available in a plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. LGA-24 (4x4x1.0 mm) Table 1. Device summary
Table 7. I
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections
Table 2. Pin description
1 Reserved Leave unconnected
2 Reserved Connect to GND
3 Reserved Connect to GND
4 Reserved Connect to GND
5 GND 0 V supply
6 GND 0 V supply
7 C1_XM Capacitor connection (C1)
8 SETC_XM S/R capacitor connection (C2)
9 SETP_XM S/R capacitor connection (C2)
10 DEN_G Gyroscope data enable
11 INT_G Gyroscope programmable interrupt
12 DRDY_G Gyroscope data ready
13 INT1_XM Accelerometer and magnetic sensor interrupt 1
14 INT2_XM Accelerometer and magnetic sensor interrupt 2
15 Vdd Power supply
16 Vdd Power supply
17 Vdd Power supply
18 Vdd_IO Power supply for I/O pins
19 CS_G
20 CS_XM
21 SCL
22 SDO_G
23 SDO_XM
24 SDA I 2C serial data (SDA)
2 Module specifications
2.1 Sensor characteristics
Table 3. Sensor characteristics
G_TCOff Zero-rate level change vs. Sensitivity starts to degrade.
- Typical specifications are not guaranteed
- Verified by wafer level test and measurement of initial offset and sensitivity
- Typical zero- g level offset value after MSL3 preconditioning
- Offset can be eliminated by enabling the built-in high-pass filter
- Set / Reset Pulse is automatically applied at each conversion cycle
- For polarity refer to Table 77: Self-test mode configuration
- “Self-test output change” is defined as: OUTPUT[mg](CTRL_REG4_G (23h) ST1:0 enabled) - OUTPUT[mg](CTRL_REG4_G (23h)
- For polarity refer to Table 31: Self-test mode configuration
Table 3. Sensor characteristics (continued)
2.2 Temperature sensor characteristics
@ Vdd = 3.0 V, T=25 °C unless otherwise noted. Table 4. Temperature sensor electrical characteristics
8 LSB/°C
- Typical specifications are not guaranteed.
- Refer to Table 84: Magnetic data rate configuration.
2.3 Electrical characteristics
Table 5. Electrical characteristics
- Typical specifications are not guaranteed
- Magnetic sensor setting ODR =6.25 Hz, Accelerometer sensor ODR =50 Hz, gyroscope in power-down mode
- Accelerometer and magnetic sensor in power-down mode
- Sleep mode introduces a faster turn-on time compared to power-down mode. Accelerometer and magnetic sensor in
- Linear accelerometer, magnetic sensor and gyroscope in power-down mode
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram Table 6. SPI slave timing values
- Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
2.4.2 Sensor I 2C - inter-IC control interface
Subject to general operating conditions for Vdd and Top. Figure 4. I2C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Table 7. I2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production.
2.5 Absolute maximum ratings
Table 8. Absolute maximum ratings permanent damage to the part. permanent damage to the part.
3 Terminology
3.1 Set / reset pulse
The set / reset pulse is an automatic operation performed before each magnetic acquisition cycle to degauss the sensor and to ensure alignment of the magnetic dipoles and thus the linearity of the sensor itself.
3.2 Sensitivity
The methods to determine sensitivity and offset are given below in the following paragraphs.
3.2.1 Linear acceleration sensor sensitivity
Sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
3.2.2 Magnetic sensor sensitivity
Sensitivity describes the gain of the sensor and can be determined by applying a magnetic field of 1 gauss to it.
3.2.3 Angular rate sensitivity
An angular rate gyroscope is a device that produces a positive-going digital output for counter-clockwise rotation around the sensitive axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time.
3.2.4 Zero- g level
The zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g for the X-axis and 0 g for the Y-axis whereas the Z-axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature” (LA_TCOff in Table 3). The Zero-g level tolerance (TyOff) describes the standard deviation of the range of Zero-g levels of a population of sensors.
3.2.5 Zero- gauss level
The zero-gauss level offset describes the deviation of an actual output signal from the ideal output if no magnetic field is present. Thanks to the Set/Reset Pulse and to the magnetic sensor readout chain, the offset is dynamically cancelled. The Zero-gauss level does not show any dependency on temperature or power supply.
3.2.6 Zero-rate level
The zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of highly accurate MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time.
4 Functionality
The LSM9DS0 is a system-in-package featuring a 3D digital accelerometer, a 3D digital magnetometer, and a 3D digital gyroscope. The device includes specific sensing elements and two IC interfaces capable of measuring both the acceleration/magnetometer and angular rate applied to the module and to provide a signal to external applications through an SPI/I 2C serial interface. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM9DS0 may also be configured to generate an inertial wake-up and free-fall interrupt signal according to a programmed acceleration event along the enabled axes.
4.1 Self-test
4.1.1 Accelerometer
The self-test allows the linear acceleration sensor functionality to be tested without moving it. The self-test function is off when the self-test bit (ST) is programmed to ‘0’. When the self- test bit is programmed to ‘1’ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Section 2.1: Sensor characteristics, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
4.1.2 Gyroscope
The self-test allows to test the mechanical and electric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. When the ST is activated by the IC, an actuation force is applied to the sensor, emulating a definite Coriolis force. In this case the sensor output will exhibit an output change. When the ST is active, the device output is given by the algebraic sum of the signals produced by the velocity acting on the sensor and by the electrostatic test-force. For polarity please refer to Table 31: Self-test mode configuration.
4.2 Linear acceleration main digital blocks
4.2.1 FIFO
The LSM9DS0 embeds 32 slots of data FIFO for each of the three output channels: X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed
and burst the significant data out from the FIFO. This buffer can work accordingly in four different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FIFO_MODE bits in FIFO_SRC_REG (2Fh). Programmable watermark level, FIFO_Empty or FIFO_Full events can be enabled to generate dedicated interrupts on the INT1_XM/INT2_XM pin (configured through FIFO_SRC_REG (2Fh)).
4.2.2 Bypass mode
In Bypass mode, the FIFO is not operational and for this reason it remains empty. For each channel only the first address is used. The remaining FIFO slots are empty.
4.2.3 FIFO mode
In FIFO mode, data from the X, Y and Z channels are stored in the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit in FIFO_CTRL_REG (2Eh)) in order to be raised when the FIFO is filled to the level specified in the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG (2Eh). The FIFO continues filling until it is full (32 slots of data for X, Y and Z). When full, the FIFO stops collecting data from the input channels.
4.2.4 Stream mode
In Stream mode, data from the X, Y and Z measurements are stored in the FIFO. A watermark interrupt can be enabled and set as in FIFO mode. The FIFO continues filling until it is full (32 slots of data for X, Y and Z). When full, the FIFO discards the older data as the new data arrives.
4.2.5 Stream-to-FIFO mode
In Stream-to-FIFO mode, data from the X, Y and Z measurements is stored in the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit in FIFO_CTRL_REG (2Eh)) in order to be raised when the FIFO is filled to the level specified in the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG (2Eh). The FIFO continues filling until it is full (32 slots of 8-bit data for X, Y and Z). When full, the FIFO discards the older data as the data new arrives. Once a trigger event occurs, the FIFO starts operating in FIFO mode.
4.2.6 Retrieving data from FIFO
A read operation to the OUT_X_L_A (28h), OUT_X_H_A (29h), OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) or OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X_L_A (28h), OUT_X_H_A (29h), OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) and OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) registers and both single read and read_burst operations can be used.
4.3 Gyroscope digital main blocks
Figure 5. Gyroscope block diagram
4.3.1 FIFO
4.3.2 Bypass mode
slots are empty. When new data is available, the old data is overwritten.
Figure 6. Bypass mode
4.3.3 FIFO mode
the FIFO is filled to the level specified in the WTM 4:0 bits of FIFO_CTRL_REG_G (2Eh). FIFO_CTRL_REG_G (2Eh) must be written back to Bypass mode. FIFO mode is represented in Figure 7. Figure 7. FIFO mode
4.3.4 Stream mode
Stream mode is represented in Figure 8. Figure 8. Stream mode
4.3.5 Bypass-to-stream mode
mode. Refer to Figure 9 below. Figure 9. Bypass-to-stream mode
4.3.6 Stream-to-FIFO mode
starts operating in FIFO mode. Refer to Figure 10. Figure 10. Stream-to-FIFO mode
4.3.7 Retrieving data from FIFO
A read operation from the OUT_X_L_G (28h), OUT_X_H_G (29h), OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) or OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest pitch, roll and yaw data are placed in the OUT_X_L_G (28h), OUT_X_H_G (29h), OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) and OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) registers and both single read and read_burst (X,Y & Z with auto-incremental address) operations can be used. When data included in OUT_Z_H_G is read, the system again starts to read information from addr OUT_X_L_G.
4.4 Temperature sensor
The LSM9DS0 features an embedded temperature sensor. Temperature data can be enabled by setting the TEMP_EN bit in the CTRL_REG5_XM (24h) register to 1. Both OUT_TEMP_H_XM and OUT_TEMP_L_XM registers must be read. Temperature data is stored inside OUT_TEMP_L_XM (05h), OUT_TEMP_H_XM (06h) as two’s complement data in 12-bit format, right justified. The output data rate of the temperature sensor is set by M_ODR in CTRL_REG5_XM (24h) and is equal to the magnetic sensor output data rate.
4.5 Factory calibration
The IC interface is factory calibrated. The trimming values are stored inside the non-volatile memory of the device. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during normal operation. This allows the using the device without further calibration.
5 Application hints
Figure 11. LSM9DS0 electrical connections
5.1 External capacitors
capacitance, with the set/reset capacitor C2 nominally 0.22 μF in capacitance. present at the same time to have proper behavior of the IC (refer to Figure 11). INT2_XM) can be completely programmed by the user through the I2C / SPI interfaces.
5.2 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendation are available at www.st.com/mems.
5.3 High current wiring effects
High current in wiring and printed circuit traces can be culprits in causing errors in magnetic field measurements for compassing. Conductor-generated magnetic fields will add to the Earth’s magnetic field leading to errors in compass-heading computation. Keep currents higher than 10 mA a few millimeters further away from the sensor IC.
6 Digital interfaces
CS line must be tied high (i.e connected to Vdd_IO).
6.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. resistors. When the bus is free, both lines are high. Table 9. Serial interface pin description Table 10. I2C terminology
6.1.1 I 2C operation
automatically increased to allow multiple data read/writes. Table 11. Transfer when master is writing one byte to slave Table 12. Transfer when master is writing multiple bytes to slave Table 13. Transfer when master is receiving (reading) one byte of data from slave Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
terminated by the generation of a STOP (SP) condition. address of first register to be read. ‘1’ (ex. address 0011101b) else if SA0 pad is connected to ground, the LSb value is ‘0’ (ex. Table 15. Linear acceleration and magnetic sensor SAD+read/write patterns Table 16. Angular rate SAD+read/write patterns
6.2 SPI bus interface
The SPI is a bus slave. The SPI allows writing and reading the registers of the device. Figure 12. Read and write protocol falling edge of SPC and should be captured at the rising edge of SPC. before the rising edge of CS. from the device is read. In the latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address will be auto-incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. MS bit is 1, the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
6.2.1 SPI read
Figure 13. SPI read protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Figure 14. Multiple byte SPI read protocol (2-byte example)
6.2.2 SPI write
Figure 15. SPI write protocol command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register. Figure 16. Multiple byte SPI write protocol (2-byte example)
6.2.3 SPI read in 3-wire mode
Figure 17. SPI read protocol in 3-wire mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. The multiple read command is also available in 3-wire mode.
7 Register mapping
Table 17. Register address map
Table 17. Register address map (continued)
permanent damage to the device.
8 Register description
write the data through the serial interface.
8.1 WHO_AM_I_G (0Fh)
Device identification register.
8.2 CTRL_REG1_G (20h)
DR[1:0] is used for ODR selection. BW [1:0] is used for Bandwidth selection. In Table 21 all frequencies resulting in combinations of DR / BW bits are given. Table 18. WHO_AM_I_G register Table 19. CTRL_REG1_G register Table 20. CTRL_REG1_G description Table 21. DR and BW configuration setting
normal / sleep mode) in accordance with Table 22 below.
8.3 CTRL_REG2_G (21h)
Table 22. Power mode selection configuration Table 21. DR and BW configuration setting (continued) Table 23. CTRL_REG2_G register
- These bits must be set to ‘0’ to ensure proper operation of the device
Table 24. CTRL_REG2_G description
8.4 CTRL_REG3_G (22h)
Table 25. High-pass filter mode configuration Table 26. High-pass filter cutoff frequency configuration (Hz) Table 27. CTRL_REG3_G register Table 28. CTRL_REG3_G description
8.5 CTRL_REG4_G (23h)
8.6 CTRL_REG5_G (24h)
Table 29. CTRL_REG4_G register Table 30. CTRL_REG4_G description BLE Big/little endian data selection. Default value 0. (0: 4-wire interface; 1: 3-wire interface). Table 31. Self-test mode configuration
- DST sign (absolute value in Table 3)
Table 32. CTRL_REG5_G register Table 33. CTRL_REG5_G description
Figure 18. INT1_Sel and Out_Sel configuration block diagram
8.7 REFERENCE/DATACAPTURE_G (25h)
8.8 STATUS_REG_G (27h)
Table 34. REFERENCE/DATACAPTURE_G register Table 35. REFERENCE/DATACAPTURE_G description Table 36. STATUS_REG_G register Table 37. STATUS_REG_G description
8.9 OUT_X_L_G (28h), OUT_X_H_G (29h)
X-axis angular rate data. The value is expressed as two’s complement.
8.10 OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh)
Y-axis angular rate data. The value is expressed as two’s complement.
8.11 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh)
Z-axis angular rate data. The value is expressed as two’s complement.
8.12 FIFO_CTRL_REG_G (2Eh)
Table 37. STATUS_REG_G description (continued) Table 38. FIFO_CTRL_REG_G register Table 39. FIFO_CTRL_REG_G description Table 40. FIFO mode configuration
8.13 FIFO_SRC_REG_G (2Fh)
8.14 INT1_CFG_G (30h)
Table 41. FIFO_SRC_REG_G register Table 42. FIFO_SRC_REG_G description Table 43. INT1_CFG_G register Table 44. INT1_CFG_G description Cleared by reading INT1_SRC reg.
8.15 INT1_SRC_G (31h)
Interrupt source register. Read-only register.
8.16 INT1_THS_XH_G (32h)
Table 44. INT1_CFG_G description (continued) Table 45. INT1_SRC_G register
0 I A Z HZ LY HY LX HX L
Table 46. INT1_SRC_G description Table 47. INT1_THS_XH_G register Table 48. INT1_THS_XH_G description
8.17 INT1_THS_XL_G (33h)
8.18 INT1_THS_YH_G (34h)
8.19 INT1_THS_YL_G (35h)
8.20 INT1_THS_ZH_G (36h)
Table 49. INT1_THS_XL_G register Table 50. INT1_THS_XL_G description Table 51. INT1_THS_YH_G register Table 52. INT1_THS_YH_G description Table 53. INT1_THS_YL_G register Table 54. INT1_THS_YL_G description Table 55. INT1_THS_ZH_G register Table 56. INT1_THS_ZH_G description
8.21 INT1_THS_ZL_G (37h)
8.22 INT1_DURATION_G (38h)
steps and maximum values depend on the ODR chosen. Table 57. INT1_THS_ZL_G register Table 58. INT1_THS_ZL_G description Table 59. INT1_DURATION_G register Table 60. INT1_DURATION_G description
8.23 OUT_TEMP_L_XM (05h), OUT_TEMP_H_XM (06h)
temperature sensor output data.
8.24 STATUS_REG_M (07h)
8.25 OUT_X_L_M (08h), OUT_X_H_M (09h)
The value is expressed in 16-bit as two’s complement left justified.
8.26 OUT_Y_L_M (0Ah), OUT_Y_H_M (0Bh)
-bit as two’s complement left justified. Table 61. STATUS_REG_M register Table 62. STATUS_REG_M description (0: no overrun has occurred; 1: a new set of data has overwritten the previous ones). (0: a new set of data is not yet available; 1: a new set of data is available).
8.27 OUT_Z_L_M (0Ch), OUT_Z_H_M (0Dh)
The value is expressed in 16-bit as two’s complement left justified.
8.28 WHO_AM_I_XM (0Fh)
Device identification register.
8.29 INT_CTRL_REG_M (12h)
Table 63. WHO_AM_I_XM register Table 64. INT_CTRL_REG_M register Table 65. INT_CTRL_REG_M description XMIEN Enable interrupt recognition on X-axis for magnetic data. Default value: 0. YMIEN Enable interrupt recognition on Y-axis for magnetic data. Default value: 0. ZMIEN Enable interrupt recognition on Z-axis for magnetic data. Default value: 0. PP_OD Interrupt pin configuration. Default value: 0. IEA Interrupt polarity for both accelerometer and magnetometer. Default value: 0. (35h) registers, and magnetometer INT_SRC_REG_M (13h) register. Default value: 0. ter the INT_SRC_REG_M (13h) register. INT_GEN_1_REG (30h) is set to 1. MIEN Enable interrupt generation for magnetic data. Default value: 0.
8.30 INT_SRC_REG_M (13h)
8.31 INT_THS_L_M (14h), INT_THS_H_M (15h)
Magnetic interrupt threshold. Default value: 0. The value is expressed in 16-bit unsigned.
8.32 OFFSET_X_L_M (16h), OFFSET_X_H_M (17h)
Magnetic offset for X-axis. Default value: 0. The value is expressed in 16-bit as two’s complement left justified.
8.33 OFFSET_Y_L_M (18h), OFFSET_Y_H_M (19h)
Magnetic offset for Z-axis. Default value: 0. The value is expressed in 16-bit as two’s complement left justified.
8.34 OFFSET_Z_L_M (1Ah), OFFSET_Z_H_M (1Bh)
Magnetic offset for Y-axis. Default value: 0. The value is expressed in 16-bit as two’s complement left justified. Table 66. INT_SRC_REG_M register Table 67. INT_SRC_REG_M description M_PTH_X Magnetic value on X-axis exceeds the threshold on the positive side. Default value: 0. M_PTH_Y Magnetic value on Y-axis exceeds the threshold on the positive side. Default value: 0. M_PTH_Z Magnetic value on Z-axis exceeds the threshold on the positive side. Default value: 0. M_NTH_X Magnetic value on X-axis exceeds the threshold on the negative side. Default value: 0. M_NTH_Y Magnetic value on Y-axis exceeds the threshold on the negative side. Default value: 0. M_NTH_Z Magnetic value on Z-axis exceeds the threshold on the negative side. Default value: 0. MROI Internal measurement range overflow on magnetic value. Default value: 0.
8.35 REFERENCE_X (1Ch)
Reference value for high-pass filter for x-axis acceleration data.
8.36 REFERENCE_Y (1Dh)
Reference value for high-pass filter for y-axis acceleration data.
8.37 REFERENCE_Z (1Eh)
Reference value for high-pass filter for z-axis acceleration data.
8.38 CTRL_REG0_XM (1Fh)
8.39 CTRL_REG1_XM (20h)
Table 68. CTRL_REG0_XM register
- These bits must be set to ‘0’ for the correct operation of the device
Table 69. CTRL_REG0_XM description Table 70. CTRL_REG1_XM register
all frequencies resulting from the combination of AODR[3:0].
8.40 CTRL_REG2_XM (21h)
Table 71. CTRL_REG1_XM description Table 72. Acceleration data rate configuration Table 73. CTRL_REG2_XM register
8.41 CTRL_REG3_XM (22h)
Table 74. CTRL_REG2_XM description Table 75. Acceleration anti-alias filter bandwidth Table 76. Acceleration full-scale selection Table 77. Self-test mode configuration Table 78. CTRL_REG3_XM register
8.42 CTRL_REG4_XM (23h)
Table 79. CTRL_REG3_XM description Table 80. CTRL_REG4_XM register Table 81. CTRL_REG4_XM description
8.43 CTRL_REG5_XM (24h)
8.44 CTRL_REG6_XM (25h)
Table 82. CTRL_REG5_XM register Table 83. CTRL_REG5_XM description reading INT2_SRC itself. Default value: 0. reading INT1_SRC itself. Default value: 0. Table 84. Magnetic data rate configuration
- Available only for accelerometer ODR > 50 Hz or accelerometer in power-down mode (refer to Table 72,
Table 85. CTRL_REG6_XM register
- These bits must be set to ‘0’ for the correct operation of the device
8.45 CTRL_REG7_XM (26h)
Table 86. CTRL_REG6_XM description Table 87. Magnetic full-scale selection Table 88. CTRL_REG7_XM register
- These bits must be set to ‘0’ for the correct operation of the device
Table 89. CTRL_REG7_XM description If this bit is ‘1’ the MODR is set to 3.125 Hz independently from the MODR settings. CTRL_REG5_XM (24h) register. Table 90. High-pass filter mode selection
8.46 STATUS_REG_A (27h)
8.47 OUT_X_L_A (28h), OUT_X_H_A (29h)
The value is expressed in 16 bit as two’s complement left justified. Table 91. Magnetic sensor mode selection Table 92. STATUS_REG_A register Table 93. STATUS_REG_A description
8.48 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh)
The value is expressed in 16-bit as two’s complement left justified.
8.49 OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh)
The value is expressed in 16-bit as two’s complement left justified.
8.50 FIFO_CTRL_REG (2Eh)
Interrupt generator 2 can change the FIFO mode.
8.51 FIFO_SRC_REG (2Fh)
Table 94. FIFO_CTRL_REG register Table 95. FIFO_CTRL_REG description Table 96. FIFO mode configuration Table 97. FIFO_SRC_REG register Table 98. FIFO_SRC_REG description WTM bit is set to ‘1’ when FIFO content exceeds watermark level. OVRN bit is set to ‘1’ when FIFO buffer is full.
8.52 INT_GEN_1_REG (30h)
This register contains the settings for the inertial interrupt generator 1. EMPTY bit is set to ‘1’ when all FIFO samples have been read and FIFO is empty. FSS4-FSS0 FIFO stored data level. FSS4-FSS0 bits contain the current number of unread FIFO levels. Table 98. FIFO_SRC_REG description (continued) Table 99. INT_GEN_1_REG register Table 100. INT_GEN_1_REG description Table 101. Interrupt mode
inside a known zone. The interrupt signal stays until the orientation is inside the zone.
8.53 INT_GEN_1_SRC (31h)
This register contains the status for the inertial interrupt generator 1. INT_GEN_1_SRC (31h) register if the latched option was chosen.
8.54 INT_GEN_1_THS (32h)
Table 102. INT_GEN_1_SRC register Table 103. INT_GEN_1_SRC description Table 104. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 105. INT1_THS description
8.55 INT_GEN_1_DURATION (33h)
The D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. Duration steps and maximum values depend on the ODR chosen.
8.56 INT_GEN_2_REG (34h)
This register contains the settings for the inertial interrupt generator 2. Table 106. INT1_DURATION register
0 D 6D 5D 4D 3D 2D 1D 0
Table 107. INT1_DURATION description Table 108. INT_GEN_2_REG register Table 109. INT_GEN_2_REG description
inside a known zone. The interrupt signal stays until the orientation is inside the zone.
8.57 INT_GEN_2_SRC (35h)
This register contains the status for the inertial interrupt generator 2. INT_GEN_2_SRC (35h) register if the latched option was chosen. Table 110. Interrupt mode Table 111. INT_GEN_2_SRC register Table 112. INT_GEN_2_SRC description
8.58 INT_GEN_2_THS (36h)
8.59 INT_GEN_2_DURATION (37h)
The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen.
8.60 CLICK_CFG (38h)
Table 113. INT_GEN_2_THS register Table 114. INT_GEN_2_THS description Table 115. INT_GEN_2_DURATION register Table 116. INT_GEN_2_DURATION description Table 117. CLICK_CFG register Table 118. CLICK_CFG description
8.61 CLICK_SRC (39h)
8.62 CLICK_THS (3Ah)
Table 119. CLICK_SRC register Table 120. CLICK_SRC description Table 121. CLICK_THS register Table 122. CLICK_SRC description
8.63 TIME_LIMIT (3Bh)
8.64 TIME_LATENCY (3Ch)
8.65 TIME WINDOW (3Dh)
8.66 Act_THS (3Eh)
Table 123. TIME_LIMIT register Table 124. TIME_LIMIT description Table 125. TIME_LATENCY register Table 126. TIME_LATENCY description Table 127. TIME_WINDOW register Table 128. TIME_WINDOW description Table 129. TIME_WINDOW register Table 130. TIME_WINDOW description
1 LSb = 16 mg
8.67 Act_DUR (3Fh)
Table 131. Act_DUR register Table 132. Act_DUR description
9 Package information
specifications, grade definitions and product status are available at: www.st.com. Note: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
- All dimensions are in millimeters.
- The “Pin 1 Indicator” is identified on top and/or bottom surfaces of the package.
- A1 is defined as the distance from the seating plane to the land.
- “N” is the maximum number of terminal positions for the specified body size.
- The tolerance of the typical value is specified in table "Tolerance of Form and Position".
- Dimensions “b” and “L” are specified:
Table 133. LGA 4x4x1 mm 24-lead mechanical data (see note 1 and 2)
Figure 21. LGA 4x4x1 mm 24-lead outline
Table 134. Document revision history