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Document overview
- PDF pages: 153
Technical content
Datasheet sections
- 1 Overview
- 2 Embedded low-power features
- 2.1 Tilt detection
- 2.2 Significant Motion Detection
- 2.3 Finite State Machine
- 3 Pin description
- 3.1 Pin connections
- 4 Module specifications
- 4.1 Mechanical characteristics
- 4.2 Electrical characteristics
- 4.3 Temperature sensor characteristics
- 4.4 Communication interface characteristics
- 4.4.1 SPI - serial peripheral interface
- 4.4.2 I²C - inter-IC control interface
- 4.5 Absolute maximum ratings
- 4.6 Terminology
- 4.6.1 Sensitivity
- 4.6.2 Zero-g and zero-rate level
- 5 Digital interfaces
- 5.1 I²C/SPI interface
- 5.1.1 I²C serial interface
- 5.1.2 SPI bus interface
- 5.2 MIPI I3C SM interface
- 5.2.1 MIPI I3C SM slave interface
- 5.2.2 MIPI I3C SM CCC supported commands
- 5.3 I²C/MIPI I3C SM coexistence in LSM6DSO32
- 5.4 Master I²C interface
- 6 Functionality
Datasheet sections
- 9.13 CTRL2_G (11h)
- 9.14 CTRL3_C (12h)
- 9.15 CTRL4_C (13h)
- 9.16 CTRL5_C (14h)
- 9.17 CTRL6_C (15h)
- 9.18 CTRL7_G (16h)
- 9.19 CTRL8_XL (17h)
- 9.20 CTRL9_XL (18h)
- 9.21 CTRL10_C (19h)
- 9.22 ALL_INT_SRC (1Ah)
- 9.23 WAKE_UP_SRC (1Bh)
- 9.24 TAP_SRC (1Ch)
- 9.25 D6D_SRC (1Dh)
- 9.26 STATUS_REG (1Eh)
- 9.27 OUT_TEMP_L (20h), OUT_TEMP_H (21h)
- 9.28 OUTX_L_G (22h) and OUTX_H_G (23h)
- 9.29 OUTY_L_G (24h) and OUTY_H_G (25h)
- 9.30 OUTZ_L_G (26h) and OUTZ_H_G (27h)
- 9.31 OUTX_L_A (28h) and OUTX_H_A (29h)
- 9.32 OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
- 9.33 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
- 9.34 EMB_FUNC_STATUS_MAINPAGE (35h)
- 9.35 FSM_STATUS_A_MAINPAGE (36h)
- 9.36 FSM_STATUS_B_MAINPAGE (37h)
- 9.37 STATUS_MASTER_MAINPAGE (39h)
- 9.38 FIFO_STATUS1 (3Ah)
- 9.39 FIFO_STATUS2 (3Bh)
- 9.40 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h),
- 9.41 TAP_CFG0 (56h)
- 9.42 TAP_CFG1 (57h)
- 9.43 TAP_CFG2 (58h)
- 9.44 TAP_THS_6D (59h)
Datasheet sections
- 11.16 EMB_FUNC_FIFO_CFG (44h)
- 11.17 FSM_ENABLE_A (46h)
- 11.18 FSM_ENABLE_B (47h)
- 11.19 FSM_LONG_COUNTER_L (48h) and
- 11.20 FSM_LONG_COUNTER_CLEAR (4Ah)
- 11.21 FSM_OUTS1 (4Ch)
- 11.22 FSM_OUTS2 (4Dh)
- 11.23 FSM_OUTS3 (4Eh)
- 11.24 FSM_OUTS4 (4Fh)
- 11.25 FSM_OUTS5 (50h)
- 11.26 FSM_OUTS6 (51h)
- 11.27 FSM_OUTS7 (52h)
- 11.28 FSM_OUTS8 (53h)
- 11.29 FSM_OUTS9 (54h)
- 11.30 FSM_OUTS10 (55h)
- 11.31 FSM_OUTS11 (56h)
- 11.32 FSM_OUTS12 (57h)
- 11.33 FSM_OUTS13 (58h)
- 11.34 FSM_OUTS14 (59h)
- 11.35 FSM_OUTS15 (5Ah)
- 11.36 FSM_OUTS16 (5Bh)
- 11.37 EMB_FUNC_ODR_CFG_B (5Fh)
- 11.38 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h)
- 11.39 EMB_FUNC_SRC (64h)
- 11.40 EMB_FUNC_INIT_A (66h)
- 11.41 EMB_FUNC_INIT_B (67h)
- 12 Embedded advanced features pages
- 13 Embedded advanced features register description
- 13.1 Page 0 - Embedded advanced features registers
- 13.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh)
- 13.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h)
Datasheet sections
- 15.15 SENSOR_HUB_15 (10h)
- 15.16 SENSOR_HUB_16 (11h)
- 15.17 SENSOR_HUB_17 (12h)
- 15.18 SENSOR_HUB_18 (13h)
- 15.19 MASTER_CONFIG (14h)
- 15.20 SLV0_ADD (15h)
- 15.21 SLV0_SUBADD (16h)
- 15.22 SLAVE0_CONFIG (17h)
- 15.23 SLV1_ADD (18h)
- 15.24 SLV1_SUBADD (19h)
- 15.25 SLAVE1_CONFIG (1Ah)
- 15.26 SLV2_ADD (1Bh)
- 15.27 SLV2_SUBADD (1Ch)
- 15.28 SLAVE2_CONFIG (1Dh)
- 15.29 SLV3_ADD (1Eh)
- 15.30 SLV3_SUBADD (1Fh)
- 15.31 SLAVE3_CONFIG (20h)
- 15.32 DATAWRITE_SLV0 (21h)
- 15.33 STATUS_MASTER (22h)
- 16 Soldering information
- 17 Package information
- 17.1 LGA-14L package information
- 17.2 LGA-14 packing information
- 18 Revision history
Features
Power consumption: 0.55 mA in combo high- performance mode “Always-on" experience with low power consumption for both accelerometer and gyroscope Smart FIFO up to 9 kbytes ±4/±8/±16/±32 g full scale ±125/±250/±500/±1000/±2000 dps full scale Analog supply voltage: 1.71 V to 3.6 V Independent IO supply (1.62 V) Compact footprint: 2.5 mm x 3 mm x 0.83 mm SPI / I²C & MIPI I3CSM serial interface with main processor data synchronization Advanced pedometer, step detector and step counter Significant Motion Detection, Tilt detection Standard interrupts: free-fall, wakeup, 6D/4D orientation, click and double-click Programmable finite state machine: accelerometer, gyroscope and external sensors Embedded temperature sensor ECOPACK, RoHS and “Green” compliant
Applications
Wearables, smart watches, and sports equipment Motion tracking and gesture detection Hard fall detection Sensor hub Navigation IoT and connected devices Smart power saving for handheld devices
Description
The LSM6DSO32 is a system-in-package featuring a 3D digital accelerometer and 3D digital gyroscope boosting power performance to 0.55 mA in high- performance mode and enabling always-on low-power features for an optimal motion experience for the consumer. The LSM6DSO32 supports main OS requirements, offering real, virtual and batch sensors with 9 kbytes for dynamic data batching. ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The LSM6DSO32 has a full-scale acceleration range of ±4/±8/±16±32 g and an angular rate range of High robustness to mechanical shock makes the LSM6DSO32 the preferred choice of system designers for the creation and manufacturing of reliable products. The LSM6DSO32 is available in a plastic land grid array (LGA) package. LGA-14L (2.5 x 3 x 0.83 mm) typ. Table 1. Device summary
1 Overview
The LSM6DSO32 is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. The LSM6DSO32 delivers best-in-class motion sensing that can detect orientation and gestures in order to empower application developers and consumers with features and capabilities that are more sophisticated than simply orienting their devices to portrait and landscape mode. The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness, implementing hardware recognition of free-fall events, 6D orientation, click and double-click sensing, activity or inactivity, stationary/motion detection and wakeup events. The LSM6DSO32 supports main OS requirements, offering real, virtual and batch mode sensors. In addition, the LSM6DSO32 can efficiently run the sensor-related features specified in Android, saving power and enabling faster reaction time. In particular, the LSM6DSO32 has been designed to implement hardware features such as significant motion detection, stationary/motion detection, tilt, pedometer functions, timestamping and to support the data acquisition of an external magnetometer. The LSM6DSO32 offers hardware flexibility to connect the pins with different mode connections to external sensors to expand functionalities such as adding a sensor hub, etc. Up to 9 kbytes of FIFO with compression and dynamic allocation of significant data (i.e. external sensors, timestamp, etc.) allows overall power saving of the system. Like the entire portfolio of MEMS sensor modules, the LSM6DSO32 leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The LSM6DSO32 is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm to address ultra-compact solutions.
LSM6DSO32 Embedded low-power features 153
2 Embedded low-power features
The LSM6DSO32 has been designed to be fully compliant with Android, featuring the following on-chip functions: 9 kbytes data buffering, data can be compressed two or three times – 100% efficiency with flexible configurations and partitioning – Possibility to store timestamp Event-detection interrupts (fully configurable): – Free-fall – Wakeup – 6D orientation – Click and double-click sensing – Activity/inactivity recognition – Stationary/Motion detection Specific IP blocks with negligible power consumption and high-performance: – Pedometer functions: step detector and step counters – Tilt – Significant Motion Detection – Finite State Machine (FSM) for accelerometer, gyroscope, and e xternal sensors Sensor hub – Up to 6 total sensors: 2 internal (accelerometer and gyroscope ) and 4 external sensors
Embedded low-power features LSM6DSO32
2.1 Tilt detection
The tilt function helps to detect activity change and has been implemented in hardware using only the accelerometer to achieve targets of both ultra-low power consumption and robustness during the short duration of dynamic accelerations. The tilt function is based on a trigger of an event each time the device's tilt changes and can be used with different scenarios, for example: a) Triggers when phone is in a front pants pocket and the user goes from sitting to standing or standing to sitting; b) Doesn’t trigger when phone is in a front pants pocket and th e user is walking, running or going upstairs.
2.2 Significant Motion Detection
The Significant Motion Detection (SMD) function generates an interrupt when a ‘significant motion’, that could be due to a change in user location, is detected. In the LSM6DSO32 device this function has been implemented in hardware using only the accelerometer. SMD functionality can be used in location-based applications in order to receive a notification indicating when the user is changing location.
2.3 Finite State Machine
The LSM6DSO32 can be configured to generate interrupt signals activated by user-defined motion patterns. To do this, up to 16 embedded finite state machines can be programmed independently for motion detection such as glance gestures, absolute wrist tilt, shake and double-shake detection. Definition of Finite State Machine A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model composed of a finite number of states and transitions between states, similar to a flow chart in which one can inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to different states through transitions dependent on the inputs, and can finally end in a specific state (called stop state). The current state is determined by the past states of the system. Figure 1: Generic state machine shows a generic state machine.
3 Pin description
Figure 3. Pin connections
- Leave pin electrically unconnected and soldered to PCB.
3.1 Pin connections
interface master for external sensor connections are available. Figure 4. LSM6DSO32 connection modes In the following table each mode is described for the pin connections and function.
Table 2. Pin description
2 SDx Connect to VDDIO or GND I²C serial data master (MSDA)
3 SCx Connect to VDDIO or GND I²C serial clock master (MSCL)
4 INT1
this pin must be set to ‘1’.
5 VDDIO (1) Power supply for I/O pins
6 GND 0 V supply
7 GND 0 V supply
8 VDD
9 INT2 Programmable interrupt 2
10 NC Leave unconnected (2) Leave unconnected(2)
11 NC Leave unconnected (2) Leave unconnected(2)
13 SCL I²C/MIPI I3CSM serial clock (SCL)
14 SDA
- Recommended 100 nF filter capacitor.
- Leave pin electrically unconnected and soldered to PCB.
4 Module specifications
4.1 Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted. Table 3. Mechanical characteristics G_SoDr Angular rate sensitivity change vs.
- Typical specifications are not guaranteed.
- Sensitivity values after factory calibration test and trimmin g.
Table 3. Mechanical characteristics (continued)
LSM6DSO32 Module specifications 153 3. Subject to change. 4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production. 5. Values after factory calibration test and trimming. 6. Gyroscope rate noise density in high-performance mode is inde pendent of the ODR and FS setting. 7. Gyroscope RMS noise in normal/low-power mode is independent o f the ODR and FS setting. 8. Accelerometer noise density in high-performance mode is indep endent of the ODR. 9. Accelerometer RMS noise in normal/low-power/ultra-low-power m ode is independent of the ODR. 10. Noise RMS related to BW = ODR/2. 11. This ODR is available when the accelerometer is in low-power mode. 12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes. 13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.122 mg at ±4 g full scale. 14. Accelerometer self-test limits are full-scale independent. 15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes. 16. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale.
4.2 Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted. Table 4. Electrical characteristics
- T ypical specifications are not guaranteed.
- 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pin in order to
guarantee the correct digital output voltage levels VOH and VOL.
4.3 Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. Table 5. Temperature sensor characteristics
- Typical specifications are not guaranteed.
- When the accelerometer is in low-power mode or ultra-low-powe r mode and the gyroscope part is turned
off, the TODR value is equal to the accelerometer ODR.
- The output of the temperature sensor is 0 LSB (typ.) at 25 °C .
- Time from power ON to valid data based on characterization da ta.
4.4 Communication interface characteristics
4.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 5. SPI slave timing diagram (in mode 3) Table 6. SPI slave timing values (in mode 3)
- Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
4.4.2 I ²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top. Figure 6. I²C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Table 7. I²C slave timing values
- Data based on standard I²C protocol requirement, not tested i n production.
4.5 Absolute maximum ratings
Note: Supply voltage on any pin should never exceed 4.8 V. Table 8. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
LSM6DSO32 Module specifications 153
4.6 Terminology
4.6.1 Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors (see Table 3). An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see Table 3).
4.6.2 Zero- g and zero-rate level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 3. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors. Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time (see Table 3).
5 Digital interfaces
5.1 I ²C/SPI interface
interface mode. The device is compatible with SPI modes 0 and 3. CS line must be tied high (i.e connected to Vdd_IO).
5.1.1 I ²C serial interface
whose content can also be read back. The relevant I²C terminology is provided in the table below. resistors. When the bus is free, both the lines are high. In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h). Table 9. Serial interface pin description
connect and address two different inertial modules to the same I²C bus. slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted. The increment of the address is configured by the CTRL3_C (12h) (IF_INC). SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 11. SAD+Read/Write patterns Table 12. Transfer when master is writing one byte to slave Table 13. Transfer when master is writing multiple bytes to slave
terminated by the generation of a STOP (SP) condition. Table 14. Transfer when master is receiving (reading) one byte of data from slave Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
5.1.2 SPI bus interface
The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO. Figure 7. Read and write protocol (in mode 3) falling edge of SPC and should be captured at the rising edge of SPC. from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
Figure 12. SPI read protocol in 3-wire mode (in mode 3) bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode.
5.2 MIPI I3C SM interface
5.2.1 MIPI I3C SM slave interface
choice of the interface when powering up the device.
5.2.2 MIPI I3C SM CCC supported commands
Table 16. MIPI I3CSM CCC commands
5.3 I²C/MIPI I3C SM coexistence in LSM6DSO32
Figure 13. I²C and MIPI I3CSM both active (INT1 pin not connected)
- Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave
is addressed, the I²C slave is disabled and the timing is compatible with MIPI I3CSM specifications. Figure 14. Only MIPI I3CSM active (INT1 pin connected to VDD_IO)
- When the slave is MIPI I3C SM only, the I²C slave is always disabled. The address can be assigned using
5.4 Master I ²C interface
interface is mapped in the following dedicated pins. Table 17. Master I²C pin details
6 Functionality
6.1 Operating modes
In the LSM6DSO32, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes. The LSM6DSO32 has three operating modes available: only accelerometer active and gyroscope in power-down only gyroscope active and accelerometer in power-down both accelerometer and gyroscope sensors active with independent ODR The accelerometer is activated from power-down by writing ODR_XL[3:0] in CTRL1_XL (10h) while the gyroscope is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h). For combo-mode the ODRs are totally independent.
6.2 Accelerometer power modes
In the LSM6DSO32, the accelerometer can be configured in five different operating modes: power-down, ultra-low-power, low-power, normal mode and high-performance mode. The operating mode selected depends on the value of the XL_HM_MODE bit in CTRL6_C (15h). If XL_HM_MODE is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz). To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Low- power mode is available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
6.2.1 Accelerometer ultra-low-power mode
The LSM6DSO32 can be configured in ultra-low-power (ULP) mode by setting the XL_ULP_EN bit to 1 in CTRL5_C (14h) register. This mode can be used in accelerometer- only mode (gyroscope sensor must be configured in power-down mode) and for ODR_XL values between 1.6 Hz and 208 Hz. When ULP mode is intended to be used, the bit XL_HM_MODE must be set to 0. When ULP mode is switched ON/OFF, the accelerometer must be configured in power- down condition. The embedded functions based on accelerometer data (free-fall, 6D/4D, tap, double-tap, wake-up, activity/inactivity, stationary/motion, step-counter, step-detection, significant motion, tilt) and the FIFO batching functionality are still supported when ULP mode is enabled.
6.3 Gyroscope power modes
is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz). for ODRs equal to 104 and 208 Hz.
6.4 Block diagram of filters
Figure 15. Block diagram of filters
6.4.1 Block diagrams of the accelerometer filters
Details of the block diagram appear in the following figure. Figure 16. Accelerometer chain
Figure 17. Accelerometer composite filter
- The cutoff value of the LPF1 output is ODR/2 when the acceler ometer is in high-performance mode. This
value is equal to 700 Hz when the accelerometer is in low-power or normal mode. detection, tilt functions and Finite State Machine.
6.4.2 Block diagrams of the gyroscope filters
Figure 18. Gyroscope digital chain - Mode 1 and Mode 2 the selected gyroscope ODR, as indicated in the following table. Table 18. Gyroscope LPF2 bandwidth selection
6.5 FIFO
The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out from the FIFO. The LSM6DSO32 embeds 3 kbytes of data in FIFO (up to 9 kbytes with the compression feature enabled) to store the following data: Gyroscope Accelerometer External sensors (up to 4) Step counter Timestamp Temperature Writing data in the FIFO can be configured to be triggered by the: Accelerometer / gyroscope data-ready signal Sensor hub data-ready signal Step detection signal The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFO-dedicated configurations: accelerometer, gyroscope and temperature sensor batching rates can be selected by the user. External sensor writing in FIFO can be triggered by the accelerometer data-ready signal or by an external sensor interrupt. The step counter can be stored in FIFO with associated timestamp each time a step is detected. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32. The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows recognizing the meaning of a word in FIFO. FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the ODR or BDR (Batching Data Rate) configuration is performed, the application can correctly reconstruct the timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores information of the new configuration and timestamp in which the change was applied in the device. Finally, FIFO embeds a compression algorithm that the user can enable in order to have up to 9 kbyte data stored in FIFO and take advantage of interface communication length for FIFO flushing and communication power consumption. The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) using the WTM[8:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh)) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh).
The FIFO buffer can be configured according to six different modes: Bypass mode FIFO mode Continuous mode Continuous-to-FIFO mode Bypass-to-continuous mode Bypass-to-FIFO mode Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register.
6.5.1 Bypass mode
In Bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
6.5.2 FIFO mode
In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the FIFO until it is full. To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to '000'. After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to '001'. The FIFO buffer memorizes up to 9 kbytes of data (with compression enabled) but the depth of the FIFO can be resized by setting the WTM [8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). If the STOP_ON_WTM bit in FIFO_CTRL2 (08h) is set to '1', FIFO depth is limited up to the WTM [8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h).
6.5.3 Continuous mode
Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new data arrives, the older data is discarded. A FIFO threshold flag FIFO_STATUS2 (3Bh)(FIFO_WTM_IA) is asserted when the number of unread samples in FIFO is greater than or equal to FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)(WTM [8:0]). It is possible to route the FIFO_WTM_IA flag to the INT1 pin by writing in register INT1_CTRL (0Dh)(INT1_FIFO_TH) = '1' or to the INT2 pin by writing in register INT2_CTRL (0Eh)(INT2_FIFO_TH) = '1'. A full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT1_FIFO_FULL) = '1' or INT2_CTRL (0Eh)(INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and eventually read its content all at once. If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag in FIFO_STATUS2 (3Bh) is asserted. In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available inFIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)(DIFF_FIFO_[9:0]).
6.5.4 Continuous-to-FIFO mode
In Continuous-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 011), FIFO behavior changes according to the trigger event detected in one of the following interrupt events: Single tap Double tap Wake-up Free-fall D6D When the selected trigger bit is equal to '1', FIFO operates in FIFO mode. When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
6.5.5 Bypass-to-Continuous mode
In Bypass-to-Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '100'), data measurement storage inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode). FIFO behavior changes according to the trigger event detected in one of the following interrupt events: Single tap Double tap Wake-up Free-fall D6D
6.5.6 Bypass-to-FIFO mode
In Bypass-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '111'), data measurement storage inside FIFO operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode). FIFO behavior changes according to the trigger event detected in one of the following interrupt events: Single tap Double tap Wake-up Free-fall D6D
6.5.7 FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes: one tag byte (FIFO_DATA_OUT_TAG (78h), in order to identify the sensor, and 6 bytes of fixed data (FIFO_DATA_OUT registers from (79h) to (7Eh)). The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) registers contains the number of words (1 byte TAG + 6 bytes DATA) collected in FIFO. In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors. The flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the counter reaches a selectable threshold (CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using the TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits (INT1_CNT_BDR of INT1_CTRL (0Dh) and INT2_CNT_BDR of INT2_CTRL (0Eh)). In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can enable the compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in EMB_FUNC_EN_B (05h) (embedded functions registers bank) and the FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h). When compression is enabled, it is also possible to force writing non-compressed data at a selectable rate using the UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h). Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling the ODR_CHG_EN bit in FIFO_CTRL2 (08h).
7 Application hints
7.1 LSM6DSO32 electrical connections in Mode 1
Figure 19. LSM6DSO32 electrical connections in Mode 1
- Leave pin electrically unconnected and soldered to PCB.
selectable and accessible through the SPI/I²C/MIPI I3CSM interface. completely programmed by the user through the SPI/I²C/MIPI I3CSM interface.
7.2 LSM6DSO32 electrical connections in Mode 2
Figure 20. LSM6DSO32 electrical connections in Mode 2
- Leave pin electrically unconnected and soldered to PCB.
selectable and accessible through the SPI/I²C/MIPI I3CSM primary interface. completely programmed by the user through the SPI/I²C/MIPI I3CSM primary interface.
Table 19. Internal pin status
2 SDx Connect to VDDIO or
3 SCx Connect to VDDIO or
5 VDDIO Power supply
6 GND 0 V supply 0 V supply
7 GND 0 V supply 0 V supply
8 VDD Power supply Power supply
9 INT2
10 NC Leave unconnected Leave unconnected Default:
11 NC Connect to VDDIO or
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on VDDIO.
- Write 40h in register at address 01h (enable access to the sensor hub registers)
- Write 08h in register at address 14h (enable the pull-up on pins 2 and 3)
- Write 00h in register at address 01h (disable access to the sensor hub registers)
13 SCL
- INT1 must be set to '0' or left unconnected during power-on i f the I²C/SPI interfaces are used.
Table 19. Internal pin status (continued)
8 Register mapping
the corresponding addresses. Table 20. Registers address map
Table 20. Registers address map (continued)
9 Register description
7 bits, are used to identify them and to write the data through the serial interface.
9.1 FUNC_CFG_ACCESS (01h)
Table 22. FUNC_CFG_ACCESS register description
9.2 PIN_CTRL (02h)
Table 24. PIN_CTRL register description Table 21. FUNC_CFG_ACCESS register
- This bit must be set to '0' for the correct operation of the device.
Enable access to the embedded functions configuration registers.
- Details concerning the embedded functions configuration regis ters are available in Section 10: Embedded
functions register mapping and Section 11: Embedded functions register description . Enable access to the sensor hub (I²C master) registers.
- Details concerning the sensor hub registers are available in Section 14: Sensor hub register mapping and
Section 15: Sensor hub register description . Table 23. PIN_CTRL register
- This bit must be set to '0' for the correct operation of the device.
- This bit must be set to '1' for the correct operation of the device.
9.3 FIFO_CTRL1 (07h)
Table 26. FIFO_CTRL1 register description
9.4 FIFO_CTRL2 (08h)
Table 28. FIFO_CTRL2 register description Table 25. FIFO_CTRL1 register
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
equal to the threshold level. Table 27. FIFO_CTRL2 register
- This bit must be set to '0' for the correct operation of the device.
- This bit is effective if the FIFO_COMPR_EN bit of EMB_FUNC_EN_B (05h) is set to 1.
or equal to the threshold level.
9.5 FIFO_CTRL3 (09h)
Table 30. FIFO_CTRL3 register description Table 29. FIFO_CTRL3 register Selects Batching Data Rate (writing frequency in FIFO) for gyroscope data. Selects Batching Data Rate (writing frequency in FIFO) for accelerometer data.
9.6 FIFO_CTRL4 (0Ah)
Table 32. FIFO_CTRL4 register description Table 31. FIFO_CTRL4 register
- This bit must be set to '0' for the correct operation of the device.
rate between XL and GYRO BDR divided by decimation decoder.
9.7 COUNTER_BDR_REG1 (0Bh)
Table 34. COUNTER_BDR_REG1 register description
9.8 COUNTER_BDR_REG2 (0Ch)
Table 36. COUNTER_BDR_REG2 register description Table 33. COUNTER_BDR_REG1 register
- This bit must be set to '0' for the correct operation of the device.
Resets the internal counter of batching events for a single sensor. This bit is automatically reset to zero if it was set to ‘1’. FIFO_STATUS2 (3Bh) is set to ‘1’.
9.9 INT1_CTRL (0Dh)
be the OR combination of the signals selected here and in MD1_CFG (5Eh). Table 38. INT1_CTRL register description Table 37. INT1_CTRL register trigger an IBI when the MIPI I3CSM interface is used. IBI when the MIPI I3CSM interface is used. an IBI when the MIPI I3CSM interface is used. trigger an IBI when the MIPI I3CSM interface is used. to trigger an IBI when the MIPI I3CSM interface is used.
9.10 INT2_CTRL (0Eh)
combination of the signals selected here and in MD2_CFG (5Fh). Table 40. INT2_CTRL register description
9.11 WHO_AM_I (0Fh)
WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Ch. Table 39. INT2_CTRL register
- This bit must be set to '0' for the correct operation of the device.
Table 41. WhoAmI register
9.12 CTRL1_XL (10h)
Table 43. CTRL1_XL register description Table 42. CTRL1_XL register
- This bit must be set to '0' for the correct operation of the device.
Table 44. Accelerometer ODR register setting Table 45. Accelerometer full-scale selection
9.13 CTRL2_G (11h)
Table 47. CTRL2_G register description Table 46. CTRL2_G register
- This bit must be set to '0' for the correct operation of the device.
Table 48. Gyroscope ODR configuration setting
9.14 CTRL3_C (12h)
Table 50. CTRL3_C register description Table 49. CTRL3_C register
- This bit must be set to '0' for the correct operation of the device.
This bit is automatically cleared. This bit is automatically cleared.
9.15 CTRL4_C (13h)
Table 52. CTRL4_C register description Table 51. CTRL4_C register
- This bit must be set to '0' for the correct operation of the device.
9.16 CTRL5_C (14h)
Table 54. CTRL5_C register description Table 53. CTRL5_C register
- Further details about the accelerometer ultra-low-power mode are provided in Section 6.2.1:
Accelerometer ultra-low-power mode. Table 55. Angular rate sensor self-test mode selection Table 56. Linear acceleration sensor self-test mode selection
9.17 CTRL6_C (15h)
Table 57. CTRL6_C register Table 58. CTRL6_C register description TRIG_EN DEN data edge-sensitive trigger enable. Refer to Table 59 . LVL1_EN DEN data level-sensitive trigger enable. Refer to Table 59 . LVL2_EN DEN level-sensitive latched enable. Refer to Table 59 . Table 60 shows the selectable bandwidth values. Table 59. Trigger mode selection
100 Edge-sensitive trigger mode is selected
010 Level-sensitive trigger mode is selected
011 Level-sensitive latched mode is selected
110 Level-sensitive FIFO enable mode is selected
Table 60. Gyroscope LPF1 bandwidth selection
9.18 CTRL7_G (16h)
Table 62. CTRL7_G register description
9.19 CTRL8_XL (17h)
Table 61. CTRL7_G register
- This bit must be set to '0' for the correct operation of the device.
Table 63. CTRL8_XL register
- This bit must be set to '0' for the correct operation of the device.
Table 64. CTRL8_XL register description
- When enabled, the first output data have to be discarded.
XL_EN Accelerometer slope filter / high-pass filter selection. Refer to Figure 21 . Table 65. Accelerometer bandwidth configurations
000 ODR/4
001 ODR/10
010 ODR/20
011 ODR/45
100 ODR/100
101 ODR/200
110 ODR/400
111 ODR/800
000 SLOPE (ODR/4)
Figure 21. Accelerometer block diagram
9.20 CTRL9_XL (18h)
Table 67. CTRL9_XL register description
9.21 CTRL10_C (19h)
Table 69. CTRL10_C register description Table 66. CTRL9_XL register
- This bit must be set to '0' for the correct operation of the device.
- It is recommended to set this bit to '1' during the initial d evice configuration phase, when the MIPI I3CSM
Table 68. CTRL10_C register
- This bit must be set to '0' for the correct operation of the device.
TIMESTAMP2 (42h), and TIMESTAMP3 (43h).
9.22 ALL_INT_SRC (1Ah)
Table 71. ALL_INT_SRC register description
9.23 WAKE_UP_SRC (1Bh)
Table 70. ALL_INT_SRC register Table 72. WAKE_UP_SRC register
0 SLEEP_
Table 73. WAKE_UP_SRC register description
9.24 TAP_SRC (1Ch)
9.25 D6D_SRC (1Dh)
Table 74. TAP_SRC register
0 TAP_IA SINGLE_
Table 75. TAP_SRC register description Table 76. D6D_SRC register Table 77. D6D_SRC register description
- The DEN data-ready signal can be latched or pulsed depending on the value of the dataready_pulsed bit of
the COUNTER_BDR_REG1 (0Bh) register.
9.26 STATUS_REG (1Eh)
9.27 OUT_TEMP_L (20h), OUT_TEMP_H (21h)
9.28 OUTX_L_G (22h) and OUTX_H_G (23h)
a 16-bit word in two’s complement. Table 78. STATUS_REG register Table 79. STATUS_REG register description Table 80. OUT_TEMP_L register Table 81. OUT_TEMP_H register Table 82. OUT_TEMP register description The value is expressed as two’s complement sign extended on the MSB. Table 83. OUTX_L_G register Table 84. OUTX_H_G register Table 85. OUTX_H_G register description
9.29 OUTY_L_G (24h) and OUTY_H_G (25h)
16-bit word in two’s complement.
9.30 OUTZ_L_G (26h) and OUTZ_H_G (27h)
a 16-bit word in two’s complement.
9.31 OUTX_L_A (28h) and OUTX_H_A (29h)
Table 86. OUTY_L_G register Table 87. OUTY_H_G register Table 88. OUTY_H_G register description Table 89. OUTZ_L_G register Table 90. OUTZ_H_G register Table 91. OUTZ_H_G register description Table 92. OUTX_L_A register Table 93. OUTX_H_A register Table 94. OUTX_H_A register description D[15:0] X-axis linear acceleration value.
9.32 OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
9.33 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
Table 95. OUTY_L_A register Table 96. OUTY_H_A register Table 97. OUTY_H_A register description Table 98. OUTZ_L_A register Table 99. OUTZ_H_A register Table 100. OUTZ_H_A register description
9.34 EMB_FUNC_STATUS_MAINPAGE (35h)
Table 102. EMB_FUNC_STATUS_MAINPAGE register description
9.35 FSM_STATUS_A_MAINPAGE (36h)
Table 104. FSM_STATUS_A_MAINPAGE register description Table 101. EMB_FUNC_STATUS_MAINPAGE register IS_FSM_LC Interrupt status bit for FSM long counter timeout interrupt event. Table 103. FSM_STATUS_A_MAINPAGE register IS_FSM8 Interrupt status bit for FSM8 interrupt event. IS_FSM7 Interrupt status bit for FSM7 interrupt event. IS_FSM6 Interrupt status bit for FSM6 interrupt event. IS_FSM5 Interrupt status bit for FSM5 interrupt event. IS_FSM4 Interrupt status bit for FSM4 interrupt event. IS_FSM3 Interrupt status bit for FSM3 interrupt event. IS_FSM2 Interrupt status bit for FSM2 interrupt event. IS_FSM1 Interrupt status bit for FSM1 interrupt event.
9.36 FSM_STATUS_B_MAINPAGE (37h)
Table 106. FSM_STATUS_B_MAINPAGE register description
9.37 STATUS_MASTER_MAINPAGE (39h)
Table 105. FSM_STATUS_B_MAINPAGE register IS_FSM16 Interrupt status bit for FSM16 interrupt event. IS_FSM15 Interrupt status bit for FSM15 interrupt event. IS_FSM14 Interrupt status bit for FSM14 interrupt event. IS_FSM13 Interrupt status bit for FSM13 interrupt event. IS_FSM12 Interrupt status bit for FSM12 interrupt event. IS_FSM11 Interrupt status bit for FSM11 interrupt event. IS_FSM10 Interrupt status bit for FSM10 interrupt event. IS_FSM9 Interrupt status bit for FSM9 interrupt event. Table 107. STATUS_MASTER_MAINPAGE register Table 108. STATUS_MASTER_MAINPAGE register description SLAVE3_NACK This bit is set to 1 if Not acknowledge occurs on slave 3 communication. SLAVE2_NACK This bit is set to 1 if Not acknowledge occurs on slave 2 communication. SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication.
9.38 FIFO_STATUS1 (3Ah)
Table 110. FIFO_STATUS1 register description
9.39 FIFO_STATUS2 (3Bh)
Table 112. FIFO_STATUS2 register description Table 109. FIFO_STATUS1 register In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh). Table 111. FIFO_STATUS2 register This bit is reset when these registers are read. This bit is reset when this register is read.
9.40 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h),
Table 114. TIMESTAMP output register description Table 113. TIMESTAMP output registers
9.41 TAP_CFG0 (56h)
Table 116. TAP_CFG0 register description Table 115. TAP_CFG0 register
- This bit must be set to '0' for the correct operation of the device.
Activity/inactivity interrupt mode configuration. HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.
9.42 TAP_CFG1 (57h)
Table 118. TAP_CFG1 register description
9.43 TAP_CFG2 (58h)
Table 121. TAP_CFG2 register description Table 117. TAP_CFG1 register
1 LSB = FS_XL / (25)
Table 119. TAP priority decoding
000 X Y Z
001 Y X Z
010 X Z Y
011 Z Y X
100 X Y Z
101 Y Z X
110 Z X Y
111 Z Y X
Table 120. TAP_CFG2 register
9.44 TAP_THS_6D (59h)
10 Reserved
11 Reserved
Table 123. TAP_THS_6D register description
9.45 INT_DUR2 (5Ah)
Table 122. TAP_THS_6D register 4D orientation detection enable. Z-axis position detection is disabled. For details, refer to Table 124.
1 LSB = FS_XL / (2
Table 124. Threshold for D4D/D6D function Table 125. INT_DUR2 register Table 126. INT_DUR2 register description bits are set to a different value, 1LSB corresponds to 32*ODR_XL time. corresponds to 8*ODR_XL time.
9.46 WAKE_UP_THS (5Bh)
Table 128. WAKE_UP_THS register description
9.47 WAKE_UP_DUR (5Ch)
Table 130. WAKE_UP_DUR register description Table 127. WAKE_UP_THS register filtered data) to the wakeup function. Table 129. WAKE_UP_DUR register FREE_FALL (5Dh) configuration.
1 LSB = 1 ODR_time
1 LSB = 512 ODR
9.48 FREE_FALL (5Dh)
Table 131. FREE_FALL register Table 132. FREE_FALL register description For details refer to Table 133 . Table 133. Threshold for free-fall function
011 Reserved
100 Reserved
101 Reserved
110 Reserved
111 Reserved
9.49 MD1_CFG (5Eh)
Table 135. MD1_CFG register description Table 134. MD1_CFG register
- Activity/Inactivity interrupt mode (sleep change or sleep sta tus) depends on the
SLEEP_STATUS_ON_INT bit in TAP_CFG0 (56h) register. Routing of sensor hub communication concluded event on INT1.
9.50 MD2_CFG (5Fh)
Table 137. MD2_CFG register description Table 136. MD2_CFG register
- Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT
bit in TAP_CFG0 (56h) register.
9.51 I3C_BUS_AVB (62h)
Table 139. I3C_BUS_AVB register description
9.52 INTERNAL_FREQ_FINE (63h)
Table 141. INTERNAL_FREQ_FINE register description
9.53 X_OFS_USR (73h)
offset register is internally subtracted from the acceleration value measured on the X-axis. Table 138. I3C_BUS_AVB register
- This bit must be set to '0' for the correct operation of the device.
This bit allows disabling the INT1 pull-down. These bits are used to select the bus available time when I3C IBI is used. Table 140. INTERNAL_FREQ_FINE register respect to the typical. Step: 0.15%. 8-bit format, 2's complement. Table 142. X_OFS_USR register Table 143. X_OFS_USR register description
9.54 Y_OFS_USR (74h)
offset register is internally subtracted from the acceleration value measured on the Y-axis. Table 145. Y_OFS_USR register description
9.55 Z_OFS_USR (75h)
offset register is internally subtracted from the acceleration value measured on the Z-axis. Table 147. Z_OFS_USR register description
9.56 FIFO_DATA_OUT_TAG (78h)
Table 149. FIFO_DATA_OUT_TAG register description Table 144. Y_OFS_USR register Table 146. Z_OFS_USR register Table 148. FIFO_DATA_OUT_TAG register
Table 150. FIFO tag
9.57 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H
Table 152. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description
9.58 FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H
Table 154. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description
9.59 FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H
Table 156. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description Table 151. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers Table 153. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers Table 155. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers
10 Embedded functions register mapping
when FUNC_CFG_EN is set to '1' in FUNC_CFG_ACCESS (01h). Table 157. Register address map - embedded functions
permanent damage to the device. Table 157. Register address map - embedded functions (continued)
11 Embedded functions register description
11.1 PAGE_SEL (02h)
Table 159. PAGE_SEL register description
11.2 EMB_FUNC_EN_A (04h)
Table 161. EMB_FUNC_EN_A register description Table 158. PAGE_SEL register
- This bit must be set to '0' for the correct operation of the device.
- This bit must be set to '1' for the correct operation of the device.
Table 160. EMB_FUNC_EN_A register
- This bit must be set to '0' for the correct operation of the device.
11.3 EMB_FUNC_EN_B (05h)
Table 163. EMB_FUNC_EN_B register description
11.4 PAGE_ADDRESS (08h)
Table 165. PAGE_ADDRESS register description
11.5 PAGE_VALUE (09h)
Table 167. PAGE_VALUE register description Table 162. EMB_FUNC_EN_B register
- This bit must be set to '0' for the correct operation of the device.
- This bit is effective if the FIFO_COMPR_RT_EN bit of FIFO_CTRL2 (08h) is set to 1.
Table 166. PAGE_VALUE register at the address PAGE_ADDR[7:0] of the selected advanced features page.
11.6 EMB_FUNC_INT1 (0Ah)
INT1 pin control register (r/w). the OR combination of the selected signals. Table 169. EMB_FUNC_INT1 register description Table 168. EMB_FUNC_INT1 register
- This bit must be set to '0' for the correct operation of the device.
- This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
11.7 FSM_INT1_A (0Bh)
INT1 pin control register (r/w). the OR combination of the selected signals. Table 171. FSM_INT1_A register description Table 170. FSM_INT1_A register
- This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
11.8 FSM_INT1_B (0Ch)
INT1 pin control register (r/w). the OR combination of the selected signals. Table 173. FSM_INT1_B register description Table 172. FSM_INT1_B register
- This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
11.9 EMB_FUNC_INT2 (0Eh)
INT2 pin control register (r/w). the OR combination of the selected signals. Table 175. EMB_FUNC_INT2 register description Table 174. EMB_FUNC_INT2 register
- This bit must be set to '0' for the correct operation of the device.
- This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
11.10 FSM_INT2_A (0Fh)
INT2 pin control register (r/w). the OR combination of the selected signals. Table 177. FSM_INT2_A register description Table 176. FSM_INT2_A register
- This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
11.11 FSM_INT2_B (10h)
INT2 pin control register (r/w). the OR combination of the selected signals. Table 179. FSM_INT2_B register description Table 178. FSM_INT2_B register
- This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
11.12 EMB_FUNC_STATUS (12h)
Table 181. EMB_FUNC_STATUS register description
11.13 FSM_STATUS_A (13h)
Table 183. FSM_STATUS_A register description Table 180. EMB_FUNC_STATUS register IS_FSM_LC Interrupt status bit for FSM long counter timeout interrupt event. Table 182. FSM_STATUS_A register IS_FSM8 Interrupt status bit for FSM8 interrupt event. IS_FSM7 Interrupt status bit for FSM7 interrupt event. IS_FSM6 Interrupt status bit for FSM6 interrupt event. IS_FSM5 Interrupt status bit for FSM5 interrupt event. IS_FSM4 Interrupt status bit for FSM4 interrupt event. IS_FSM3 Interrupt status bit for FSM3 interrupt event. IS_FSM2 Interrupt status bit for FSM2 interrupt event. IS_FSM1 Interrupt status bit for FSM1 interrupt event.
11.14 FSM_STATUS_B (14h)
Table 185. FSM_STATUS_B register description
11.15 PAGE_RW (17h)
Table 187. PAGE_RW register description Table 184. FSM_STATUS_B register IS_FSM16 Interrupt status bit for FSM16 interrupt event. IS_FSM15 Interrupt status bit for FSM15 interrupt event. IS_FSM14 Interrupt status bit for FSM14 interrupt event. IS_FSM13 Interrupt status bit for FSM13 interrupt event. IS_FSM12 Interrupt status bit for FSM12 interrupt event. IS_FSM11 Interrupt status bit for FSM11 interrupt event. IS_FSM10 Interrupt status bit for FSM10 interrupt event. IS_FSM9 Interrupt status bit for FSM9 interrupt event. Table 186. PAGE_RW register
- This bit must be set to '0' for the correct operation of the device.
- Page selected by PAGE_SEL[3:0] in PAGE_SEL (02h) register.
Enable reads from the selected advanced features dedicated page(1).
11.16 EMB_FUNC_FIFO_CFG (44h)
Table 189. EMB_FUNC_FIFO_CFG register description
11.17 FSM_ENABLE_A (46h)
Table 191. FSM_ENABLE_A register description Table 188. EMB_FUNC_FIFO_CFG register
- This bit must be set to '0' for the correct operation of the device.
Table 190. FSM_ENABLE_A register
11.18 FSM_ENABLE_B (47h)
Table 193. FSM_ENABLE_B register description
11.19 FSM_LONG_COUNTER_L (48h) and
using the LC_CLEAR bit in FSM_LONG_COUNTER_CLEAR (4Ah) register. Table 192. FSM_ENABLE_B register Table 194. FSM_LONG_COUNTER_L register Table 195. FSM_LONG_COUNTER_L register description Table 196. FSM_LONG_COUNTER_H register Table 197. FSM_LONG_COUNTER_H register description
11.20 FSM_LONG_COUNTER_CLEAR (4Ah)
Table 199. FSM_LONG_COUNTER_CLEAR register description
11.21 FSM_OUTS1 (4Ch)
Table 201. FSM_OUTS1 register description Table 198. FSM_LONG_COUNTER_CLEAR register
- This bit must be set to '0' for the correct operation of the device.
This read-only bit is automatically set to 1 when the long counter reset is done. Table 200. FSM_OUTS1 register P_X FSM1 output: positive event detected on the X-axis. N_X FSM1 output: negative event detected on the X-axis. P_Y FSM1 output: positive event detected on the Y-axis. N_Y FSM1 output: negative event detected on the Y-axis. P_Z FSM1 output: positive event detected on the Z-axis. N_Z FSM1 output: negative event detected on the Z-axis. P_V FSM1 output: positive event detected on the vector. N_V FSM1 output: negative event detected on the vector.
11.22 FSM_OUTS2 (4Dh)
Table 203. FSM_OUTS2 register description
11.23 FSM_OUTS3 (4Eh)
Table 205. FSM_OUTS3 register description Table 202. FSM_OUTS2 register P_X FSM2 output: positive event detected on the X-axis. N_X FSM2 output: negative event detected on the X-axis. P_Y FSM2 output: positive event detected on the Y-axis. N_Y FSM2 output: negative event detected on the Y-axis. P_Z FSM2 output: positive event detected on the Z-axis. N_Z FSM2 output: negative event detected on the Z-axis. P_V FSM2 output: positive event detected on the vector. N_V FSM2 output: negative event detected on the vector. Table 204. FSM_OUTS3 register P_X FSM3 output: positive event detected on the X-axis. N_X FSM3 output: negative event detected on the X-axis. P_Y FSM3 output: positive event detected on the Y-axis. N_Y FSM3 output: negative event detected on the Y-axis. P_Z FSM3 output: positive event detected on the Z-axis. N_Z FSM3 output: negative event detected on the Z-axis. P_V FSM3 output: positive event detected on the vector. N_V FSM3 output: negative event detected on the vector.
11.24 FSM_OUTS4 (4Fh)
Table 207. FSM_OUTS4 register description
11.25 FSM_OUTS5 (50h)
Table 209. FSM_OUTS5 register description Table 206. FSM_OUTS4 register P_X FSM4 output: positive event detected on the X-axis. N_X FSM4 output: negative event detected on the X-axis. P_Y FSM4 output: positive event detected on the Y-axis. N_Y FSM4 output: negative event detected on the Y-axis. P_Z FSM4 output: positive event detected on the Z-axis. N_Z FSM4 output: negative event detected on the Z-axis. P_V FSM4 output: positive event detected on the vector. N_V FSM4 output: negative event detected on the vector. Table 208. FSM_OUTS5 register P_X FSM5 output: positive event detected on the X-axis. N_X FSM5 output: negative event detected on the X-axis. P_Y FSM5 output: positive event detected on the Y-axis. N_Y FSM5 output: negative event detected on the Y-axis. P_Z FSM5 output: positive event detected on the Z-axis. N_Z FSM5 output: negative event detected on the Z-axis. P_V FSM5 output: positive event detected on the vector. N_V FSM5 output: negative event detected on the vector.
11.26 FSM_OUTS6 (51h)
Table 211. FSM_OUTS6 register description
11.27 FSM_OUTS7 (52h)
Table 213. FSM_OUTS7 register description Table 210. FSM_OUTS6 register P_X FSM6 output: positive event detected on the X-axis. N_X FSM6 output: negative event detected on the X-axis. P_Y FSM6 output: positive event detected on the Y-axis. N_Y FSM6 output: negative event detected on the Y-axis. P_Z FSM6 output: positive event detected on the Z-axis. N_Z FSM6 output: negative event detected on the Z-axis. P_V FSM6 output: positive event detected on the vector. N_V FSM6 output: negative event detected on the vector. Table 212. FSM_OUTS7 register P_X FSM7 output: positive event detected on the X-axis. N_X FSM7 output: negative event detected on the X-axis. P_Y FSM7 output: positive event detected on the Y-axis. N_Y FSM7 output: negative event detected on the Y-axis. P_Z FSM7 output: positive event detected on the Z-axis. N_Z FSM7 output: negative event detected on the Z-axis. P_V FSM7 output: positive event detected on the vector. N_V FSM7 output: negative event detected on the vector.
11.28 FSM_OUTS8 (53h)
Table 215. FSM_OUTS8 register description
11.29 FSM_OUTS9 (54h)
Table 217. FSM_OUTS9 register description Table 214. FSM_OUTS8 register P_X FSM8 output: positive event detected on the X-axis. N_X FSM8 output: negative event detected on the X-axis. P_Y FSM8 output: positive event detected on the Y-axis. N_Y FSM8 output: negative event detected on the Y-axis. P_Z FSM8 output: positive event detected on the Z-axis. N_Z FSM8 output: negative event detected on the Z-axis. P_V FSM8 output: positive event detected on the vector. N_V FSM8 output: negative event detected on the vector. Table 216. FSM_OUTS9 register P_X FSM9 output: positive event detected on the X-axis. N_X FSM9 output: negative event detected on the X-axis. P_Y FSM9 output: positive event detected on the Y-axis. N_Y FSM9 output: negative event detected on the Y-axis. P_Z FSM9 output: positive event detected on the Z-axis. N_Z FSM9 output: negative event detected on the Z-axis. P_V FSM9 output: positive event detected on the vector. N_V FSM9 output: negative event detected on the vector.
11.30 FSM_OUTS10 (55h)
Table 219. FSM_OUTS10 register description
11.31 FSM_OUTS11 (56h)
Table 221. FSM_OUTS11 register description Table 218. FSM_OUTS10 register P_X FSM10 output: positive event detected on the X-axis. N_X FSM10 output: negative event detected on the X-axis. P_Y FSM10 output: positive event detected on the Y-axis. N_Y FSM10 output: negative event detected on the Y-axis. P_Z FSM10 output: positive event detected on the Z-axis. N_Z FSM10 output: negative event detected on the Z-axis. P_V FSM10 output: positive event detected on the vector. N_V FSM10 output: negative event detected on the vector. Table 220. FSM_OUTS11 register P_X FSM11 output: positive event detected on the X-axis. N_X FSM11 output: negative event detected on the X-axis. P_Y FSM11 output: positive event detected on the Y-axis. N_Y FSM11 output: negative event detected on the Y-axis. P_Z FSM11 output: positive event detected on the Z-axis. N_Z FSM11 output: negative event detected on the Z-axis. P_V FSM11 output: positive event detected on the vector. N_V FSM11 output: negative event detected on the vector.
11.32 FSM_OUTS12 (57h)
Table 223. FSM_OUTS12 register description
11.33 FSM_OUTS13 (58h)
Table 225. FSM_OUTS13 register description Table 222. FSM_OUTS12 register P_X FSM12 output: positive event detected on the X-axis. N_X FSM12 output: negative event detected on the X-axis. P_Y FSM12 output: positive event detected on the Y-axis. N_Y FSM12 output: negative event detected on the Y-axis. P_Z FSM12 output: positive event detected on the Z-axis. N_Z FSM12 output: negative event detected on the Z-axis. P_V FSM12 output: positive event detected on the vector. N_V FSM12 output: negative event detected on the vector. Table 224. FSM_OUTS13 register P_X FSM13 output: positive event detected on the X-axis. N_X FSM13 output: negative event detected on the X-axis. P_Y FSM13 output: positive event detected on the Y-axis. N_Y FSM13 output: negative event detected on the Y-axis. P_Z FSM13 output: positive event detected on the Z-axis. N_Z FSM13 output: negative event detected on the Z-axis. P_V FSM13 output: positive event detected on the vector. N_V FSM13 output: negative event detected on the vector.
11.34 FSM_OUTS14 (59h)
Table 227. FSM_OUTS14 register description
11.35 FSM_OUTS15 (5Ah)
Table 229. FSM_OUTS15 register description Table 226. FSM_OUTS14 register P_X FSM14 output: positive event detected on the X-axis. N_X FSM14 output: negative event detected on the X-axis. P_Y FSM14 output: positive event detected on the Y-axis. N_Y FSM14 output: negative event detected on the Y-axis. P_Z FSM14 output: positive event detected on the Z-axis. N_Z FSM14 output: negative event detected on the Z-axis. P_V FSM14 output: positive event detected on the vector. N_V FSM14 output: negative event detected on the vector. Table 228. FSM_OUTS15 register P_X FSM15 output: positive event detected on the X-axis. N_X FSM15 output: negative event detected on the X-axis. P_Y FSM15 output: positive event detected on the Y-axis. N_Y FSM15 output: negative event detected on the Y-axis. P_Z FSM15 output: positive event detected on the Z-axis. N_Z FSM15 output: negative event detected on the Z-axis. P_V FSM15 output: positive event detected on the vector. N_V FSM15 output: negative event detected on the vector.
11.36 FSM_OUTS16 (5Bh)
Table 231. FSM_OUTS16 register description
11.37 EMB_FUNC_ODR_CFG_B (5Fh)
Table 233. EMB_FUNC_ODR_CFG_B register description Table 230. FSM_OUTS16 register P_X FSM16 output: positive event detected on the X-axis. N_X FSM16 output: negative event detected on the X-axis. P_Y FSM16 output: positive event detected on the Y-axis. N_Y FSM16 output: negative event detected on the Y-axis. P_Z FSM16 output: positive event detected on the Z-axis. N_Z FSM16 output: negative event detected on the Z-axis. P_V FSM16 output: positive event detected on the vector. N_V FSM16 output: negative event detected on the vector. Table 232. EMB_FUNC_ODR_CFG_B register
- This bit must be set to '0' for the correct operation of the device.
- This bit must be set to '1' for the correct operation of the device.
11.38 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h)
11.39 EMB_FUNC_SRC (64h)
Table 239. EMB_FUNC_SRC register description Table 234. STEP_COUNTER_L register Table 235. STEP_COUNTER_L register description Table 236. STEP_COUNTER_H register Table 237. STEP_COUNTER_H register description Table 238. EMB_FUNC_SRC register
0 STEP_
Reset pedometer step counter. Read/write bit. Step detector event detection status. Read-only bit. Pedometer step recognition on delta time status. Read-only bit. Step counter overflow status. Read-only bit. embedded advanced features (page 1) registers, this bit is kept to 0.
11.40 EMB_FUNC_INIT_A (66h)
Table 241. EMB_FUNC_INIT_A register description
11.41 EMB_FUNC_INIT_B (67h)
Table 243. EMB_FUNC_INIT_B register description Table 240. EMB_FUNC_INIT_A register
- This bit must be set to '0' for the correct operation of the device.
STEP_DET_INIT Pedometer Step Counter/Detector algorithm initialization request. Table 242. EMB_FUNC_INIT_B register
- This bit must be set to '0' for the correct operation of the device.
12 Embedded advanced features pages
Table 244. Register address map - embedded advanced features page 0
permanent damage to the device.
- Write bit FUNC_CFG_EN = 1
- Write 0001 in PAGE_SEL[3:0] field
- Write 84h in PAGE_ADDR register (08h) // Set address
- Write 06h in PAGE_DATA register (09h) // Set value to be written
- Write bit FUNC_CFG_EN = 0 in
Table 245. Register address map - embedded advanced features page 1
Embedded advanced features pages LSM6DSO32 Read procedure example: Example: read value of register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1 1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h) // Enable access to embedded functions registers 2. Write bit PAGE_READ = 1 in PAGE_RW (17h) register // Select read operation mode 3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h) // Select page 1 4. Write 84h in PAGE_ADDR register (08h) // Set address 5. Read value of PAGE_DATA register (09h) // Get register value 6. Write bit PAGE_READ = 0 in PAGE_RW (17h) register // Read operation disabled 7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h) // Disable access to embedded functions registers Note: Steps 1 and 2 of both procedures are intended to be performed at the beginning of the procedure. Steps 6 and 7 of both procedures are intended to be performed at the end of the procedure. If the procedure involves multiple operations, only steps 3, 4 and 5 must be repeated for each operation. If, in particular, the multiple operations involve consecutive registers, only step 5 can be performed.
13 Embedded advanced features register description
13.1 Page 0 - Embedded advanced features registers
13.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh)
External magnetometer sensitivity value register for the Finite State Machine (r/w). format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value of MAG_SENS[15:0] is 0x1624, corresponding to 0.0015 gauss/LSB.
13.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h)
Offset for X-axis hard-iron compensation register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 246. MAG_SENSITIVITY_L register Table 247. MAG_SENSITIVITY_L register description Table 248. MAG_SENSITIVITY_H register Table 249. MAG_SENSITIVITY_H register description Table 250. MAG_OFFX_L register Table 251. MAG_OFFX_L register description Table 252. MAG_OFFX_H register Table 253. MAG_OFFX_H register description
13.1.3 MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h)
Offset for Y-axis hard-iron compensation register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
13.1.4 MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h)
Offset for Z-axis hard-iron compensation register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 254. MAG_OFFY_L register Table 255. MAG_OFFY_L register description Table 256. MAG_OFFY_H register Table 257. MAG_OFFY_H register description Table 258. MAG_OFFZ_L register Table 259. MAG_OFFZ_L register description Table 260. MAG_OFFZ_H register Table 261. MAG_OFFZ_H register description
13.1.5 MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h)
Soft-iron (3x3 symmetric) matrix correction register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
13.1.6 MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h)
Soft-iron (3x3 symmetric) matrix correction register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 262. MAG_SI_XX_L register Table 263. MAG_SI_XX_L register description Table 264. MAG_SI_XX_H register Table 265. MAG_SI_XX_H register description Table 266. MAG_SI_XY_L register Table 267. MAG_SI_XY_L register description Table 268. MAG_SI_XY_H register Table 269. MAG_SI_XY_H register description
13.1.7 MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh)
Soft-iron (3x3 symmetric) matrix correction register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
13.1.8 MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh)
Soft-iron (3x3 symmetric) matrix correction register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 270. MAG_SI_XZ_L register Table 271. MAG_SI_XZ_L register description Table 272. MAG_SI_XZ_H register Table 273. MAG_SI_XZ_H register description Table 274. MAG_SI_YY_L register Table 275. MAG_SI_YY_L register description Table 276. MAG_SI_YY_H register Table 277. MAG_SI_YY_H register description
13.1.9 MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh)
Soft-iron (3x3 symmetric) matrix correction register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
13.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h)
Soft-iron (3x3 symmetric) matrix correction register (r/w). (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 278. MAG_SI_YZ_L register Table 279. MAG_SI_YZ_L register description MAG_SI_YZ_[7:0] Soft-iron correction row2 col3 (and row3 col2) coefficient (LSbyte). Table 280. MAG_SI_YZ_H register Table 281. MAG_SI_YZ_H register description MAG_SI_YZ_[15:8] Soft-iron correction row2 col3 (and row3 col2) coefficient (MSbyte). Table 282. MAG_SI_ZZ_L register Table 283. MAG_SI_ZZ_L register description Table 284. MAG_SI_ZZ_H register Table 285. MAG_SI_ZZ_H register description
13.1.11 MAG_CFG_A (D4h)
13.1.12 MAG_CFG_B (D5h)
Table 286. MAG_CFG_A register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 287. MAG_CFG_A description Table 288. MAG_CFG_B register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 289. MAG_CFG_B description
13.2 Page 1 - Embedded advanced features registers
13.2.1 FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh)
FSM long counter timeout register (r/w). counter value reached this value, the FSM generates an interrupt.
13.2.2 FSM_PROGRAMS (7Ch)
Table 290. FSM_LC_TIMEOUT_L register Table 291. FSM_LC_TIMEOUT_L register description Table 292. FSM_LC_TIMEOUT_H register Table 293. FSM_LC_TIMEOUT_H register description Table 294. FSM_PROGRAMS register Table 295. FSM_PROGRAMS register description FSM_N_PROG[7:0] Number of FSM programs; must be less than or equal to 16.
13.2.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh)
FSM start address register (r/w). First available address is 0x033C.
13.2.4 PEDO_CMD_REG (83h)
Table 301. PEDO_CMD_REG register description
13.2.5 PEDO_DEB_STEPS_CONF (84h)
Table 303. PEDO_DEB_STEPS_CONF register description Table 296. FSM_START_ADD_L register Table 297. FSM_START_ADD_L register description Table 298. FSM_START_ADD_H register Table 299. FSM_START_ADD_H register description Table 300. PEDO_CMD_REG register
- This bit must be set to '0' for the correct operation of the device.
CARRY_COUNT_EN Set when user wants to generate interrupt only on count overflow event.
- This bit is effective if the PEDO_ADV_EN bit of EMB_FUNC_EN_B (05h) is set to 1.
Enables the false-positive rejection feature.
- This bit is effective if both the FP_REJECTION_EN bit in PEDO_CMD_REG (83h) register and the
PEDO_ADV_EN bit of EMB_FUNC_EN_B (05h) are set to 1. Enables the advanced detection feature. Table 302. PEDO_DEB_STEPS_CONF register
13.2.6 PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h)
Table 304. PEDO_SC_DELTAT_L register Table 305. PEDO_SC_DELTAT_H register Table 306. PEDO_SC_DELTAT_H/L register description
14 Sensor hub register mapping
when bit SHUB_REG_ACCESS is set to '1' in FUNC_CFG_ACCESS (01h). Table 307. Register address map - sensor hub registers
permanent damage to the device.
15 Sensor hub register description
15.1 SENSOR_HUB_1 (02h)
15.2 SENSOR_HUB_2 (03h)
15.3 SENSOR_HUB_3 (04h)
Table 308. SENSOR_HUB_1 register Table 309. SENSOR_HUB_1 register description Table 310. SENSOR_HUB_2 register Table 311. SENSOR_HUB_2 register description Table 312. SENSOR_HUB_3 register Table 313. SENSOR_HUB_3 register description
15.4 SENSOR_HUB_4 (05h)
15.5 SENSOR_HUB_5 (06h)
15.6 SENSOR_HUB_6 (07h)
Table 314. SENSOR_HUB_4 register Table 315. SENSOR_HUB_4 register description Table 316. SENSOR_HUB_5 register Table 317. SENSOR_HUB_5 register description Table 318. SENSOR_HUB_6 register Table 319. SENSOR_HUB_6 register description
15.7 SENSOR_HUB_7 (08h)
15.8 SENSOR_HUB_8 (09h)
15.9 SENSOR_HUB_9 (0Ah)
Table 320. SENSOR_HUB_7 register Table 321. SENSOR_HUB_7 register description Table 322. SENSOR_HUB_8 register Table 323. SENSOR_HUB_8 register description Table 324. SENSOR_HUB_9 register Table 325. SENSOR_HUB_9 register description
15.10 SENSOR_HUB_10 (0Bh)
15.11 SENSOR_HUB_11 (0Ch)
15.12 SENSOR_HUB_12 (0Dh)
Table 326. SENSOR_HUB_10 register Table 327. SENSOR_HUB_10 register description Table 328. SENSOR_HUB_11 register Table 329. SENSOR_HUB_11 register description Table 330. SENSOR_HUB_12 register Table 331. SENSOR_HUB_12 register description
15.13 SENSOR_HUB_13 (0Eh)
15.14 SENSOR_HUB_14 (0Fh)
15.15 SENSOR_HUB_15 (10h)
Table 332. SENSOR_HUB_13 register Table 333. SENSOR_HUB_13 register description Table 334. SENSOR_HUB_14 register Table 335. SENSOR_HUB_14 register description Table 336. SENSOR_HUB_15 register Table 337. SENSOR_HUB_15 register description
15.16 SENSOR_HUB_16 (11h)
15.17 SENSOR_HUB_17 (12h)
15.18 SENSOR_HUB_18 (13h)
Table 338. SENSOR_HUB_16 register Table 339. SENSOR_HUB_16 register description Table 340. SENSOR_HUB_17 register Table 341. SENSOR_HUB_17 register description Table 342. SENSOR_HUB_17 register Table 343. SENSOR_HUB_17 register description
15.19 MASTER_CONFIG (14h)
15.20 SLV0_ADD (15h)
Table 344. MASTER_CONFIG register Table 345. MASTER_CONFIG register description Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. Slave 0 write operation is performed only at the first sensor hub cycle. Number of external sensors to be read by the sensor hub. Table 346. SLV0_ADD register Table 347. SLV_ADD register description slave0_add[6:0] I²C slave address of Sensor1 that can be read by the sensor hub.
15.21 SLV0_SUBADD (16h)
15.22 SLAVE0_CONFIG (17h)
Table 348. SLV0_SUBADD register Table 349. SLV0_SUBADD register description Table 350. SLAVE0_CONFIG register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 351. SLAVE0_CONFIG register description
15.23 SLV1_ADD (18h)
15.24 SLV1_SUBADD (19h)
15.25 SLAVE1_CONFIG (1Ah)
Table 352. SLV1_ADD register Table 353. SLV1_ADD register description Slave1_add[6:0] I²C slave address of Sensor 2 that can be read by the sensor hub. Table 354. SLV1_SUBADD register Table 355. SLV1_SUBADD register description bit value in SLV1_ADD (18h). Table 356. SLAVE1_CONFIG register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 357. SLAVE1_CONFIG register description
15.26 SLV2_ADD (1Bh)
15.27 SLV2_SUBADD (1Ch)
15.28 SLAVE2_CONFIG (1Dh)
Table 358. SLV2_ADD register Table 359. SLV2_ADD register description Slave2_add[6:0] I²C slave address of Sensor 3 that can be read by the sensor hub. Table 360. SLV2_SUBADD register Table 361. SLV2_SUBADD register description bit value in SLV2_ADD (1Bh). Table 362. SLAVE2_CONFIG register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 363. SLAVE2_CONFIG register description
15.29 SLV3_ADD (1Eh)
15.30 SLV3_SUBADD (1Fh)
15.31 SLAVE3_CONFIG (20h)
Table 364. SLV3_ADD register Table 365. SLV3_ADD register description Slave3_add[6:0] I²C slave address of Sensor 4 that can be read b y the sensor hub. Table 366. SLV3_SUBADD register Table 367. SLV3_SUBADD register description Table 368. SLAVE3_CONFIG register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 369. SLAVE3_CONFIG register description
15.32 DATAWRITE_SLV0 (21h)
15.33 STATUS_MASTER (22h)
Table 370. DATAWRITE_SLV0 register Table 371. DATAWRITE_SLV0 register description Table 372. STATUS_MASTER register Table 373. STATUS_MASTER register description SLAVE3_NACK This bit is set to 1 if Not acknowledge occurs on slave 3 communication. SLAVE2_NACK This bit is set to 1 if Not acknowledge occurs on slave 2 communication. SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication.
Soldering information LSM6DSO32
16 Soldering information
The LGA package is compliant with the ECOPACK, RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Land pattern and soldering recommendations are available at www.st.com/mems.
specifications, grade definitions and product status are available at: www.st.com.
17.1 LGA-14L package information
Figure 22. LGA-14L 2.5x3x0.86 mm package outline and mechanical data
17.2 LGA-14 packing information
Figure 23. Carrier tape information for LGA-14 package Figure 24. LGA-14 package orientation in carrier tape
Figure 25. Reel information for carrier tape of LGA-14 package Table 374. Reel dimensions for carrier tape of LGA-14 package
Table 375. Document revision history