LSM6DS33 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Overview
- 2 Embedded low-power features
- 2.1 Tilt detection
- 3 Pin description
- 4 Module specifications
- 4.1 Mechanical characteristics
- 4.2 Electrical characteristics
- 4.3 Temperature sensor characteristics
- 4.4 Communication interface characteristics
- 4.4.1 SPI - serial peripheral interface
- 4.4.2 I 2C - inter-IC control interface
- 4.5 Absolute maximum ratings
- 4.6 Terminology
- 4.6.1 Sensitivity
- 4.6.2 Zero-g and zero-rate level
- 5 Functionality
- 5.1 Operating modes
- 5.2 Gyroscope power modes
- 5.3 Accelerometer power modes
- 5.4 FIFO
- 5.4.1 Bypass mode
- 5.4.2 FIFO mode
- 5.4.3 Continuous mode
- 5.4.4 Continuous-to-FIFO mode
- 5.4.5 Bypass-to-Continuous mode
- 5.4.6 FIFO reading procedure
- 5.4.7 Filter block diagrams
- 6 Digital interfaces
Datasheet sections
- 9.21 WAKE_UP_SRC (1Bh)
- 9.22 TAP_SRC (1Ch)
- 9.23 D6D_SRC (1Dh)
- 9.24 STATUS_REG (1Eh)
- 9.25 OUT_TEMP_L (20h), OUT_TEMP(21h)
- 9.26 OUTX_L_G (22h)
- 9.27 OUTX_H_G (23h)
- 9.28 OUTY_L_G (24h)
- 9.29 OUTY_H_G (25h)
- 9.30 OUTZ_L_G (26h)
- 9.31 OUTZ_H_G (27h)
- 9.32 OUTX_L_XL (28h)
- 9.33 OUTX_H_XL (29h)
- 9.34 OUTY_L_XL (2Ah)
- 9.35 OUTY_H_XL (2Bh)
- 9.36 OUTZ_L_XL (2Ch)
- 9.37 OUTZ_H_XL (2Dh)
- 9.38 FIFO_STATUS1 (3Ah)
- 9.39 FIFO_STATUS2 (3Bh)
- 9.40 FIFO_STATUS3 (3Ch)
- 9.41 FIFO_STATUS4 (3Dh)
- 9.42 FIFO_DATA_OUT_L (3Eh)
- 9.43 FIFO_DATA_OUT_H (3Fh)
- 9.44 TIMESTAMP0_REG (40h)
- 9.45 TIMESTAMP1_REG (41h)
- 9.46 TIMESTAMP2_REG (42h)
- 9.47 STEP_TIMESTAMP_L (49h)
- 9.48 STEP_TIMESTAMP_H (4Ah)
- 9.49 STEP_COUNTER_L (4Bh)
- 9.50 STEP_COUNTER_H (4Ch)
- 9.51 FUNC_SRC (53h)
- 9.52 TAP_CFG (58h)
- 9.53 TAP_THS_6D (59h)
Features
Power consumption: 0.9 mA in combo normal mode and 1.25 mA in combo high-performance mode up to 1.6 kHz. “Always-on” experience with low power consumption for both accelerometer and gyroscope Smart FIFO up to 8 kbyte based on features set Compliant with Android K and L ±2/±4/±8/±16 g full scale ±125/±245/±500/±1000/±2000 dps full scale Analog supply voltage: 1.71 V to 3.6 V Independent IOs supply (1.62 V) Compact footprint, 3 mm x 3 mm x 0.86 mm SPI/I 2C serial interface with main processor data synchronization feature Embedded temperature sensor ECOPACK®, RoHS and “Green” compliant
Applications
Pedometer, step detector and step counter Significant motion and tilt functions Indoor navigation Tap and double-tap detection IoT and connected devices Intelligent power saving for handheld devices Vibration monitoring and compensation Free-fall detection 6D orientation detection
Description
The LSM6DS33 is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope performing at 1.25 mA (up to 1.6 kHz ODR) in high- performance mode and enabling always-on low-power features for an optimal motion experience for the consumer. The LSM6DS33 supports main OS requirements, offering real, virtual and batch sensors with 8 kbyte for dynamic data batching. ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The LSM6DS33 has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular rate range of High robustness to mechanical shock makes the LSM6DS33 the preferred choice of system designers for the creation and manufacturing of reliable products. The LSM6DS33 is available in a plastic land grid array (LGA) package. LGA-16L (3 x 3 x 0.86 mm) typ. Table 1. Device summary
1 Overview
The LSM6DS33 is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. The integrated power-efficient modes are able to reduce the power consumption down to 1.25 mA in high-performance mode, combining always-on low-power features with superior sensing precision for an optimal motion experience for the consumer thanks to ultra-low noise performance for both the gyroscope and accelerometer. The LSM6DS33 delivers best-in-class motion sensing that can detect orientation and gestures in order to empower application developers and consumers with features and capabilities that are more sophisticated than simply orienting their devices to portrait and landscape mode. The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness, implementing hardware recognition of free-fall events, 6D orientation, tap and double-tap sensing, activity or inactivity, and wakeup events. The LSM6DS33 supports main OS requirements, offering real, virtual and batch mode sensors. In addition, the LSM6DS33 can efficiently run the sensor-related features specified in Android, saving power and enabling faster reaction time. In particular, the LSM6DS33 has been designed to implement hardware features such as significant motion, tilt, pedometer functions, and time stamping. Up to 8 kbyte of FIFO with dynamic allocation of significant data (i.e. sensors, temperature, step counter and time stamp) allows overall power saving of the system. Like the entire portfolio of MEMS sensor modules, the LSM6DS33 leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The LSM6DS33 is available in a small plastic land grid array (LGA) package of 3 x 3 x 0.86 mm to address ultra-compact solutions.
Embedded low-power features LSM6DS33
2 Embedded low-power features
The LSM6DS33 has been designed to be fully compliant with Android, featuring the following on-chip functions: 8 kbyte data buffering – 100% efficiency with flexible configurations and partitioning – possibility to store time stamp Event-detection interrupts (fully configurable): – free-fall – wakeup – 6D orientation – tap and double-tap sensing – activity / inactivity recognition Specific IP blocks with negligible power consumption and high-performance: – pedometer functions: step detector and step counters – tilt (Android compliant, refer to Section 2.1: Tilt detection for additional info – significant motion (Android compliant)
2.1 Tilt detection
The tilt function helps to detect activity change and has been implemented in hardware using only the accelerometer to achieve both the targets of ultra-low power consumption and robustness during the short duration of dynamic accelerations. It is based on a trigger of an event each time the device's tilt changes by an angle greater than 35 degrees from the start position. The tilt function can be used with different scenarios, for example: a) Trigger when phone is in a front pants pocket and the user goes from sitting to standing or standing to sitting; b) Doesn’t trigger when phone is in a front pants pocket and the user is walking, running or going upstairs.
3 Pin description
Figure 1. Pin connections In the LSM6DS33 an I2C slave interface or SPI (3- and 4-wire) serial interface is available.
Table 2. Pin description
1 VDDIO (1)
- Recommended 100 nF filter capacitor.
2 SCL I2C serial clock (SCL)
3 SDA
4 SDO/SA0 SPI 4-wire interface serial data output (SDO)
6 INT2 Programmable interrupt
7 INT1 Programmable interrupt
8 RES Reserved, connect to GND
9 RES Reserved, connect to GND
10 RES Reserved, connect to GND
11 RES Reserved, connect to GND
12 GND 0 V supply
13 GND 0 V supply
14 NC Leave unconnected
15 RES Reserved, connect to GND
16 VDD
- Recommended 100 nF capacitor.
4 Module specifications
4.1 Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. Table 3. Mechanical characteristics
- Typical specifications are not guaranteed.
- Measurements are performed in a uniform temperature setup.
Table 3. Mechanical characteristics (continued)
4.2 Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. Table 4. Electrical characteristics modes and 5.3: Accelerometer power modes.
- Typical specifications are not guaranteed.
4.3 Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. Table 5. Temperature sensor characteristics
- Typical specifications are not guaranteed.
- The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
- Time from power ON bit to valid data based on characterization data.
4.4 Communication interface characteristics
4.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 2. SPI slave timing diagram Table 6. SPI slave timing values
- Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
4.4.2 I 2C - inter-IC control interface
Subject to general operating conditions for Vdd and Top. Figure 3. I2C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Table 7. I2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production.
4.5 Absolute maximum ratings
Note: Supply Voltage on any pin should never exceed 4.8 V. Table 8. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
Module specifications LSM6DS33
4.6 Terminology
4.6.1 Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors. An angular rate gyroscope is device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time.
4.6.2 Zero- g and zero-rate level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 3. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors. Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time.
5 Functionality
5.1 Operating modes
The LSM6DS33 has three operating modes available: only accelerometer active and gyroscope in power-down only gyroscope active and accelerometer in power-down both accelerometer and gyroscope sensors active with independent ODR The accelerometer is activated from power down by writing ODR_XL[3:0] in CTRL1_XL (10h) while the gyroscope is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h). For combo mode the ODRs are totally independent.
5.2 Gyroscope power modes
In the LSM6DS33, the gyroscope can be configured in four different operating modes: power-down, low-power, normal mode and high-performance mode. The operating mode selected depends on the value of the G_HM_MODE bit in CTRL7_G (16h). If G_HM_MODE is set to ‘0’, high-performance mode is valid for all ODRs (from 13 Hz up to 1.6 kHz). To enable the low-power and normal mode, the G_HM_MODE bit has to be set to ‘1’. Low- power mode is available for lower ODR (13, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
5.3 Accelerometer power modes
In the LSM6DS33, the accelerometer can be configured in four different operating modes: power-down, low-power, normal mode and high-performance mode. The operating mode selected depends on the value of the XL_HM_MODE bit in CTRL6_C (15h). If XL_HM_MODE is set to ‘0’, high-performance mode is valid for all ODRs (from 13 Hz up to 6.66 kHz). To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to ‘1’. Low- power mode is available for lower ODRs (13, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
5.4 FIFO
The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. LSM6DS33 embeds 8 kbytes data FIFO to store the following data: gyroscope accelerometer step counter and time stamp temperature
Writing data in the FIFO can be configured to be triggered by the: - accelerometer/gyroscope data-ready signal; in which case the ODR must be lower than or equal to both the accelerometer and gyroscope ODRs; - step detection signal. In addition, each data can be stored at a decimated data rate compared to FIFO ODR and it is configurable by the user, setting the registers FIFO_CTRL3 (08h) and FIFO_CTRL4 (09h). The available decimation factors are 2, 3, 4, 8, 16, 32. Programmable FIFO threshold can be set in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h) using the FTH [11:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh), FIFO_STATUS3 (3Ch), FIFO_STATUS4 (3Dh)) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO threshold status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pads of these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh). FIFO buffer can be configured according to five different modes: – Bypass mode – FIFO mode – Continuous mode – Continuous-to-FIFO mode – Bypass-to-continuous mode Each mode is selected by the FIFO_MODE_[2:0] in FIFO_CTRL5 (0Ah) register. To guarantee the correct acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded.
5.4.1 Bypass mode
In Bypass mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
5.4.2 FIFO mode
In FIFO mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 001) data from the output channels are stored in the FIFO until it is full. To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0]) to '000' After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0]) to '001'. FIFO buffer memorizes up to 4096 samples of 16 bits each but the depth of the FIFO can be resized by setting the FTH [11:0] bits in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h). If the STOP_ON_FTH bit in CTRL4_C (13h) is set to '1', FIFO depth is limited up to FTH [11:0] bits in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h).
5.4.3 Continuous mode
Continuous mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new data arrives, the older data is discarded.
A FIFO threshold flag FIFO_STATUS2 (3Bh)(FTH) is asserted when the number of unread samples in FIFO is greater than or equal to FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)(FTH [11:0]). It is possible to route FIFO_STATUS2 (3Bh) (FTH) to the INT1 pin by writing in register INT1_CTRL (0Dh) (INT1_FTH) = ‘1’ or to the INT2 pin by writing in register INT2_CTRL (0Eh) (INT2_FTH) = ‘1’. A full-flag interrupt can be enabled, INT1_CTRL (0Dh) (INT_ FULL_FLAG) = '1', in order to indicate FIFO saturation and eventually read its content all at once. If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the OVER_RUN flag in FIFO_STATUS2 (3Bh) is asserted. In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) (DIFF_FIFO[11:0]).
5.4.4 Continuous-to-FIFO mode
In Continuous-to-FIFO mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 011), FIFO behavior changes according to the trigger event detected in one of the following interrupt registers FUNC_SRC (53h), TAP_SRC (1Ch), WAKE_UP_SRC (1Bh) and D6D_SRC (1Dh). When the selected trigger bit is equal to '1', FIFO operates in FIFO mode. When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
5.4.5 Bypass-to-Continuous mode
In Bypass-to-Continuous mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = '100'), data measurement storage inside FIFO operates in Continuous mode when selected triggers in one of the following interrupt registers FUNC_SRC (53h), TAP_SRC (1Ch), WAKE_UP_SRC (1Bh) and D6D_SRC (1Dh) are equal to '1', otherwise FIFO content is reset (Bypass mode).
5.4.6 FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers (FIFO_DATA_OUT_L (3Eh) and FIFO_DATA_OUT_H (3Fh)) and each FIFO sample is composed of 16 bits. All FIFO status registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh), FIFO_STATUS3 (3Ch), FIFO_STATUS4 (3Dh)) can be read at the start of a reading operation, minimizing the intervention of the application processor. Saving data in the FIFO buffer is organized in four FIFO data sets consisting of 6 bytes each: The 1st FIFO data set is reserved for gyroscope data; The 2nd FIFO data set is reserved for accelerometer data;
5.4.7 Filter block diagrams
Figure 4. Accelerometer chain Figure 5. Accelerometer composite filter
Figure 6. Gyroscope chain
6 Digital interfaces
CS line must be tied high (i.e connected to Vdd_IO).
6.1 I 2C serial interface
whose content can also be read back. The relevant I2C terminology is provided in the table below. resistors. When the bus is free, both the lines are high. In order to disable the I2C block, (I2C_disable) = 1 must be written in CTRL4_C (13h). Table 9. Serial interface pin description Table 10. I2C terminology
6.1.1 I 2C operation
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted. The increment of the address is configured by the CTRL3_C (12h) (IF_INC). SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 11. SAD+Read/Write patterns Table 12. Transfer when master is writing one byte to slave Table 13. Transfer when master is writing multiple bytes to slave
terminated by the generation of a STOP (SP) condition.
6.2 SPI bus interface
The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO. Figure 7. Read and write protocol falling edge of SPC and should be captured at the rising edge of SPC. Table 14. Transfer when master is receiving (reading) one byte of data from slave Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
6.2.1 SPI read
Figure 8. SPI read protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register.
Figure 9. Multiple byte SPI read protocol (2-byte example)
6.2.2 SPI write
Figure 10. SPI write protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1 -7: address AD(6:0). This is the address field of the indexed register. Figure 11. Multiple byte SPI write protocol (2-byte example)
6.2.3 SPI read in 3-wire mode
Figure 12. SPI read protocol in 3-wire mode bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode.
7 Application hints
7.1 LSM6DS33 electrical connections
Figure 13. LSM6DS33 electrical connections selectable and accessible through the SPI/I2C interface. completely programmed by the user through the SPI/I2C interface.
7.2 Pin compatibility with LSM6DS0
Figure 14. Schematic 1 (pin 15 connected to GND)
Figure 15. Schematic 2 (pin 15 connected to VDD, Vdd_IO = VDD)
8 Register mapping
the corresponding addresses. Table 16. Registers address map
Table 16. Registers address map (continued)
permanent damage to the device.
9 Register description
7 bits, are used to identify them and to write the data through the serial interface.
9.1 FUNC_CFG_ACCESS (01h)
Enable embedded functions register (r/w). Table 18. FUNC_CFG_ACCESS register description
9.2 FIFO_CTRL1 (06h)
FIFO control register (r/w). Table 20. FIFO_CTRL1 register description
9.3 FIFO_CTRL2 (07h)
FIFO control register (r/w). Table 17. FUNC_CFG_ACCESS register
- This bit must be set to ‘0’ for the correct operation of the device.
02h to 32h. Default value: 0.
- The embedded functions configuration registers details are available in 10: Embedded functions register
mapping and 11: Embedded functions registers description. Table 19. FIFO_CTRL1 register FIFO threshold level setting(1). Default value: 0000 0000. greater than or equal to the threshold level.
- For a complete watermark threshold configuration, consider FTH_[11:8] in FIFO_CTRL2 (07h).
Table 21. FIFO_CTRL2 register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 22. FIFO_CTRL2 register description
9.4 FIFO_CTRL3 (08h)
FIFO control register (r/w). Table 24. FIFO_CTRL3 register description write is greater than or equal to the threshold level.
- For a complete watermark threshold configuration, consider FTH_[11:8] in FIFO_CTRL1 (06h)
Table 23. FIFO_CTRL3 register
- This bit must be set to ‘0’ for the correct operation of the device.
For the configuration setting, refer to Table 25. For the configuration setting, refer to Table 26. Table 25. Gyro FIFO decimation setting
000 Gyro sensor not in FIFO
001 No decimation
010 Decimation with factor 2
011 Decimation with factor 3
100 Decimation with factor 4
101 Decimation with factor 8
110 Decimation with factor 16
111 Decimation with factor 32
9.5 FIFO_CTRL4 (09h)
FIFO control register (r/w). Table 28. FIFO_CTRL4 register description Table 26. Accelerometer FIFO decimation setting
000 Accelerometer sensor not in FIFO
Table 27. FIFO_CTRL4 register
- This bit must be set to ‘0’ for the correct operation of the device.
For the configuration setting, refer to Table 29. Table 29. Third FIFO data set decimation setting
000 Third FIFO data set not in FIFO
9.6 FIFO_CTRL5 (0Ah)
FIFO control register (r/w). Table 31. FIFO_CTRL5 register description Table 30. FIFO_CTRL5 register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 32. FIFO ODR selection
- If the device is working at an ODR slower than the one selected, FIFO ODR is limited to that ODR value.
Moreover, these bits are effective if the TIMER_PEDO_FIFO_DRDY bit of FIFO_CTRL2 (07h) is set to 0.
0000 FIFO disabled
0001 FIFO ODR is set to 13 Hz
0010 FIFO ODR is set to 26 Hz
0011 FIFO ODR is set to 52 Hz
0100 FIFO ODR is set to 104 Hz
0101 FIFO ODR is set to 208 Hz
0110 FIFO ODR is set to 416 Hz
0111 FIFO ODR is set to 833 Hz
Table 33. FIFO mode selection 000 Bypass mode. FIFO disabled. 001 FIFO mode. Stops collecting data when FIFO is full.
010 Reserved
011 Continuous mode until trigger is deasserted, then FIFO mode. 100 Bypass mode until trigger is deasserted, then Continuous mode.
101 Reserved
110 Continuous mode. If the FIFO is full, the new sample overwrites the older one.
111 Reserved
9.7 ORIENT_CFG_G (0Bh)
Angular rate sensor sign and orientation register (r/w). Table 34. ORIENT_CFG_G register Table 35. ORIENT_CFG_G register description
9.8 INT1_CTRL (0Dh)
INT1 pad control register (r/w). supply the OR combination of the selected signals. Table 37. INT1_CTRL register
- This bit must be set to ‘0’ for the correct operation of the device.
For the configuration setting, refer to Table 36. Table 36. Settings for orientation of axes
Table 38. INT1_CTRL register description
9.9 INT2_CTRL (0Eh)
INT2 pad control register (r/w). supply the OR combination of the selected signals. Table 39. INT2_CTRL register Table 40. INT2_CTRL register description Pedometer step recognition interrupt on delta time(1) enable on INT2 pad.
- Delta time value is defined in register STEP_COUNT_DELTA (15h).
9.10 WHO_AM_I (0Fh)
Who_AM_I register (r). This register is a read-only register. Its value is fixed at 69h.
9.11 CTRL1_XL (10h)
Linear acceleration sensor control register 1 (r/w). Table 42. CTRL1_XL register Table 43. CTRL1_XL register description Table 41. WHO_AM_I register ODR_XL [3:0] Output data rate and power mode selection . Default value: 0000 (see Table 44). FS_XL [1:0] Accelerometer full-scale selection. Default value: 00. Table 44. Accelerometer ODR register setting
Table 45. BW and ODR (high-performance mode)
- Filter not used when accelerometer is in normal and low-power modes.
833 Hz 400 Hz
416 Hz 200 Hz
208 Hz 100 Hz
9.12 CTRL2_G (11h)
Angular rate sensor control register 2 (r/w). Table 46. CTRL2_G register Table 47. CTRL2_G register description
- This bit must be set to ‘0’ for the correct operation of the device.
Table 48. Gyroscope ODR configuration setting
9.13 CTRL3_C (12h)
Table 49. CTRL3_C register Table 50. CTRL3_C register description
- Boot request is executed as soon as internal oscillator is turned on. It is possible to set bit while in power-
down mode, in this case it will be served at the next normal mode or sleep mode. (0: 4-wire interface; 1: 3-wire interface). This bit is cleared by hardware after next flash boot.
9.14 CTRL4_C (13h)
9.15 CTRL5_C (14h)
Table 53. CTRL5_C register Table 51. CTRL4_C register Table 52. CTRL4_C register description
- Filter used in high-performance mode only with ODR less than 3.33 kHz.
- Filter used in high-performance mode only.
- This bit is effective if the TIMER_PEDO_FIFO_EN bit of FIFO_CTRL2 register is set to 0.
- In configuration 1, switching to combo mode, data are collected in FIFO only when both accelerometer and
gyroscope are set. Switching to accelerometer only, data are collected in FIFO after filter setting. STOP_ON_FTH Enable FIFO threshold level use. Default value: 0.
- This bit must be set to ‘0’ for the correct operation of the device
Table 54. CTRL5_C register description
9.16 CTRL6_C (15h)
Angular rate sensor control register 6 (r/w). Table 55. Output registers rounding pattern
000 No rounding
001 Accelerometer only
010 Gyroscope only
011 Gyroscope + accelerometer
Table 56. Angular rate sensor self-test mode selection Table 57. Linear acceleration sensor self-test mode selection Table 58. CTRL6_C register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 59. CTRL6_C register description
- Normal and low-power mode depends on the ODR setting, for details refer to Table 44.
9.17 CTRL7_G (16h)
Angular rate sensor control register 7 (r/w).
9.18 CTRL8_XL (17h)
Linear acceleration sensor control register 8 (r/w). Table 60. CTRL7_G register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 61. CTRL7_G register description
- Normal and low-power mode depends on the ODR setting, for details refer to Table 48.
HPCF_G[1:0] Gyroscope high-pass filter cutoff frequency selection. Default value: 00. Table 62. Gyroscope high-pass filter mode configuration Table 63. CTRL8_XL register
- This bit must be set to ‘0’ for the correct operation of the device.
9.19 CTRL9_XL (18h)
Linear acceleration sensor control register 9 (r/w). Table 64. CTRL8_XL register description LPF2_XL_EN Accelerometer low-pass filter LPF2 selection. Refer to Figure 5. HP_SLOPE_XL_EN Accelerometer slope filter / high-pass filter selection. Refer to Figure 5. LOW_PASS_ON_6D Low-pass filter on 6D function selection. Refer to Figure 5. Table 65. Accelerometer slope and high-pass filter selection and cutoff frequency
00 Slope ODR_XL/50
01 High-pass ODR_XL/100
10 High-pass ODR_XL/9
11 High-pass ODR_XL/400
Table 66. CTRL9_XL register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 67. CTRL9_XL register description
9.20 CTRL10_C (19h)
9.21 WAKE_UP_SRC (1Bh)
Wake up interrupt source register (r). Table 68. CTRL10_C register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 69. CTRL10_C register description Table 70. WAKE_UP_SRC register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 71. WAKE_UP_SRC register description
9.22 TAP_SRC (1Ch)
9.23 D6D_SRC (1Dh)
Table 72. TAP_SRC register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 73. TAP_SRC register description Table 74. D6D_SRC register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 75. D6D_SRC register description
9.24 STATUS_REG (1Eh)
9.25 OUT_TEMP_L (20h), OUT_TEMP(21h)
9.26 OUTX_L_G (22h)
Table 76. STATUS_REG register Table 77. STATUS_REG register description Table 78. OUT_TEMP_L register Table 79. OUT_TEMP_H register Table 80. OUT_TEMP register description The value is expressed as two’s complement sign extended on the MSB. Table 81. OUTX_L_G register Table 82. OUTX_L_G register description
9.27 OUTX_H_G (23h)
9.28 OUTY_L_G (24h)
word in two’s complement. (r).
9.29 OUTY_H_G (25h)
word in two’s complement. (r).
9.30 OUTZ_L_G (26h)
word in two’s complement. (r). Table 83. OUTX_H_G register Table 84. OUTX_H_G register description Table 85. OUTY_L_G register Table 86. OUTY_L_G register description Table 87. OUTY_H_G register Table 88. OUTY_H_G register description Table 89. OUTZ_L_G register Table 90. OUTZ_L_G register description
9.31 OUTZ_H_G (27h)
9.32 OUTX_L_XL (28h)
9.33 OUTX_H_XL (29h)
9.34 OUTY_L_XL (2Ah)
Table 91. OUTZ_H_G register Table 92. OUTZ_H_G register description Table 93. OUTX_L_XL register Table 94. OUTX_L_XL register description Table 95. OUTX_H_XL register Table 96. OUTX_H_XL register description Table 97. OUTY_L_XL register Table 98. OUTY_L_XL register description
9.35 OUTY_H_XL (2Bh)
9.36 OUTZ_L_XL (2Ch)
9.37 OUTZ_H_XL (2Dh)
9.38 FIFO_STATUS1 (3Ah)
BDU bit in CTRL3_C (12h) to 1. Table 105. FIFO_STATUS1 register Table 106. FIFO_STATUS1 register description Table 99. OUTY_H_G register Table 100. OUTY_H_G register description Table 101. OUTZ_L_XL register Table 102. OUTZ_L_XL register description Table 103. OUTZ_H_XL register Table 104. OUTZ_H_XL register description DIFF_FIFO_[7:0] Number of unread words (16-bit axes) stored in FIFO (1).
- For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS2 (3Bh)
9.39 FIFO_STATUS2 (3Bh)
BDU bit in CTRL3_C (12h) to 1. Table 107. FIFO_STATUS2 register Table 108. FIFO_STATUS2 register description
9.40 FIFO_STATUS3 (3Ch)
BDU bit in CTRL3_C (12h) to 1. Table 109. FIFO_STATUS3 register Table 110. FIFO_STATUS3 register description
- FIFO watermark level is set in FTH_[11:0] in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)
DIFF_FIFO_[7:0] Number of unread words (16-bit axes) stored in FIFO (2).
- For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS1 (3Ah)
PATTERN_[7:0] Word of recursive pattern read at the next reading.
9.41 FIFO_STATUS4 (3Dh)
BDU bit in CTRL3_C (12h) to 1. Table 111. FIFO_STATUS4 register Table 112. FIFO_STATUS4 register description
9.42 FIFO_DATA_OUT_L (3Eh)
9.43 FIFO_DATA_OUT_H (3Fh)
- This bit must be set to ‘0’ for the correct operation of the device.
PATTERN_[9:8] Word of recursive pattern read at the next reading. Table 113. FIFO_DATA_OUT_L register Table 114. FIFO_DATA_OUT_L register description Table 115. FIFO_DATA_OUT_H register Table 116. FIFO_DATA_OUT_H register description
9.44 TIMESTAMP0_REG (40h)
resolution is defined by setting the value in WAKE_UP_DUR (5Ch).
9.45 TIMESTAMP1_REG (41h)
resolution is defined by setting value in WAKE_UP_DUR (5Ch).
9.46 TIMESTAMP2_REG (42h)
has to be stored in this register.
9.47 STEP_TIMESTAMP_L (49h)
TIMESTAMP_REG1 register is copied in STEP_TIMESTAMP_L. Table 117. TIMESTAMP0_REG register Table 118. TIMESTAMP0_REG register description Table 119. TIMESTAMP1_REG register Table 120. TIMESTAMP1_REG register description Table 121. TIMESTAMP2_REG register Table 122. TIMESTAMP2_REG register description Table 123. STEP_TIMESTAMP_L register Table 124. STEP_TIMESTAMP_L register description STEP_TIMESTAMP_L[7:0] Timestamp of last step detected.
9.48 STEP_TIMESTAMP_H (4Ah)
TIMESTAMP_REG2 register is copied in STEP_TIMESTAMP_H.
9.49 STEP_COUNTER_L (4Bh)
Step counter output register (r).
9.50 STEP_COUNTER_H (4Ch)
Step counter output register (r).
9.51 FUNC_SRC (53h)
Significant motion, tilt, step detector interrupt source register (r). Table 125. STEP_TIMESTAMP_H register Table 126. STEP_TIMESTAMP_H register description STEP_TIMESTAMP_H[7:0] Timestamp of last step detected. Table 127. STEP_COUNTER_L register Table 128. STEP_COUNTER_L register description Table 129. STEP_COUNTER_H register Table 130. STEP_COUNTER_H register description Table 131. FUNC_SRC register
9.52 TAP_CFG (58h)
Table 132. FUNC_SRC register description Table 133. TAP_CFG register Table 134. TAP_CFG register description
9.53 TAP_THS_6D (59h)
Portrait/landscape position and tap function threshold register (r/w).
9.54 INT_DUR2 (5Ah)
Tap recognition function setting register (r/w). Table 135. TAP_THS_6D register Table 136. TAP_THS_6D register description 4D orientation detection enable (Z-axis position detection is disabled). For details, refer to Table 137. Table 137. Threshold for D4D/D6D function Table 138. INT_DUR2 register Table 139. INT_DUR2 register description DUR[3:0] bits are set to a different value, 1LSB corresponds to 32*ODR_XL time.
9.55 WAKE_UP_THS (5Bh)
Single and double-tap function threshold register (r/w).
9.56 WAKE_UP_DUR (5Ch)
Free-fall, wakeup, time stamp and sleep mode functions duration setting register (r/w). Table 140. WAKE_UP_THS register Table 141. WAKE_UP_THS register description Table 142. WAKE_UP_DUR register Table 143. WAKE_UP_DUR register description FREE_FALL (5Dh) configuration.
- Configuration of this bit affects TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h),
STEP_COUNT_DELTA (15h) registers.
1 LSB = 512 ODR
9.57 FREE_FALL (5Dh)
Free-fall function duration setting register (r/w).
9.58 MD1_CFG (5Eh)
Functions routing on INT1 register (r/w). Table 144. FREE_FALL register Table 145. FREE_FALL register description For details refer to Table 146. Table 146. Threshold for free-fall function Table 147. MD1_CFG register Table 148. MD1_CFG register description
9.59 MD2_CFG (5Fh)
Functions routing on INT2 register (r/w). Table 148. MD1_CFG register description (continued) Table 149. MD2_CFG register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 150. MD2_CFG register description
10 Embedded functions register mapping
when FUNC_CFG_EN is set to ‘1’ in FUNC_CFG_ACCESS (01h). permanent damage to the device. Table 151. Registers address map - embedded functions
11 Embedded functions registers description
11.1 PEDO_THS_REG (0Fh)
Table 152. PEDO_THS_REG register default values Table 153. PEDO_THS_REG register description with the device in power-down mode.
11.2 SM_THS (13h)
Significant motion configuration register (r/w). saturation is avoided (e.g. FAST walk). 0: internal full scale = 2 g. Table 154. SM_THS register Table 155. SM_THS register description
11.3 PEDO_DEB_REG (14h)
with the device in power-down mode.
11.4 STEP_COUNT_DELTA (15h)
Time period register for step detection on delta time (r/w). Table 156. PEDO_DEB_REG register default values Table 157. PEDO_DEB_REG register description Table 158. STEP_COUNT_DELTA register Table 159. STEP_COUNT_DELTA register description
- This value is effective if the TIMER_EN bit of the TAP_CFG register is set to 1 and the TIMER_HR bit of
the WAKE_UP_DUR register is set to 0.
Soldering information LSM6DS33
12 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave "Pin 1 Indicator" unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/mems.
specifications, grade definitions and product status are available at: www.st.com.
13.1 LGA-16 package information
Figure 16. LGA 3x3x0.86 16L package outline and dimensions
13.2 LGA-16 packing information
Figure 17. Carrier tape information for LGA-16 package Figure 18. LGA-16 package orientation in carrier tape
Figure 19. Reel information for carrier tape of LGA-16 package Table 160. Reel dimensions for carrier tape of LGA-16 package
Table 161. Document revision history