LSM6DB0 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagrams and pin description
- 1.1 Block diagrams
- 1.2 Pin description
- 2 LSM6DB0 features
- 3 Mechanical characteristics
- 3.1 Accelerometer and gyroscope mechanical characteristics
- 3.2 Accelerometer and gyroscope electrical characteristics
- 3.3 Microprocessor electrical characteristics
- 3.4 Temperature sensor characteristics
- 4 Motion sensor communication interface characteristics
- 4.1 I 2C - inter-IC control interface
- 5 Terminology
- 5.1 Sensitivity
- 5.2 Zero-g and zero rate level
- 6 Device operating modes
- 6.1 Accelerometer and gyroscope operating modes
- 6.2 Gyroscope power modes
- 6.3 Microprocessor operating modes
- 7 Accelerometer and gyroscope functionality
- 7.1 Multiple reads (burst)
- 7.2 FIFO
- 7.2.1 Bypass mode
- 7.2.2 FIFO mode
- 7.2.3 Continuous mode
- 7.2.4 Continuous-to-FIFO mode
- 7.2.5 Bypass-to-Continuous mode
Datasheet sections
- 11.9 INT_GEN_THS1_Z_XL (09h)
- 11.10 INT_GEN_DUR1_XL (0Ah)
- 11.11 REFERENCE_G (0Bh)
- 11.12 INT1_CTRL (0Ch)
- 11.13 INT2_CTRL (0Dh)
- 11.14 WHO_AM_I (0Fh)
- 11.15 CTRL_REG1_G (10h)
- 11.16 CTRL_REG2_G (11h)
- 11.17 CTRL_REG3_G (12h)
- 11.18 ORIENT_CFG_G (13h)
- 11.19 INT_GEN_SRC_G (14h)
- 11.20 OUT_TEMP_L (15h), OUT_TEMP_H (16h)
- 11.21 STATUS_REG (17h)
- 11.22 OUT_X_G (18h - 19h)
- 11.23 OUT_Y_G (1Ah - 1Bh)
- 11.24 OUT_Z_G (1Ch - 1Dh)
- 11.25 CTRL_REG4 (1Eh)
- 11.26 CTRL_REG5_XL (1Fh)
- 11.27 CTRL_REG6_XL (20h)
- 11.28 CTRL_REG7_XL (21h)
- 11.29 CTRL_REG8 (22h)
- 11.30 CTRL_REG9 (23h)
- 11.31 CTRL_REG10 (24h)
- 11.32 INT_GEN_SRC_XL (26h)
- 11.33 STATUS_REG (27h)
- 11.34 OUT_X_XL (28h - 29h)
- 11.35 OUT_Y_XL (2Ah - 2Bh)
- 11.36 OUT_Z_XL (2Ch - 2Dh)
- 11.37 FIFO_CTRL (2Eh)
- 11.38 FIFO_SRC (2Fh)
- 11.39 INT_GEN_CFG_G (30h)
- 11.40 INT_GEN_THS_X_G (31h - 32h)
- 11.41 INT_GEN_THS_Y_G (33h - 34h)
Features
Motion sensors: – ±2/±4/±8 g full scale – ±245/±500/±2000 dps full scale – 6-axis eco power mode down to 1.8 mA – 3 independent acceleration channels and 3 angular rate channels – Embedded temperature sensor – 20 Kbyte data batching – 6-axis and 9-axis quaternions – Self-test – ECOPACK ®, RoHS and “Green” compliant Signal processor: – Brain: ARM-based, 32-bit Cortex-M0 core – Flash memory and SRAM including a bank with error code correction (ECC) 2C master port –I 2C slave port – SPI master/slave – 4-wire UART – 11 programmable GPIOs – Low-power features – 8 x 32-bit dual timers, watchdog timer (WDG), Cortex-M0 system tick (SysTick) timer – Standard 4-wire JTAG and 2-wire SWD – 80 MHz / 32 kHz RC / up to 80 MHz from single-ended external clock
Applications
Sensor hubs and sensor fusion Significant motion-detection and gesture recognition Gaming and geomagnetic rotation vectors Pedometers, step counters and step detectors Calibrated compasses Enhanced navigation and motion tracking
Description
The LSM6DB0 is an advanced low-power high- performance smart sensor system available in a plastic 3x3x1 mm LGA (land grid array) package. The module includes a three-axis accelerometer, 3-axis gyroscope and Cortex-M0 core with Flash, SRAM, dual timers, 2 I 2C (master/slave), 1 SPI (master/slave) and 1 UART (transmitter/receiver). The LSM6DB0 has a full-scale acceleration range of ±2/±4/±8 g and an angular rate range of ±245/±500/±2000 dps. The LSM6DB0 has two operating modes in that the accelerometer and gyroscope sensors can be either activated at the same ODR or the accelerometer can be enabled while the gyroscope is in power-down. The module collects inputs from the accelerometer, gyroscope, compass and several other sensors and elaborates/fuses together 9 or 10 axes (iNemo Engine software) which are provided to the main application processor. For example, quaternions achieve the best compromise in terms of power saving for the overall system. The LSM6DB0 is fully compliant with the Android Kitkat OS. LGA-22 (3x3x1 mm) Table 1. Device summary
1 Block diagrams and pin description
1.1 Block diagrams
Figure 2 and Figure 3, respectively. Figure 1. LSM6DB0 application block diagramMagnetometer
1.2 Pin description
Figure 4. Pin connections Table 2. Pin description
4 DIO2 GPIO2 / I
5 RESET Microcontroller reset VDD
6 DIO3 GPIO3 / I
9 DIO8 GPIO8 / I
10 DIO6 GPIO6 / 16 MHz clock output / Clock 32KHz VDD
11 DIO7 GPIO7 / I 2C1_SCL (master) / SPI_Clock VDD
12 GND 0 V supply
14 VDD (1) Analog and I/O pins power supply
15 DIO10 GPIO10 / spi_input VDD
16 DIO9 GPIO9 / SPI_CS VDD
17 RES Connect to GND
18 RES Connect to GND
19 RES Connect to VDD
20 CAP Connect to GND with ceramic capacitor
21 RES Leave unconnected
22 RES Leave unconnected
- Recommended 100 nF filter capacitor.
- 10 nF (±10%), 16 V. 1 nF minimum value has to be guaranteed under 12 V bias condition.
DIO11 pins of the microcontroller, refer to Figure 1. Table 2. Pin description (continued)
2 LSM6DB0 features
In the LSM6DB0 a complete sensor networking has been created with three additional external sensor connections supported by the I2C bus (eg. compass, pressure sensors, others). External data acquisition is totally configurable with a different data rate selection and different data reads for each slave sensor. To minimize the core’s (Brain) power consumption, dedicated FIFO buffers are available in the inertial sensors to maximize the temporary data storage. The LSM6DB0 can manage standard hub functionalities together with the implementation of complex algorithms for the following applications: – Sensor batching with combination of sensors based on different ODR and related time-stamp information; – Sensor fusion with the support of quaternions, gravity, linear acceleration and orientation data; – Pedometers; – Game rotation vectors; – Geomagnetic rotation vectors (3-axis accelerometer and 3-axis magnetometer); – Compass calibration; – Gyroscope bias estimation and offset compensation; – Accelerometer background calibration; – Significant motion; – Gesture recognition; The device provides optimal flexibility, modularity and scalability in the customization of software routines for the customer. The LSM6DB0 completely offloads the application processor from the computation of sensor fusion, delivering unparalleled low-power consumption at the system level. Owing to the embedded core (Brain) in the device, there is no need for an external processing unit nor storage. The LSM6DB0 is compliant with Android Kitkat OS.
3 Mechanical characteristics
3.1 Accelerometer and gyroscope mechanical characteristics
a. The operational power supply range is from 1.71 V to 3.6 V. Table 3. Mechanical characteristics
3.2 Accelerometer and gyroscope electrical characteristics
Table 4. Electrical characteristics
- Typical specifications are not guaranteed.
- Typical zero-g level offset value after soldering.
- Typical zero-rate level offset value after MSL3 preconditioning.
Table 3. Mechanical characteristics (continued)
- Typical specifications are not guaranteed.
3.3 Microprocessor electrical characteristics
otherwise specified. Typical values are in reference to TA = 25 C, VDD =1.8 V. Table 5. DC and AC parameters
3.4 Temperature sensor characteristics
b. The product is factory calibrated at 3.0 V. Table 6. Temperature sensor characteristics
- Typical specifications are not guaranteed.
- When the accelerometer ODR is set to 10 Hz and the gyroscope block is turned off, the TODR value is 10 Hz.
- The output of the temperature sensor is 0 (typ.) at 25
4 Motion sensor communication interface
4.1 I 2C - inter-IC control interface
Subject to general operating conditions for Vdd and Top. Figure 5. I2C slave timing diagram Note: Measurement points are done at 0.2·VDD and 0.8·VDD, for both ports. Table 7. I2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production.
5 Terminology
5.1 Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors. An angular rate gyroscope is device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time.
5.2 Zero- g and zero rate level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 3. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors. Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time.
6 Device operating modes
6.1 Accelerometer and gyroscope operating modes
Figure 6 depicts both modes of operation from power down. Figure 6. Switching operating modes
6.2 Gyroscope power modes
power-down, low-power and normal mode. To enable low-power mode, the LP_mode bit in CTRL_REG3_G (12h) has to be set to ‘1’. always on, refer to Table 9. is indicated in Table 10 and Table 11.
Table 8. Gyroscope operating mode
- Gyroscope low-power mode is available for G_FS = ±2000 dps.
000 Power-down Power-down
Table 9. Operating mode current consumption
- Gyroscope and accelerometer current consumption typical values based on characterization data.
Table 10. Gyroscope turn-on time
- The table contains the number of samples to be discarded after switching between low-power mode and
6.3 Microprocessor operating modes
80 MHz RC oscillator is powered down. All peripherals, apart from one timer, are disabled. The power consumption is about 800 μA with a 1 kHz clock. consumption in this mode is around 2 mA with an 80 MHz clock. frequency oscillator. The MCU core is also running. Table 11. Accelerometer turn-on time
- The table contains the number of samples to be discarded after switching between power-down mode
Table 12 summarizes the modes of operation and transition times. Table 12. LSM6DB0 operating modes
7 Accelerometer and gyroscope functionality
7.1 Multiple reads (burst)
read, the system automatically restarts from OUT_X_XL (28h - 29h) (see Figure 7). Figure 7. Multiple reads: accelerometer only is read, the system automatically restarts from OUT_X_G (18h - 19h) (see Figure 8). Figure 8. Multiple reads: accelerometer and gyroscope
7.2 FIFO
using the INT1_CTRL (0Ch) register.
(FTH[4:0]) is equal to 0, FIFO_SRC (2Fh) (FTH) goes to ‘0’. FIFO_SRC (2Fh) (OVRN) is equal to '1' if a FIFO slot is overwritten. and the unread samples are 32. The FIFO feature is enabled by writing '1' in CTRL_REG9 (23h) (FIFO_EN). the first sample acquired must be discarded.
7.2.1 Bypass mode
Bypass mode is also used to reset the FIFO when in FIFO mode. is available the old data is overwritten. Figure 9. Bypass mode
7.2.2 FIFO mode
stored in the FIFO until it is overwritten. FIFO depth is limited to FIFO_CTRL (2Eh)(FTH [4:0]) + 1 data. FIFO stops collecting data from the input channels.
Figure 10. FIFO mode
7.2.3 Continuous mode
update: as new data arrives, the older is discarded. samples in FIFO is greater than or equal to FIFO_CTRL (2Eh)(FTH4:0). in register INT1_CTRL (0Ch). becomes saturated and in order to read the contents all at once. unread samples available in FIFO_SRC (2Fh) (FSS[5:0]). Figure 11. Continuous mode
7.2.4 Continuous-to-FIFO mode
(26h)(IA_XL) bit is equal to '0' FIFO operates in Continuous mode. (08h)and INT_GEN_THS1_Z_XL (09h). The CTRL_REG4 (1Eh)(LIR_XL) bit should be set to '1' in order to have latched interrupt. Figure 12. Continuous-to-FIFO mode
7.2.5 Bypass-to-Continuous mode
(26h)(IA_XL) is equal to '1', otherwise FIFO content is reset (Bypass mode). and INT_GEN_THS1_Z_XL (09h). The CTRL_REG4 (1Eh)(LIR_XL) bit should be set to '1' in order to have latched interrupt. Figure 13. Bypass-to-Continuous mode
8 Microprocessor functionality
8.1 ARM Cortex-M0 core
a smaller code size to 8-bit and 16-bit architectures.
8.1.1 Nested vectored interrupt controller (NVIC)
8.2 Power supply scheme
– VDD (c) = 1.8 V to 3.3 V: external power supply for master serial port (DIO6 to DIO10). decoupling capacitor for stable operation. Figure 14. LSM6DB0 digital power supply generation c. For minimum and maximum operating conditions of VDD and VDD1.8 refer to Table 5.
1.8 V supply
8.3 Reset management
is in reset. The BOR is always active in the LSM6DB0 at power-on. at power-on is typically 1 ms with the BOR active.
8.4 Boot mode
the main Flash which contains the user’s program.
8.5 Clock management
Figure 15. Clock tree
- Same clock supply for both I 2C
Microprocessor functionality LSM6DB0 The clock management block distributes clocks from various clock sources to the CPU and peripherals. The clock management block is comprised of the following circuitry and switches: Clock divider: the system contains various clock dividers which allow the frequency of the peripherals and CPU clock sources to be changed. Glitch-free clock switching: the clock sources can be changed dynamically and securely in active mode. Clock gating: the peripherals can have their clocks gated off to reduce their power consumption. Three system clock sources: – RC80M 80 MHz internal RC oscillator which is trimmed at 1% accuracy with factory settings – RC32K 32 kHz internal RC oscillator which is trimmed at 1% accuracy with factory settings – EXTCLK external clock up to 80 MHz Watchdog clock sources: the RC32k or EXTCLK. I 2C clock source: system clock divided by 3. UART clock source: system clock divided by a programmable division factor between 1 and 127. SPI clock source: clock synchronous to the processor. Dual timers: four timers clocked by 32 kHz clock pulses synchronous to the system clock sources and four timers clocked on a clock synchronous to the processor clock. Clock-out capability: either the 32 kHz clock or the output of the divide-by-5 clock can be output on a GPIO for external use.
8.6 General-purpose inputs/outputs (GPIOs)
8.7 Memories
to by the JTAG link if the debug features are connected. Table 13. Alternate function input/output
Microprocessor functionality LSM6DB0
8.8 Timers and watchdogs
The LSM6DB0 includes eight dual timers, one WDG timer, and a SysTick timer.
8.8.1 Dual timer
The dual-timer features are listed below. They consist of two identical programmable free- running counters (FRCs) that can be configured for 32-bit or 16-bit operations. The FRCs operate from a common timer clock which must be synchronous to the CPU clock. – 16/32-bit down counter – Interrupt generation when the counter reaches zero – Free-running mode: the counter operates continuously and wraps around to its maximum value each time it reaches zero. – Periodic mode: the counter operates continuously by reloading the programmed value each time it reaches zero. – One-shot mode: the counter decrements to zero and then halts until it is reprogrammed – The timer clock prescaler factors are 1, 16, or 256
8.8.2 Watchdog (WDG) timer
The WDG timer is a 32-bit down counter which operates on either the RC32k clock or the EXTCLK clock. It can generate an interrupt and/or a reset when the counter reaches zero.
8.8.3 System tick (SysTick) timer
The SysTick timer provides a 24-bit clear-on-write, decrementing counter which wraps around when it reaches zero. It operates on the CPU clock.
LSM6DB0 Microprocessor functionality
8.9 Communication interfaces
8.10 I²C bus
The LSM6DB0 provides two I²C interfaces which can operate in master and slave modes. They can support standard mode and fast mode.
8.11 Universal asynchronous receiver transmitter (UART)
The UART interface (IO0, IO1, IO2, IO3 pins) of the LSM6DB0 supports the following maximum baud rates: – 921600 bps in UART mode – 460800 bps in Infrared data association (IrDA) mode – 115200 bps in low-power IrDA mode The interface supports the IrDA serial infrared (SIR) ENDEC and also provides flow control capabilities through the hardware management of the clear-to-send (CTS) and request-to- send (RTS) signals. For more details, refer to the ARM document “DDIO83G_uart_pl011_trm.pdf”.
8.12 Serial peripheral interface (SPI)
The SPI interface operates as a master or slave interface. This interface supports 6 MHz bit rate max in slave mode and 16 MHz bit rate max in master mode due to the limitation of the IOs. A programmable clock prescaler inside the SPI allows the input clock to be divided by a factor of 2 to 254 in steps of two to provide the serial output clock. The SPI interface provides data frames between 4 and 16 bits long. For more details, refer to the ARM document “DDIO94C_ssp_PL022_trm.pdf”.
8.13 JTAG and SW debug support
SW_TDIO and SW_TCK respectively. setting the IO9 pin to zero. During reset, the SW debug mode is selected by default. Figure 16. Debug mode selection timing
- RESETN needs an external pull-up if not driven
- Default option depending on software configuration
Table 14. Debug mode selection
9 Absolute maximum ratings
9.1 Accelerometer and gyroscope
9.2 Microprocessor
Absolute maximum ratings are those values above which damage to the device may occur. Table 16. Absolute maximum ratings for microprocessor Table 15. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
10 Register mapping
Table 17. Motion sensor registers
permanent damage to the device. table must not be accessed and the content stored on those registers must not be changed. Table 17. Motion sensor registers (continued)
11 Register description
7 bits, are used to identify them and to write the data through the serial interface.
11.1 INT_GEN_CFG2_XL (01h)
Linear acceleration sensor interrupt generator 2 configuration register (r/w). Table 19. INT_GEN_CFG2_XL register description Table 18. INT_GEN_CFG2_XL register AOI2_XL And/Or combination of accelerometer’s interrupt 2 events. Default value: 0. 6D2 6 direction detection function for interrupt 2. Default value: 0. recognition. Default value: 0. recognition. Default value: 0. recognition. Default value: 0. recognition. Default value: 0. recognition. Default value: 0. recognition. Default value: 0.
11.2 INT_GEN_THS2_XL (02h)
Linear acceleration sensor interrupt 2 threshold register (r/w). Table 21. INT_GEN_THS2_XL register description
11.3 INT_GEN_DUR2_XL (03h)
Linear acceleration sensor interrupt 2 duration register (r/w). Table 23. INT_GEN_DUR2_XL register description
11.4 ACT_THS (04h)
Activity threshold register. Table 25. ACT_THS register description
11.5 ACT_DUR (05h)
Inactivity duration register. Table 27. ACT_DUR register description Table 20. INT_GEN_THS2_XL register Table 22. INT_GEN_DUR2_XL register WAIT2_XL Wait function enable on duration counter. Default value: 0. Table 24. ACT_THS register ACT_THS [6:0] Inactivity threshold. Default value: 000 0000. Table 26. ACT_DUR register
11.6 INT_GEN_CFG1_XL (06h)
Linear acceleration sensor interrupt 1 generator configuration register. Table 29. INT_GEN_CFG1_XL register description
11.7 INT_GEN_THS1_X_XL (07h)
Linear acceleration sensor interrupt 1 threshold register. Table 31. INT_GEN_THS1_X_XL register description Table 28. INT_GEN_CFG1_XL register Table 30. INT_GEN_THS1_X_XL register
11.8 INT_GEN_THS1_Y_XL (08h)
Linear acceleration sensor interrupt 1 threshold register. Table 33. INT_GEN_THS1_Y_XL register description
11.9 INT_GEN_THS1_Z_XL (09h)
Linear acceleration sensor interrupt 1 threshold register. Table 35. INT_GEN_THS_Z_XL register description
11.10 INT_GEN_DUR1_XL (0Ah)
Linear acceleration sensor interrupt 1 duration register. Table 36. INT_GEN_DUR1_XL register Table 37. INT_GEN_DUR1_XL register description
11.11 REFERENCE_G (0Bh)
Table 38. REFERENCE_G register Table 39. REFERENCE_G register description Table 32. INT_GEN_THS1_Y_XL register Table 34. INT_GEN_THS1_Z_XL register REF_G [7:0] Reference value for gyroscope’s digital high-pass filter (r/w).
11.12 INT1_CTRL (0Ch)
Table 40. INT1_CTRL register Table 41. INT1_CTRL register description
11.13 INT2_CTRL (0Dh)
Table 42. INT2_CTRL register
Table 43. INT2_CTRL register description
11.14 WHO_AM_I (0Fh)
11.15 CTRL_REG1_G (10h)
Angular rate sensor control register 1. Table 45. CTRL_REG1_G register Table 46. CTRL_REG1_G register description Table 44. WHO_AM_I register
- This bit must be set to ‘0’ for the correct operation of the device
Table 47. ODR and BW configuration setting (after LPF1)
- Values in the table are indicative and can vary proportionally with the specific ODR value.
Table 48. ODR and BW configuration setting (after LPF2)
- Values in the table are indicative and can vary proportionally with the specific ODR value.
11.16 CTRL_REG2_G (11h)
Angular rate sensor control register 2. Figure 17. INT_SEL and OUT_SEL configuration gyroscope block diagram
11.17 CTRL_REG3_G (12h)
Angular rate sensor control register 3. Table 49. CTRL_REG2_G register
- These bits must be set to ‘0’ for the correct operation of the device
Table 50. CTRL_REG2_G register description Table 51. CTRL_REG3_G register
- These bits must be set to ‘0’ for the correct operation of the device
Table 52. CTRL_REG3_G register description
11.18 ORIENT_CFG_G (13h)
Angular rate sensor sign and orientation register. Table 54. ORIENT_CFG_G register Table 55. ORIENT_CFG_G register description
11.19 INT_GEN_SRC_G (14h)
Angular rate sensor interrupt source register. Table 53. Gyroscope high-pass filter cutoff frequency configuration Hz
- Values in the table are indicative and can vary proportionally with the specific ODR value.
- These bits must be set to ‘0’ for the correct operation of the device
Table 56. INT_GEN_SRC_G register
0 IA_G ZH_G ZL_G YH_G YL_G XH_G XL_G
11.20 OUT_TEMP_L (15h), OUT_TEMP_H (16h)
11.21 STATUS_REG (17h)
Table 61. STATUS_REG register Table 57. INT_GEN_SRC_G register description Table 58. OUT_TEMP_L register Table 59. OUT_TEMP_H register Table 60. OUT_TEMP register description Temp [11:0] Temperature sensor output data. The value is expressed as two’s complement sign extended on the MSB.
0 IG_XL IG_G INACT BOOT_
11.22 OUT_X_G (18h - 19h)
16-bit word in two’s complement.
11.23 OUT_Y_G (1Ah - 1Bh)
16-bit word in two’s complement.
11.24 OUT_Z_G (1Ch - 1Dh)
16-bit word in two’s complement.
11.25 CTRL_REG4 (1Eh)
Table 62. STATUS_REG register description Table 63. CTRL_REG4 register
- These bits must be set to ‘0’ for the correct operation of the device
11.26 CTRL_REG5_XL (1Fh)
Linear acceleration sensor control register 5.
11.27 CTRL_REG6_XL (20h)
Linear acceleration sensor control register 6. Table 67. CTRL_REG6_XL register Table 64. CTRL_REG4 register description Table 65. CTRL_REG5_XL register
- These bits must be set to ‘0’ for the correct operation of the device
Table 66. CTRL_REG5_XL register description
Table 68. CTRL_REG6_XL register description available frequencies when only the accelerometer is activated.
11.28 CTRL_REG7_XL (21h)
Linear acceleration sensor control register 7. Output data rate and power mode selection. Default value: 000 (see Table 69). Accelerometer Full Scale selection. Default value: 00. Bandwidth selection. Default value: 0. Anti-aliasing filter bandwidth selection. Default value: 00. Table 69. ODR register setting (accelerometer only mode) Table 70. CTRL_REG7_XL register
- These bits must be set to ‘0’ for the correct operation of the device
11.29 CTRL_REG8 (22h)
Table 71. CTRL_REG7_XL register description (0: disabled; 1: enabled). Refer to Table 72. high-pass filter depends on the selected ODR. Refer to Table 72. FDS Filtered data selection. Default value: 0. HPIS1 High Pass filter enabled for acceleration sensor interrupt function on Interrupt. Default value: 0. Table 72. Low-pass cutoff frequency in high resolution mode (HR = 1) Table 73. CTRL_REG8 register
- This bit must be set to ‘0’ for the correct operation of the device.
Table 74. CTRL_REG8 register description BLE Big/Little Endian data selection. Default value 0. This bit is cleared by hardware after next flash boot.
- Boot request is executed as soon as the internal oscillator is turned-on. It is possible to set the bit while in power-down
mode, in this case it will be served at the next normal mode or sleep mode.
11.30 CTRL_REG9 (23h)
11.31 CTRL_REG10 (24h)
Table 77. CTRL_REG10 register Table 75. CTRL_REG9 register
- These bits must be set to ‘0’ for the correct operation of the device
Table 76. CTRL_REG9 register description
- These bits must be set to ‘0’ for the correct operation of the device
Table 78. CTRL_REG10 register description
11.32 INT_GEN_SRC_XL (26h)
Linear acceleration sensor interrupt source register.
11.33 STATUS_REG (27h)
Table 79. INT_GEN_SRC_XL register
0 IA_XL ZH_XL ZL_XL YH_XL YL_XL XH_XL XL_XL
Table 80. INT_GEN_SRC_XL register description Table 81. STATUS_REG register Table 82. STATUS_REG register description
11.34 OUT_X_XL (28h - 29h)
11.35 OUT_Y_XL (2Ah - 2Bh)
11.36 OUT_Z_XL (2Ch - 2Dh)
11.37 FIFO_CTRL (2Eh)
Table 83. FIFO_CTRL register Table 84. FIFO_CTRL register description For further details refer to Table 85. Table 85. FIFO mode selection 0 0 1 FIFO mode. Stop collecting data when FIFO is full.
11.38 FIFO_SRC (2Fh)
FIFO status control register. Table 86. FIFO_SRC register Table 87. FIFO_SRC register description
11.39 INT_GEN_CFG_G (30h)
Angular rate sensor interrupt generator configuration register. For further details refer to Table 88. FSS [5:0] Number of unread samples stored into FIFO. For further details refer to Table 88. Table 88. FIFO_SRC example: OVR/FSS details
- When the number of unread samples in FIFO is greater than the threshold level set in register FIFO_CTRL
Table 89. INT_GEN_CFG_G register
Table 90. INT_GEN_CFG_G register description
11.40 INT_GEN_THS_X_G (31h - 32h)
bit word in two’s complement. Table 93. INT_GEN_THS_X_G register description XLIE_G Enable interrupt generation on gyroscope’s pitch (X) axis low event. Default value: 0. Table 91. INT_GEN_THS_XH_G register Table 92. INT_GEN_THS_XL_G register THS_G_X [14:0] Angular rate sensor interrupt threshold on pitch (X) axis.
11.41 INT_GEN_THS_Y_G (33h - 34h)
bit word in two’s complement. Table 96. INT_GEN_THS_Y_G register description
11.42 INT_GEN_THS_Z_G (35h - 36h)
bit word in two’s complement. Table 99. INT_GEN_THS_Z_G register description
11.43 INT_GEN_DUR_G (37h)
Angular rate sensor interrupt generator duration register. Table 100. INT_GEN_DUR_G register Table 94. INT_GEN_THS_YH_G register
- This bit must be set to ‘0’ for the correct operation of the device
Table 95. INT_GEN_THS_YL_G register THS_G_Y [14:0] Angular rate sensor interrupt threshold on roll (Y) axis. Table 97. INT_GEN_THS_ZH_G register
- This bit must be set to ‘0’ for the correct operation of the device
Table 98. INT_GEN_THS_ZL_G register THS_G_Z [14:0] Angular rate sensor interrupt thresholds on yaw (Z) axis.
Table 101. INT_GEN_DUR_G register description The DUR_G [6:0] bits set the minimum duration of the interrupt event to be recognized. Duration steps and maximum values depend on the ODR chosen. equal to the value of the duration counter register. For further details refer to Figure 18 and Figure 19. Figure 18. Wait bit disabled
- Wait bit = ‘0’ /barb2right/barb2rightInterrupt disabled as soon as condition is no longer valid (ex: Rate value below threshold) Rate (dps) Rate Threshold t(n) t(n) t(n) Interrupt Counter Duration Value “Wait” Disabled
Figure 19. Wait bit enabled
LSM6DB0 Soldering information
12 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/mems.
specifications, grade definitions and product status are available at: www.st.com. Figure 20. LGA-22: mechanical data and package dimensions
Table 102. Document revision history