LSM330D STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Module specifications
- 2.1 Mechanical characteristics
- 2.2 Electrical characteristics
- 2.3 Temperature sensor characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 I2C - inter IC control interface
- 2.5 Absolute maximum ratings
- 3 Terminology
- 3.1 Sensitivity
- 3.2 Zero level
- 4 Functionality
- 4.1 Accelerometer
- 4.1.1 Normal mode, Low power mode
- 4.1.2 Self-test
- 4.1.5 FIFO
- 4.1.6 Bypass mode
- 4.1.7 FIFO mode
- 4.1.8 Stream mode
- 4.1.9 Stream-to-FIFO mode
- 4.1.10 Retrieve data from FIFO
- 4.2 Gyroscope digital main blocks
- 4.3 FIFO
- 4.3.1 Bypass mode
Datasheet sections
- 8.11 OUT_Z_L _A, OUT_Z_H_A
- 8.12 FIFO_CTRL_REG_A (2Eh)
- 8.13 FIFO_SRC_REG_A (2Fh)
- 8.14 INT1_CFG_A (30h)
- 8.15 INT1_SRC_A (31h)
- 8.16 INT1_THS_A (32h)
- 8.17 INT1_DURATION_A (33h)
- 8.18 CLICK_CFG _A (38h)
- 8.19 CLICK_SRC_A (39h)
- 8.20 CLICK_THS_A (3Ah)
- 8.21 TIME_LIMIT_A (3Bh)
- 8.22 TIME_LATENCY_A (3Ch)
- 8.23 TIME WINDOW_A (3Dh)
- 8.24 Act_THS (3Eh)
- 8.25 Act_DUR (3Fh)
- 8.26 WHO_AM_I_G (0Fh)
- 8.27 CTRL_REG1_G (20h)
- 8.28 CTRL_REG2_G (21h)
- 8.29 CTRL_REG3_G (22h)
- 8.30 CTRL_REG4_G (23h)
- 8.31 CTRL_REG5_G (24h)
- 8.32 REFERENCE_G (25h)
- 8.33 OUT_TEMP_G (26h)
- 8.34 STATUS_REG_G (27h)
- 8.35 OUT_X_L_G, OUT_X_H_G
- 8.36 OUT_Y_L_G, OUT_Y_H_G
- 8.37 OUT_Z_L_G, OUT_Z_H_G
- 8.38 FIFO_CTRL_REG_G (2Eh)
- 8.39 FIFO_SRC_REG_G (2Fh)
- 8.40 INT1_CFG_G (30h)
- 8.41 INT1_SRC_G (31h)
- 8.42 INT1_THS_XH_G (32h)
- 8.43 INT1_THS_XL_G (33h)
Features
■ Analog supply voltage: 2.4 V to 3.6 V ■ Digital supply voltage IOs: 1.8 V ■ Low power mode ■ Power-down mode ■ 3 independent acceleration channels and 3 angular rate channels ■ ±2 g/±4 g/±8 g/±16 g dynamically selectable full scale ■ ±250/±500/±2000 dps dynamically selectable full scale ■ SPI/I2C serial interface (16-bit data output) ■ Programmable interrupt generator for free-fall and motion detection ■ ECOPACK® RoHS and “Green” compliant Application ■ GPS navigation systems ■ Impact recognition and logging ■ Gaming and virtual reality input devices ■ Motion activated functions ■ Intelligent power saving for handheld devices ■ Vibration monitoring and compensation ■ Free-fall detection ■ 6D orientation detection
Description
The LSM330D is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope. ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM330D has dynamically user-selectable full scale acceleration range of ±2 g/±4 g/±8 g/±16 g and angular rate of ±250/±500/±2000 deg/sec. The accelerometer and gyroscope sensors can be either activated or separately put in Low power/Power-down mode for applications optimized for power saving. The LSM330D is available in a plastic land grid array (LGA) package. Table 1. Device summary
1 Block diagram and pin description
1.1 Block diagram
Figure 1. LSM330D block diagram
1.2 Pin description
Figure 2. Pin connection Table 2. Pin description
1 Res Reserved connect to GND
2 Res Reserved connect to GND
3 Res Reserved connect to GND
4 Res Reserved connect to GND
6 Vdd Power supply
7 Vdd Power supply
8 Vdd Power supply
9 Res Reserved connect to Vdd
10 Res Reserved connect to Vdd
11 Res Reserved connect to Vdd
12 Res Reserved connect to Vdd
13 Res Reserved connect to Vdd
14 Res Leave unconnected
15 DRDY_G/
16 INT1_G Gyroscope interrupt signal 1
17 INT2_A Accelerometer interrupt signal 2
18 INT1_A Accelerometer interrupt signal 1
19 Vdd_IO Power supply for IO pins
20 CS_G
21 CS_A
22 SCL_A/G I2C serial clock (SCL)
23 Vdd_IO Power supply for IO pins
24 SDO_G Gyroscope: SPI serial data output (SDO) /
25 SDO_A Accelerometer :SPI serial data output (SDO) /
26 SDA_A/G I2C serial data (SDA) / SPI serial data input (SDI)
27 DEN_G Gyroscope data enable
28 GND 0 V supply
Table 2. Pin description (continued)
2 Module specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics G_SoDr Angular rate sensitivity change vs. G_TCOff Zero-rate level change vs.
1001 Ta bl e 1 9
2.2 Electrical characteristics
- Typical specifications are not guaranteed.
- Verified by wafer level test and measurement of initial offset and sensitivity.
- Typical zero- g level offset value after MSL3 preconditioning.
- Offset can be eliminated by enabling the built-in high-pass filter.
Table 3. Mechanical characteristics (continued) Table 4. Electrical characteristics
- Typical specifications are not guaranteed.
- Sleep mode introduces a faster turn-on time compared to Power-down mode.
2.3 Temperature sensor characteristics
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and TOP. b. The product is factory calibrated at 3.0 V. Table 5. Electrical characteristics
- Typical specifications are not guaranteed.
Table 6. SPI slave timing values
- Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results. Not
Figure 3. SPI slave timing diagram (c)(d)
- Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.
2.4.2 I 2C - inter IC control interface
Subject to general operating conditions for Vdd and TOP. c. The SDO_A output line features an internal pull-up. d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports. Table 7. I 2C slave timing values
- SCL (SCL_A/G pin), SDA (SDA_A/G pin)
- Cb = total capacitance of one bus line, in pF
Figure 4. I 2C slave timing diagram(e) e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
2.5 Absolute maximum ratings
Table 8. Absolute maximum ratings (1)
- Supply voltage on any pin should never exceed 4.8 V.
3 Terminology
3.1 Sensitivity
Linear acceleration sensitivity can be determined e.g. by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors. Angular Rate Sensitivity describes the angular rate gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and also very little over time.
3.2 Zero level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X axis and Y axes, whereas the Z axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 3. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors. Angular rate zero-rate level describes the actual output value if there is no angular rate present. zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and over time.
4 Functionality
signal according to a programmed acceleration event along the enabled axes.
4.1 Accelerometer
4.1.1 Normal mode, Low power mode
resolution, while Low power mode further reduces current consumption.
4.1.2 Self-test
the interface chip are within the defined specifications. Table 9. Operating mode selection
4.1.3 6D/4D orient ation detection The LSM330D includes 6D/4D orientation detection. In this configuration the interrupt is generated when the device is stable in a known direction. In 4D configuration, Z axis position detection is disabled. 4.1.4 “Sleep-to-wake” and “Return to sleep” The LSM330D can be programmed to automatically switch to Low power mode upon recognition of a determined event. Once the event condition is over, the device returns to the preset Normal mode. To enable this function, the desired threshold value must be stored in the Act_THS register, while the duration value is written in the Act_DUR register. When the internally high-pass filtered acceleration becomes lower than the threshold value on all the three axes, the device automatically switches to Low power mode (10Hz ODR). During this condition, the ODRx bits and LPen bit in the CTRL_REG1_G register and the HR bit in the CTRL_REG3_G register are not considered. When the acceleration goes back over the threshold (on at least one axis), the system restores the operating mode and ODRs as per the CTRL_REG1_G register and CTRL_REG3_G register settings. Accelerometer digital main blocks
4.1.5 FIFO
The LSM330D embeds 32 slots of data FIFO for each of the three output channels: X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work accordingly in four different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FIFO_MODE bits in the FIFO_CTRL_REG_A register. Programmable watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on the INT1_A/INT2_A pin (configured through the FIFO_CTRL_REG_A register).
4.1.6 Bypass mode
In Bypass mode, the FIFO is not operational and for this reason it remains empty. For each channel only the first address is used. The remaining FIFO slots are empty.
4.1.7 FIFO mode
In FIFO mode, data from the X, Y and Z channels are stored into the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit in the FIFO_CTRL_REG_A register in order to be raised when the FIFO is filled to the level specified into the FIFO_WTMK_LEVEL bits of the FIFO_CTRL_REG_A register. The FIFO continues filling until it is full (32 slots of data for X, Y and Z). When full, the FIFO stops collecting data from the input channels.
4.1.8 Stream mode
In Stream mode, data from X, Y and Z measurement are stored into the FIFO. A watermark interrupt can be enabled and set as in FIFO mode.The FIFO continues filling until it is full (32 slots of data for X, Y and Z). When full, the FIFO discards the older data as the new data arrives.
4.1.9 Stream-to-FIFO mode
In Stream-to-FIFO mode, data from X, Y and Z measurement is stored in the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit in the FIFO_CTRL_REG_A register) in order to be raised when the FIFO is filled to the level specified in the FIFO_WTMK_LEVEL bits of the FIFO_CTRL_REG_A register. The FIFO continues filling until it is full (32 slots of 8 -bit data for X, Y and Z). When full, the FIFO discards the older data as the data new arrives. Once trigger event occurs, the FIFO starts operating in FIFO mode.
4.1.10 Retrieve data from FIFO
FIFO data is read through OUT_X_L_A, OUT_X_H_A, OUT_Y_L_A, OUT_Y_H_A and OUT_Z_L _A, OUT_Z_H_A. When the FIFO is in Stream, Trigger or FIFO mode, a read OUT_Z_H_A registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X_L_A, OUT_X_H_A, OUT_Y_L_A, OUT_Y_H_A and OUT_Z_L _A, OUT_Z_H_A registers and both single read and read_burst operations can be used.
4.2 Gyroscope digital main blocks
Figure 5. Gyroscope block diagram
4.3 FIFO
in the FIFO_CTRL_REG_G register.
4.3.1 Bypass mode
FIFO slots are empty. When new data is available the old data is overwritten.
Figure 6. Bypass mode
4.3.2 FIFO mode
collection, the FIFO_CTRL_REG_G register must be written back to Bypass mode. FIFO mode is represented in Figure 7: FIFO mode.
Figure 7. FIFO mode
4.3.3 Stream mode
Stream mode is represented in Figure 8: Stream mode.
Figure 8. Stream mode
4.3.4 Bypass-to-stream mode
mode. Refer to Figure 9 below. Figure 9. Bypass-to-stream mode
4.3.5 Stream-to-FIFO mode
the FIFO starts operating in FIFO mode. Refer to Figure 10: Trigger stream mode.
Figure 10. Trigger stream mode
4.3.6 Retrieve data from FIFO
4.4 Level-sensitive / Edge-sensitive data enable
sensitive or Edge-sensitive trigger.
Figure 11. Level-sensitive trigger stamping (LVLen = 1; EXTRen = 0)
4.4.1 Level-sensitive trigger stamping
4.4.2 Edge-sensitive trigger
Figure 12. Edge-sensitive trigger
4.5 Factory calibration
use of the device without further calibration.
5 Application hints
Figure 13. LSM330D electrical connection
5.1 External capacitors
device (common design practice). acceleration/angular rate data are selectable and accessible through the SPI/I2C interface. completely programmed by the user though the SPI/I2C interface.
5.2 Soldering information
qualified for soldering heat resistance according to JEDEC J-STD-020D. Leave “Pin 1 Indicator” unconnected during soldering.
6 Digital interfaces
To select/exploit the I2C interface, the CS line must be tied high (i.e. connected to Vdd_IO).
6.1 I 2C serial interface
whose content can also be read back. The relevant I2C terminology is provided in the table below. Table 10. Serial interface pin description Table 11. Serial interface pin description
6.1.1 I 2C operation
allow multiple data read/write. other function, it can hold the clock line, SCL, LOW to force the transmitter into a wait state. Table 12. Transfer when master is writing one byte to slave Table 13. Transfer when master is writing multiple bytes to slave Table 14. Transfer when master is receiving (reading) one byte of data from slave Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
terminated by the generation of a STOP (SP) condition. address of first register to be read. Angular rate sensor: the default (factory) 7-bit slave address is 110101xb. Table 16. Linear acceleration SAD+Read/Write patterns Table 17. Angular rate SAD+Read/Write patterns
6.2 SPI bus interface
Figure 14. Read and write protocol of SPC and should be captured at the rising edge of SPC. from the device is read. In the latter case, the chip drives SDO at the start of bit 8. bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address is auto-incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. the MS bit is ‘1’, the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
6.2.1 SPI read
Figure 15. SPI read protocol performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Figure 16. Multiple-byte SPI read protocol (2-byte example)
6.2.2 SPI write
Figure 17. SPI write protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register. Figure 18. Multiple bytes SPI write protocol (2 bytes example)
6.2.3 SPI read in 3-wire mode
Figure 19. SPI read protocol in 3-wire mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Multiple read command is also available in 3-wire mode.
7 Register mapping
Table 18. Register address map
Table 18. Register address map (continued)
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
8 Register descriptions
are used to identify them and to write the data through the serial interface.
8.1 CTRL_REG1_A (20h)
the frequencies resulting from the ODR<3:0> combinations. Table 19. CTRL_REG1_A register Table 20. CTRL_REG1_A description Table 21. Data rate configuration
8.2 CTRL_REG2_A (21h)
8.3 CTRL_REG3_A (22h)
Table 22. CTRL_REG2_A register Table 23. CTRL_REG2_A description HPCLICK High-pass filter enabled for CLICK function. Table 24. High-pass filter mode configuration Table 25. CTRL_REG3_A register
- This bit has to be set ‘0’ for correct operation
Table 26. CTRL_REG3_A description I1_CLICK CLICK interrupt on INT1_A. Default value 0. I1_AOI1 AOI1 interrupt on INT1_A. Default value 0.
8.4 CTRL_REG4_A (23h)
8.5 CTRL_REG5_A (24h)
I1_DRDY1 DRDY1 interrupt on INT1_A. Default value 0. I1_DRDY2 DRDY2 interrupt on INT1_A. Default value 0. I1_WTM FIFO watermark interrupt on INT1_A. Default value 0. I1_OVERRUN FIFO Overrun interrupt on INT1_A. Default value 0. Table 26. CTRL_REG3_A description (continued) Table 27. CTRL_REG4_A register
- This bit must be set to ‘0’ for correct operation.
Table 28. CTRL_REG4_A description BLE Big/little endian data selection. Default value 0. (0: 4-wire interface; 1: 3-wire interface). Table 29. CTRL_REG5_A register
- This bit must be set to ‘0’ for correct operation.
Table 30. CTRL_REG5_A description
8.6 CTRL_REG6_A (25h)
8.7 REFERENCE_A (26h)
8.8 STATUS_REG_A (27h)
cleared by reading INT1_SRC itself. Default value: 0. Table 30. CTRL_REG5_A description (continued) Table 31. CTRL_REG6_A register
- This bit must be set to ‘0’ for correct operation.
Table 32. CTRL_REG6 description I2_CLICKen Click interrupt on INT2_A. Default value 0. I2_INT1 Interrupt 1 function enabled on INT2_A. Default 0. H_LACTIVE 0: interrupt active high; 1: interrupt active low. Table 33. REFERENCE_A register Table 34. REFERENCE_A register description Table 35. STATUS_REG_A register Table 36. STATUS_REG_A register description
X-axis acceleration data. The value is expressed in two’s complement. Y -axis acceleration data. The value is expressed in two’s complement. Z-axis acceleration data. The value is expressed in two’s complement.
8.12 FIFO_CTRL_REG_A (2Eh)
Table 36. STATUS_REG_A register description (continued) Table 37. FIFO_CTRL_REG_A register Table 38. FIFO_CTRL_REG_A register description
8.13 FIFO_SRC_REG_A (2Fh)
8.14 INT1_CFG_A (30h)
Table 39. FIFO mode configuration Table 40. FIFO_SRC_REG_A register Table 41. FIFO_SRC_REG_A description Table 42. INT1_CFG_A register Table 43. INT1_CFG_A description
The content of this register is loaded at boot. A write operation at this address is possible only after system boot. The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. inside a “known zone”. The interrupt signal remains until orientation is within the zone.
8.15 INT1_SRC_A (31h)
Table 44. Interrupt mode Table 43. INT1_CFG_A description (continued) Table 45. INT1_SRC_A register
- This bit must be set to ‘0’ for correct operation.
Table 46. INT1_SRC_A description
Interrupt 1 source register. Read only register.
8.16 INT1_THS_A (32h)
8.17 INT1_DURATION_A (33h)
steps and maximum values depend on the ODR chosen. Table 46. INT1_SRC_A description (continued) Table 47. INT1_THS_A register
- This bit has to be set ‘0’ for correct operation.
Table 48. INT1_THS_A description Table 49. INT1_DURATION_A register
- This bit must be set ‘0’ for correct operation.
Table 50. INT1_DURATION_A description
8.18 CLICK_CFG _A (38h)
8.19 CLICK_SRC_A (39h)
Table 51. CLICK_CFG_A register Table 52. CLICK_CFG_A description Table 53. CLICK_SRC_A register Table 54. CLICK_SRC_A description
8.20 CLICK_THS_A (3Ah)
8.21 TIME_LIMIT_A (3Bh)
8.22 TIME_LATENCY_A (3Ch)
8.23 TIME WINDOW_A (3Dh)
Table 55. CLICK_THS_A register Table 56. CLICK_SRC_A description Table 57. TIME_LIMIT_A register Table 58. TIME_LIMIT_A description Table 59. TIME_LATENCY_A register Table 60. TIME_LATENCY_A description Table 61. TIME_WINDOW_A register
8.24 Act_THS (3Eh)
8.25 Act_DUR (3Fh)
8.26 WHO_AM_I_G (0Fh)
Device identification register.
8.27 CTRL_REG1_G (20h)
Table 62. TIME_WINDOW_A description Table 63. Act_THS register Table 64. Act_THS description Table 65. Act_DUR register Table 66. Act_DUR description Table 67. WHO_AM_I_G register Table 68. CTRL_REG1_G register Table 69. CTRL_REG1_G description
DR<1:0> is used to set ODR selection. BW <1:0> is used to set bandwidth selection. Table 70 below provides all the frequencies resulting from the DR / BW bit combinations. Table 70. DR and BW configuration setting
8.28 CTRL_REG2_G (21h)
Table 71. Power mode selection configuration Table 72. CTRL_REG2_G register Table 73. CTRL_REG2_G description Table 74. High-pass filter mode configuration Table 75. High-pass filter cut-off frequency configuration [Hz]
8.29 CTRL_REG3_G (22h)
8.30 CTRL_REG4_G (23h)
Table 75. High-pass filter cut-off frequency configuration [Hz] (continued) Table 76. CTRL_REG3_G register Table 77. CTRL_REG3_G description Table 78. CTRL_REG4_G register Table 79. CTRL_REG4_G description BLE Big/little endian data selection. Default value 0. (0: 3-wire Read mode disabled; 1: 3-wire read enabled).
8.31 CTRL_REG5_G (24h)
Figure 20. INT1_Sel and Out_Sel configuration block diagram
8.32 REFERENCE_G (25h)
Table 80. CTRL_REG5_G register Table 81. CTRL_REG5_G description Table 82. REFERENCE_G register
8.33 OUT_TEMP_G (26h)
8.34 STATUS_REG_G (27h)
X-axis angular rate data. The value is expressed as two’s complement. Table 83. REFERENCE_G register description Table 84. OUT_TEMP_G register Table 85. OUT_TEMP_G register description Table 86. STATUS_REG_G register Table 87. STATUS_REG description
Y -axis angular rate data. The value is expressed as two’s complement. Z-axis angular rate data. The value is expressed as two’s complement.
8.38 FIFO_CTRL_REG_G (2Eh)
8.39 FIFO_SRC_REG_G (2Fh)
Table 88. FIFO_CTRL_REG_G register Table 89. FIFO_CTRL_REG_G description Table 90. FIFO mode configuration Table 91. FIFO_SRC_REG_G register Table 92. FIFO_SRC_REG_G description
8.40 INT1_CFG_G (30h)
Configuration register for interrupt source.
8.41 INT1_SRC_G (31h)
Table 92. FIFO_SRC_REG_G description (continued) Table 93. INT1_CFG_G register Table 94. INT1_CFG_G description Cleared by reading INT1_SRC_G reg. Table 95. INT1_SRC_G register
0 I A Z HZ LY HY LX HX L
Interrupt source register. Read only register.
8.42 INT1_THS_XH_G (32h)
8.43 INT1_THS_XL_G (33h)
8.44 INT1_THS_YH _G (34h)
Table 96. INT1_SRC_G description Table 97. INT1_THS_XH_G register Table 98. INT1_THS_XH_G description Table 99. INT1_THS_XL_G register Table 100. INT1_THS_XL_G description Table 101. INT1_THS_YH_G register
8.45 INT1_THS_YL_G (35h)
8.46 INT1_THS_ZH_G (36h)
8.47 INT1_THS_ZL_G (37h)
8.48 INT1_DURATION_G (38h)
Table 102. INT1_THS_YH_G description Table 103. INT1_THS_YL_G register Table 104. INT1_THS_YL_G description Table 105. INT1_THS_ZH_G register Table 106. INT1_THS_ZH_G description Table 107. INT1_THS_ZL_G register Table 108. INT1_THS_ZL_G description Table 109. INT1_DURATION_G register
and maximum values depend on the ODR chosen. Figure 21. Wait disabled Table 110. INT1_DURATION_G description
Figure 22. Wait enabled
9 Package information
specifications, grade definitions and product status are available at: www.st.com. Figure 23. LGA-28L (3x5.5x1.0 mm) drawing Table 111. LGA-28L (3x5.5x1.0 mm) mechanical data
Table 112. Document revision history 02-Dec-2011 1 Initial release.