LSM303DLH STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 47
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Module specifications
- 2.1 Mechanical characteristics
- 2.2 Electrical characteristics
- 2.3 Communication interface characteristics
- 2.3.1 Accelerometer sensor I2C - inter IC control interface
- 2.3.2 Magnetic field sensing I2C digital interface
- 3 Absolute maximum ratings
- 4 Terminology
- 4.1 Linear acceleration sensitivity
- 4.2 Zero-g level
- 4.3 Sleep-to-wakeup
- 5 Functionality
- 5.1 Factory calibration
- 5.2 Linear acceleration self-test operation
- 5.3 Magnetic self-test operation
- 6 Application hints
- 6.1 External capacitors
- 6.2 Pull-up resistors
- 6.3 Digital interface power supply
- 6.4 Soldering information
- 6.5 High current wiring effects
- 7 Digital interfaces
- 7.1 I2C serial interface
- 7.1.1 I2C operation
Datasheet sections
- 10 Package information
- 11 Revision history
Features
■ Analog supply voltage: 2.5 V to 3.3 V ■ Digital supply voltage IOs: 1.8 V ■ Power-down mode ■ 3 magnetic field channels and 3 acceleration channels ■ ±1.3 to ±8,1 gauss magnetic field full-scale ■ ±2 g/±4 g/±8 g dynamically selectable full- scale ■ 16-bit data out ■ I2C serial interface ■ 2 independent programmable interrupt generators for free-fall and motion detection ■ Embedded self-test ■ Accelerometer sleep-to-wakeup function ■ 6D orientation detection ■ ECOPACK® RoHS and “Green” compliant (see Section 10)
Applications
■ Compensated compassing ■ Map rotation ■ Position detection ■ Motion-activated functions ■ Free-fall detection ■ Intelligent power-saving for handheld devices ■ Display orientation ■ Gaming and virtual reality input devices ■ Impact recognition and logging ■ Vibration monitoring and compensation
Description
The LSM303DLH is a system-in-package featuring a 3D digital linear acceleration sensor and a 3D digital magnetic sensor. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are realized using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM303DLH has a linear acceleration full-scale of ±2 g / ±4 g / ±8 g and a magnetic field full-scale gauss, both fully selectable by the user. The LSM303DLH includes an I 2C serial bus interface that supports standard mode (100 kHz) and fast mode (400 kHz). The internal self-test capability allows the user to check the functioning of the whole module in the final application. The system can be configured to generate an interrupt signal by inertial wakeup/free-fall events, as well as by the position of the device itself. Thresholds and timing of interrupt generators are programmable on the fly by the end user. Magnetic and accelerometer parts can be enabled or put in power-down mode separately. The LSM303DLH is available in a plastic land grid array (LGA) package, and is guaranteed to operate over an extended temperature range from -30 to +85 °C. Table 1. Device summary
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connection
Table 2. Pin description
1 Reserved Connect to GND
2 GND 0 V supply
3 Reserved Connect to GND
4 SA0_A Linear acceleration signal I
5 Reserved To be connected to Vdd I 2C bus
7 Reserved Connect to Vdd
8 NC Not connected
9 NC Not connected
10 Reserved Leave unconnected
11 Reserved Leave unconnected
12 SET2 S/R capacitor connection (C2)
13 Reserved Leave unconnected
14 Reserved Leave unconnected
15 C1 Reserved capacitor connection (C1)
16 SET1 S/R capacitor connection (C2)
17 Reserved Connect to GND
18 DRDY_M Magnetic signal interface data ready - test point
19 SDA_M Magnetic signal interface I
20 SCL_M Magnetic signal interface I 2C serial clock (SCL)
21 Vdd_dig_M Magnetic sensor digital power supply
22 Vdd_IO_A Linear acceleration signal interface power supply for I/O pins
23 Reserved Connect to Vdd_IO_A
24 SCL_A Linear acceleration signal interface I
25 SDA_A Linear acceleration signal interface I 2C serial data (SDA)
26 INT1 Inertial interrupt 1
27 INT2 Inertial interrupt 2
28 Reserved Connect to GND
2 Module specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics
- Typical specificat ions are not guaranteed
- Verified by wafer level test and measur ement of initial offset and sensitivity
- Typical zero- g level offset value after MSL3 preconditioning
- Offset can be eliminated by enabl ing the built-in high-pass filter
- The sign of “Self-test output change” is defined by the CTRL_REG4 STsign bit (Table 29), for all axes.
- Self-test output changes with the power supply. “Self-test output change” is defined as
- Output data reach 99% of final value after 1/ODR+1ms when enabling self-test mode, due to device filtering
Table 3. Mechanical characteristics (continued)
2.2 Electrical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted. Table 4. Electrical characteristics
- Typical specificat ions are not guaranteed.
- Magnetic sensor setting ODR = 7.5 Hz. Accelerometer sensor ODR = 50 Hz.
2.3 Communication interface characteristics
2.3.1 Accelerometer sensor I 2C - inter IC control interface
Subject to general operating conditions for Vdd and top. Figure 3. I 2C slave timing diagram (b) Table 5. I 2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production.
- Cb = total capacitance of one bus line, in pF.
b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port.
LSM303DLH Module specifications Doc ID 16941 Rev 1 15/47
2.3.2 Magnetic field sensing I 2C digital interface
This magnetic sensor IC has a 7-bit serial address and supports I2C protocols with standard and fast modes (100 kHz and 400 kHz, respectively), but does not support high-speed mode (Hs). External pull-up resistors are required to support the standard and fast modes. Depending on the application, the internal pull-ups may be used to support slower data speeds than specified by I 2C standards. This device does not contain 50 ns spike suppression, as required by fast mode operation in the I2C bus specification. Activities required by the master (register read and write) have priority over internal activities, such as measurement. The purpose of this priority is to prevent the master waiting and the I 2C bus being engaged for longer than necessary.
3 Absolute maximum ratings
Table 6. Absolute maximum ratings
4 Terminology
4.1 Linear acceleration sensitivity
Linear acceleration sensitivity describes the gain of the accelerometer sensor and can be determined e.g. by applying 1 g acceleration to it. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, a ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors.
4.2 Zero- g level
Zero-g level Offset (LA_TyOff) describes the deviation of an actual output signal from the ideal output signal if no linear acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X and Y axes, whereas the Z axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature; see “Linear acceleration zero-g level change vs temperature” (LA_TCOff) in Table 3. The Zero-g level tolerance (TyOff) describes the standard deviation of the range of Zero-g levels of a group of sensors.
4.3 Sleep-to-wakeup
The “sleep-to-wakeup” function, in conjunction with low-power mode, allows further reduction of system power consumption and the development of new smart applications. The LSM303DLH may be set to a low-power operating mode, characterized by lower date rate refreshing. In this way the device, even if sleeping, continues sensing acceleration and generating interrupt requests. When the sleep-to-wakeup function is activated, the LSM303DLH is able to automatically wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. With this feature the system may be efficiently switched from low-power mode to full-performance depending on user-selectable positioning and acceleration events, thus ensuring power-saving and flexibility.
5 Functionality
The LSM303DLH is a system-in-package featuring a 3D digital linear acceleration and 3D digital magnetic field detection sensor. The system includes specific sensing elements and an IC interfaces capable of measuring both the linear acceleration and magnetic field applied to it, and to provide a signal to the external world through an I 2C serial interface with separated digital ouput. The sensing system is manufactured using specialized micromachining processes, while the IC interfaces are realized using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM303DLH features two data-ready signals (RDY) which indicate when a new set of measured acceleration data and magnetic data are available, thus simplifying data synchronization in the digital system that uses the device. The LSM303DLH may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. Both free-fall and wakeup can be used simultaneously on two different accelerometer interrupts.
5.1 Factory calibration
The IC interface is factory calibrated for linear acceleration sensitivity (LA_So), and linear acceleration Zero-g level (LA_TyOff). The trimming values are stored inside the device in non-volatile memory. When the device is turned on, the trimming parameters are downloaded into the registers to be used during normal operation. This allows the use of the device without further calibration.
5.2 Linear acceleratio n self-test operation
Self-test allows the checking of sensor functionality without moving it. The self-test function is off when the self-test bit (ST) of CTRL_REG4_A (control register 4) is programmed to ‘0‘. When the self-test bit of CTRL_REG4_A is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full-scale through the device sensitivity. When self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
5.3 Magnetic self-test operation
To check the magnetic sensor for proper operation, a self-test feature is incorporated in which the sensor offset straps are excited to create a nominal field strength (bias field) to be measured. To implement this self-test, the least significant bits (MS1 and MS0) of configuration register A are changed from 00 to 01 (0x12 or 0b000xxx01).
cycles are made on each magnetic vector. The first acquisition is a set pulse followed shortly by measurement data of the external field. Table 7. Magnetic ST (positive bias)
- Typical specificat ions are not guaranteed
6 Application hints
Figure 4. LSM303DLH electrical connection 1 - recommended for I 2C fast mode Figure 5. LSM303DLH electrical connection 2
6.1 External capacitors
The C1 and C2 external capacitors should have a low SR value ceramic type construction. nominally 0.22 µF in capacitance. present at the same time to obtain proper behavior of the IC (refer to Figure 4). completely programmed by the user through the I2C interface.
6.2 Pull-up resistors
Pull-up resistors are placed on the two I2C bus lines.
6.3 Digital interface power supply
standard power supply (Vdd) or using a dedicated power supply (Vdd_IO_A). The table below shows the modes available in the various power supply conditions.
6.4 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “pin 1 Indicator” unconnected during soldering. Table 8. Operational mode and power supply for magnetic field sensing from Vdd_dig_M supply, including all onboard clocks. Device measurement functionality not supported. Device I2C bus and register access supported.
6.5 High current wiring effects
High current in wiring and printed circuit traces can be the cause of errors in magnetic field measurements for compassing. Conducto-generated magnetic fields add to earth’s magnetic field, creating errors in compass heading computation. Keep currents that are higher than 10 mA a few millimeters further away from the sensor IC.
7 Digital interfaces
serial interfaces: one for the accelerometer core and the other for the magnetometer core. The two interfaces can be connected together on the PCB.
7.1 I 2C serial interface
whose content can also be read back. The relevant I2C terminology is given in the table below. Table 9. Serial interface pin description Table 10. Serial interface pin description
7.1.1 I 2C operation
7 LSb represent the actual register address while the MSB enables address auto-increment. allow multiple data read/write. terminated by the generation of a STOP (SP) condition. Table 11. Transfer when master is writing one byte to slave Table 12. Transfer when master is writing multiple bytes to slave Table 13. Transfer when master is receiving (reading) one byte of data from slave
7.1.2 Linear accelera tion digital interface
the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 14. SAD+Read/Write patterns address of the first register to be read. binary data returned. Negative binary values will be in two’s complement form. (0x3C) for write operations, or 00111101b (0x3D) for read operations. recommended with a nominal 1.8 V digital supply voltage (Vdd_dig_M). Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
a 9th clock pulse, and releases the SDA_M line. terminated with the master issuing a stop sequence. perform these tasks in code. succeed the 7-bit address plus 1 bit read/write identifier. LSM303DLH, the address pointer is updated automatically without master intervention.
- if address pointer = 09, then address pointer = 03
- while if address pointer >12, then address pointer = 0
- while address pointer = address pointer + 1
- the address pointer value itself cannot be read via the I2C bus. Any attempt to read an invalid address location returns 0’s, and any write to an invalid address location or an undefined bit within a valid address location is ignored by this device.
Table 16. SAD+Read/Write patterns
8 Register mapping
Table 17. Register address map
permanent damage to the device. Table 17. Register address map (continued)
9 Registers description
write the data through the serial interface.
9.1 Linear acceleration register
For linear acceleration sensors, the default (factory) 7-bit slave address is 001100xb.
9.1.1 CTRL_REG1_A (20h)
are produced. In low-power mode they define the output data resolution. the possible configurations for the DR1 and DR0 bits. Table 18. CTRL_REG1_A register Table 19. CTRL_REG1_A description Table 20. Power mode and low-power output data rate configurations
9.1.2 CTRL_REG2_A (21h)
Table 21. Normal-mode output data rate configurations and low-pass cut-off Table 20. Power mode and low-power output data rate configurations (continued) Table 22. CTRL_REG2_A register Table 23. CTRL_REG2_A description
BOOT bit is again set to ‘0’.
9.1.3 CTRL_REG3_A (22h)
Table 24. High-pass filter mode configuration Table 25. High-pass filter cut-off frequency configuration Table 26. CTRL_REG3_A register
9.1.4 CTRL_REG4_A (23h)
Table 27. CTRL_REG3_A description PP_OD Push-pull/open drain selection on interrupt pad. Default value 0. reading INT2_SRC itself. Default value: 0. Data signal on INT 2 pad control bits. Default value: 00. reading INT1_SRC register. Default value: 0. Data signal on INT 1 pad control bits. Default value: 00. Table 28. Data signal on INT 1 and INT 2 pad Table 29. CTRL_REG4_A register Table 30. CTRL_REG4_A description BLE Big/little endian data selection. Default value 0. FS1, FS0 Full-scale selection. Default value: 00. STsign Self-test sign. Default value: 00. ST Self-test enable. Default value: 0.
also. This feature avoids reading LSB and MSB related to different samples.
9.1.5 CTRL_REG5_A (24h)
TurnOn bits are used for turning on the sleep-to-wake function. is not automatically changed to “normal mode” configuration.
9.1.6 HP_FILTER_RESET_A (25h)
g. This makes it possible to surmount the settling time of the high-pass filter.
9.1.7 REFERENCE_A (26h)
Table 31. CTRL_REG5_A register
000000 T u r n O n 1 T u r n O n 0
Table 32. CTRL_REG5_A description Tur nOn0 Turn-on mode selection for sleep-to-wake function. Default value: 00. Table 33. Sleep-to-wake configuration
11 Turned on: The device is in low-power mode
Table 34. REFERENCE_A register Table 35. REFERENCE_A description Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.
This register sets the acceleration value taken as a reference for the high-pass filter output. bits are set to “01”, filter out is generated taking this value as a reference.
9.1.8 STATUS_REG_A(27h)
9.1.9 OUT_X_L_A (28h ), OUT_X_H_A (29h)
X-axis acceleration data. The value is expressed as two’s complement.
9.1.10 OUT_Y_L_A (2Ah ), OUT_Y_H_A (2Bh)
Y -axis acceleration data. The value is expressed as two’s complement.
9.1.11 OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh)
Z-axis acceleration data. The value is expressed as two’s complement. Table 36. STATUS_REG_A register Table 37. STATUS_REG_A description
9.1.12 INT1_CFG_A (30h)
Configuration register for Interrupt 1 source. Table 38. INT1_CFG_A register Table 39. INT1_CFG_A description AOI AND/OR combination of interrupt events. Default value: 0. 6D 6 direction detection function enable. Default value: 0. Table 40. Interrupt 1 source configurations
9.1.13 INT1_SRC_A (31h)
Interrupt 1 source register. Read-only register.
9.1.14 INT1_THS_A (32h)
9.1.15 INT1_DURATION_A (33h)
Table 41. INT1_SRC register
0 I A Z HZ LY HY LX HX L
Table 42. INT1_SRC_A description Table 43. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 44. INT1_THS description Table 45. INT1_DURATION_A register
0 D 6D 5D 4D 3D 2D 1D 0
Table 46. INT2_DURATION_A description
The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen.
9.1.16 INT2_CFG_A (34h)
Configuration register for Interrupt 2 source. Table 47. INT2_CFG_A register Table 48. INT2_CFG_A description AOI AND/OR combination of interrupt events. Default value: 0. 6D 6 direction detection function enable. Default value: 0. Table 49. Interrupt mode configuration
9.1.17 INT2_SRC_A (35h)
Interrupt 2 source register. Read-only register.
9.1.18 INT2_THS_A (36h)
9.1.19 INT2_DURATION_A (37h)
Table 50. INT2_SRC_A register Table 51. INT2_SRC_A description Table 52. INT2_THS register Table 53. INT2_THS description Table 54. INT2_DURATION_A register Table 55. INT2_DURATION_A description
The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen.
9.2 Magnetic field sensing register description
identify them and to read/write the data through the serial interface. (0x3C) for write operations, or 00111101b (0x3D) for read operations.
9.2.1 CRA_REG_M (00h)
stream. The number in parentheses indicates the default value of that bit. Table 56. CRA_REG_M register Table 57. CRA_REG_M description CRA7 to CRA5 These bits must be cleared for correct operation. Table 58. CRA_REG M description
9.2.2 CRB_REG_M (01h)
9.2.3 MR_REG_M (02h)
Table 59. CRA_REG_M description configuration the device follows normal measurement flow. 0 1 Positive bias configuration. 1 0 Negative bias configuration. Table 60. CRA_REG register Table 61. CRA_REG description Table 62. Gain setting
9.2.4 OUT_X_M (03-04h)
register L. These registers store the measurement result from channel X. register L contains the LSB from the measurement result. locations, with DXRH and DXRL denoting the bits that are in the data output X registers. DXRH7 and DXRL7 denote the first bit of the data stream. 2’s complement form. This register value clears after the next valid measurement is made. The content of this register is the MSB magnetic field data for X-axis. Table 63. MR_REG
000000 M D 1 M D 0
Table 64. MR_REG description MR1 to MR0 Mode select bits. These bits se lect the operation mode of this device. Table 65. Magnetic sensor operating mode available at a frequency of fDO, where fDO is the frequency of data output. high and returns to sleep mode. Mode register returns to sleep mode bit values. until the data output register is read or another conversion is performed. Table 66. OUTXH_M register
The content of this register is the LSB magnetic field data for X-axis.
9.2.5 OUT_Y_M (05-06h)
register L. These registers store the measurement result from channel Y . register L contains the LSB from the measurement result. The content of this register is the MSB magnetic field data for Y -axis. The content of this register is the LSB magnetic field data for Y -axis.
9.2.6 OUT_Z_M (07-08h)
register L. These registers store the measurement result from channel Z. register L contains the LSB from the measurement result. The content of this register is the MSB magnetic field data for Z-axis. The content of this register is the LSB magnetic field data for Z-axis.
9.2.7 SR_REG_M (09h)
Table 67. OUTXL_M register Table 68. OUT_YH_M register Table 69. OUT_YL_M register Table 70. OUTZH_M register Table 71. OUTZL_M register
status register. SR7 denotes the first bit of the data stream.
9.2.8 IR_REG_M (0Ah/0Bh/0Ch)
locations, with IRA/IRB/IRC denoting the bits that are in the identification registers A, B & C. IRA7/IRB7/IRC7 denotes the first bit of the data stream. The identification value for this device is stored in this register. This is a read-only register. Table 72. SR register
00000 R E N L O C R D Y
Table 73. Status register bit designations enabled. This bit is cleared when the internal regulator is disabled. four, the measurement is changed. Table 74. IRA_REG_M Table 75. IRB_REG_M
Table 76. IRC_REG_M
specifications, grade definitions and product status are available at: www.st.com. Figure 6. LGA-28: mechanical data and package dimensions
Table 77. Document revision history