LSM303AGR STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 68
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Module specifications
- 2.1 Sensor characteristics
- 2.2 Temperature sensor characteristics
- 2.3 Electrical characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 I 2C - inter-IC control interface
- 2.5 Absolute maximum ratings
- 3 Terminology
- 3.1 Sensitivity
- 3.1.1 Linear acceleration sensor sensitivity
- 3.1.2 Magnetic sensor sensitivity
- 3.2 Zero-g level
- 3.3 Zero-gauss level
- 3.4 Magnetic dynamic range
- 4 Functionality
- 4.1 Magnetometer
- 4.1.1 Magnetometer power modes
- 4.1.2 Magnetometer offset cancellation
- 4.1.3 Magnetometer interrupt
- 4.1.4 Magnetometer hard-iron compensation
- 4.1.5 Magnetometer self-test
- 4.2 Accelerometer
- 4.2.1 Accelerometer power modes
- 4.2.2 Accelerometer 6D / 4D orientation detection
- 4.2.3 Accelerometer activity/inactivity function
- 4.2.4 Accelerometer self-test
Datasheet sections
- 8.10 CTRL_REG5_A (24h)
- 8.11 CTRL_REG6_A (25h)
- 8.12 REFERENCE/DATACAPTURE_A (26h)
- 8.13 STATUS_REG_A (27h)
- 8.14 OUT_X_L_A (28h), OUT_X_H_A (29h)
- 8.15 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh)
- 8.16 OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh)
- 8.17 FIFO_CTRL_REG_A (2Eh)
- 8.18 FIFO_SRC_REG_A (2Fh)
- 8.19 INT1_CFG_A (30h)
- 8.20 INT1_SRC_A (31h)
- 8.21 INT1_THS_A (32h)
- 8.22 INT1_DURATION_A (33h)
- 8.23 INT2_CFG_A (34h)
- 8.24 INT2_SRC_A (35h)
- 8.25 INT2_THS_A (36h)
- 8.26 INT2_DURATION_A (37h)
- 8.27 CLICK_CFG_A (38h)
- 8.28 CLICK_SRC_A (39h)
- 8.29 CLICK_THS_A (3Ah)
- 8.30 TIME_LIMIT_A (3Bh)
- 8.31 TIME_LATENCY_A (3Ch)
- 8.32 TIME_WINDOW_A (3Dh)
- 8.33 Act_THS_A (3Eh)
- 8.34 Act_DUR_A (3Fh)
- 8.35 OFFSET_X_REG_L_M (45h) and OFFSET_X_REG_H_M (46h)
- 8.36 OFFSET_Y_REG_L_M (47h) and OFFSET_Y_REG_H_M (48h)
- 8.37 OFFSET_Z_REG_L_M (49h) and OFFSET_Z_REG_H_M (4Ah)
- 8.38 WHO_AM_I_M (4Fh)
- 8.39 CFG_REG_A_M (60h)
- 8.40 CFG_REG_B_M (61h)
- 8.41 CFG_REG_C_M (62h)
- 8.42 INT_CTRL_REG_M (63h)
Features
3 magnetic field channels and 3 acceleration channels ±50 gauss magnetic dynamic range ±2/±4/±8/16 g selectable acceleration full scales 16-bit data output SPI / I2C serial interfaces Analog supply voltage 1.71 V to 3.6 V Power-down mode / low-power mode Programmable interrupt generators for free- fall, motion detection and magnetic field detection Embedded self test Embedded temperature sensor Embedded FIFO ECOPACK ®, RoHS and “Green” compliant
Applications
Tilt-compensated compasses Map rotation Position detection Motion-activated functions Free-fall detection Click/double-click recognition Pedometers Intelligent power saving for handheld devices Display orientation Gaming and virtual reality input devices Impact recognition and logging Vibration monitoring and compensation
Description
The LSM303AGR is an ultra-low-power high- performance system-in-package featuring a 3D digital linear acceleration sensor and a 3D digital magnetic sensor. The LSM303AGR has linear acceleration full scales of ±2g/±4g/±8g/16g and a magnetic field dynamic range of ±50 gauss. The LSM303AGR includes an I 2C serial bus interface that supports standard, fast mode, fast mode plus, and high-speed (100 kHz, 400 kHz, 1 MHz, and 3.4 MHz) and an SPI serial standard interface. The system can be configured to generate an interrupt signal for free-fall, motion detection and magnetic field detection. The magnetic and accelerometer blocks can be enabled or put into power-down mode separately. The LSM303AGR is available in a plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. /*$ [[PP Table 1. Device summary
Table 18. I
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections
Table 2. Pin description
1 SCL
2 CS_XL
3 CS_MAG
5 C1 Capacitor connection (C1 = 220 nF)
6 GND Connected to GND
7 INT_MAG/DRDY Magnetometer interrupt/data-ready signal
8 GND 0 V
9 Vdd Power supply
10 Vdd_IO Power supply for I/O pins
11 INT_2_XL Accelerometer interrupt 2
12 INT_1_XL Accelerometer interrupt 1
2 Module specifications
2.1 Sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted(a). Table 3. Sensor characteristics LA_TCOff Zero-g level change vs.
- Typical specifications are not guaranteed.
- Verified by wafer level test and measurement of initial offset and sensitivity.
- Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited
number of samples, not measured during final test for production.
- Typical zero- g level offset value after MSL3 preconditioning.
- Offset can be eliminated by enabling the built-in high-pass filter.
- With low-pass filter or offset cancellation enabled.
- The sign of “Self-test output change” is defined by the ST bit in CTRL_REG4_A (23h), for all axes.
OUTPUT[LSb](Self-test enabled) - OUTPUT[LSb](Self-test disabled). 1LSb=4mg at 10bit representation, ±2 g full scale.
- After enabling the ST bit, correct data is obtained after two samples (low-power mode / normal mode) or after eight samples
- Magnetic “self-test” is defined as: OUTPUT[gauss](Self-test enabled) - OUTPUT[gauss](Self-test disabled).
Table 3. Sensor characteristics (continued)
2.2 Temperature sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted (b).
2.3 Electrical characteristics
Table 4. Temperature sensor characteristics
- Typical specifications are not guaranteed.
Table 5. Electrical characteristics
50 Hz ODR in
Accelerometer in power-down mode. Accelerometer in power-down mode.
- Typical specifications are not guaranteed.
- It is possible to remove Vdd maintaining Vdd_IO without blocking the communication bus, in this condition the
measurement chain is powered off.
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram characterization results, not tested in production. Table 6. SPI slave timing values
2.4.2 I 2C - inter-IC control interface
Subject to general operating conditions for Vdd and Top. Table 7. I2C slave timing values (standard and fast mode)
- Data based on standard I 2C protocol requirement, not tested in production.
Table 8. I2C slave timing values (fast mode plus and high speed)
- Data based on standard I 2C protocol requirement, not tested in production.
Figure 4. I2C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
2.5 Absolute maximum ratings
Table 9. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
3 Terminology
3.1 Sensitivity
3.1.1 Linear acceleration sensor sensitivity
Sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
3.1.2 Magnetic sensor sensitivity
Sensitivity describes the ratio of the output digital data expressed in LSB units and the applied magnetic field expressed in mG (milligauss). It can be measured, for example, by applying a known magnetic field along one axis and measuring the digital output of the device.
3.2 Zero- g level
The zero-g level offset (LA_TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on the X-axis and 0 g on the Y-axis whereas the Z-axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little with temperature, see Table 3 “Zero-g level change vs. temperature” (LA_TCOff). The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a population of sensors.
3.3 Zero- gauss level
Zero-gauss level offset (M_TyOff) describes the deviation of an actual output signal from the ideal output if no magnetic field is present.
3.4 Magnetic dynamic range
The magnetic dynamic range is defined as the magnetic field driven along one sensitive axis, giving the maximum digital output value.
4 Functionality
4.1 Magnetometer
4.1.1 Magnetometer power modes
improved without any increase in power consumption. Magnetometer offset cancellation). Table 10. Digital low-pass filter Table 11. Current consumption of operating modes Table 12. Operating mode and turn-on time
4.1.2 Magnetometer offset cancellation
The offset cancellation is the result of performing a set and reset in the magnetic sensor. The offset cancellation technique is defined as follows: where Hn and Hn-1 are two consecutive magnetic field measurements, one after a set pulse, the other after a reset pulse. Considering a magnetic offset (Hoff), the two magnetic field measurements are: Set: Hn = H + Hoff Reset: Hn-1 = –H + Hoff The offset is cancelled according the offset cancellation technique: In the LSM303AGR the offset cancellation is enabled by setting the bit OFF_CANC = 1 in CFG_REG_B_M (61h). If the offset cancellation is disabled, a set of the magnetic sensor is performed anyway. The set pulse frequency can be configured by setting the Set_FREQ bit in CFG_REG_B_M (61h).
4.1.3 Magnetometer interrupt
In the LSM303AGR the magnetometer interrupt signal generation is based on the comparison between data and a programmable threshold. To enable the interrupt function, in INT_CTRL_REG_M register (63h) the "IEN" bit must be set to '1'. In the LSM303AGR the user can select the axis/axes in which the interrupt function can be enabled. In order to do this, the XIEN, YIEN, and ZIEN bits in INT_CTRL_REG_M (63h) need be set properly. The threshold value can be programmed by setting the INT_THS_L_REG_M (65h) and INT_THS_H_REG_M (66h) registers. The threshold is expressed in absolute value as a 15-bit unsigned number. The threshold has the same sensitivity as the magnetic data. When magnetic data exceeds the positive or the negative threshold, the interrupt signal is generated and the information about the type of interrupt is stored in the INT_SOURCE_REG_M (64h) register. In particular, when magnetic data exceeds the positive threshold the P_TH_S_axis bit is set to '1', while if data exceeds the negative threshold the N_TH_S_axis bit is set to '1'. If magnetic data lay between the positive and the negative thresholds, no interrupt signal is released. Hout Hn Hn1–– Hout Hn Hn1––
Figure 5. Interrupt function the advanced approach is selected. kind of interrupt is selected by setting the IEL bit in INT_CTRL_REG_M (63h) to '0'. bit in INT_CTRL_REG_M (63h) to '1'. The interrupt signal polarity can be set using the IEA bit in INT_CTRL_REG_M (63h). CFG_REG_C_M (62h) must be set to '1'.
4.1.4 Magnetometer hard-iron compensation
Hard-iron distortion occurs when a magnetic object is placed near the magnetometer and appears as a permanent bias in the sensor’s outputs. The hard-iron correction consists of compensating magnetic data from hard-iron distortion. The operation is defined as follows: H out = Hread – HHI where: Hread is the generic uncompensated magnetic field data, as read by the sensor; HHI is the hard-iron distortion field; Hout is the compensated magnetic data. The computation of the hard-iron distortion field should be performed by an external processor. After the computation of the hard iron-distortion field has been performed, the measured magnetic data can be compensated. The LSM303AGR offers the possibility of storing hard-iron data inside six dedicated registers from 45h to 4Ah. Each register contains eight bits so that the hard-iron data can be expressed as a 16-bit two’s complement number. The OFFSET_axis_REG_H registers contain the MSBs of the hard-iron data, while the OFFSET_axis_REG_L registers contain the LSBs. Hard-iron data have the same format and weight of the magnetic output data. The hard-iron values stored in dedicated registers are automatically subtracted from the output data.
4.1.5 Magnetometer self-test
The self-test function is available for the magnetic sensor. When the magnetic self-test is enabled, a current is forced into a coil inside the device. This current will generate a magnetic field that will produce a variation of the magnetometer output signals. If the output signals change within the amplitude limits specified in Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications. The self-test procedure is described in the following figure.
Figure 6. Magnetometer self-test procedure
4.2 Accelerometer
4.2.1 Accelerometer power modes
modes: high-resolution mode, normal mode and low-power mode. The table below summarizes how to select the different operating modes. The turn-on time to transition to another operating mode is given in Table 14. Table 13. Operating mode selection Table 14. Turn-on time for operating mode transition Table 15. Current consumption of operating modes
4.2.2 Accelerometer 6D / 4D orientation detection
direction. In 4D configuration, detection of the position of the Z-axis is disabled.
4.2.3 Accelerometer activity/inactivity function
accelerometer block of the device. been detected, increasing the output data rate and bandwidth. ensuring power saving and flexibility. Act_THS_A (3Eh) register. The high-pass filter is automatically enabled. Table 16. Activity/Inactivity function control registers (20h)(ODR [3:0]) bits are left untouched. CTRL_REG1_A (20h) is restored immediately (Activity). by setting the CTRL_REG6_A (25h) (P2_ACT) bit to ‘1’. Table 15. Current consumption of operating modes (continued)
4.2.4 Accelerometer self-test
The self-test allows the user to check the sensor functionality without moving it. When the self-test is enabled, an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications. The self-test procedure is described in the following figure.
Figure 7. Accelerometer self-test procedure
4.3 IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an analog-to-digital converter. The acceleration and magnetic data may be accessed through an I 2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LSM303AGR features a data-ready signal which indicates when new sets of measured acceleration and magnetic data are available, thus simplifying data synchronization in the digital system that uses the device.
4.4 FIFO
The FIFO buffer applies only to the accelerometer. The LSM303AGR embeds a 32-level FIFO for each of the three output channels, X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. In order to enable the FIFO buffer, the FIFO_EN bit in CTRL_REG5_A (24h) must be set to ‘1’. This buffer can work according to the following different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FM [1:0] bits in FIFO_CTRL_REG_A (2Eh). Programmable FIFO watermark level, FIFO empty or FIFO overrun events can be enabled to generate dedicated interrupts on the INT_1_XL pin (configuration through CTRL_REG3_A (22h)). In the FIFO_SRC_REG_A (2Fh) register the EMPTY bit is equal to ‘1’ when all FIFO samples are ready and FIFO is empty. In the FIFO_SRC_REG_A (2Fh) register the WTM bit goes to ‘1’ if new data is written in the buffer and FIFO_SRC_REG_A (2Fh) (FSS [4:0]) is greater than or equal to FIFO_CTRL_REG_A (2Eh) (FTH [4:0]). FIFO_SRC_REG_A (2Fh) (WTM) goes to ‘0’ if reading an X, Y, Z data slot from FIFO and FIFO_SRC_REG_A (2Fh) (FSS [4:0]) is less than or equal to FIFO_CTRL_REG_A (2Eh) (FTH [4:0]). In the FIFO_SRC_REG_A (2Fh) register the OVRN_FIFO bit is equal to ‘1’ if the FIFO slot is overwritten.
4.4.1 Bypass mode
In Bypass mode the FIFO is not operational and for this reason it remains empty. For each channel only the first address is used. The remaining FIFO levels are empty. Bypass mode must be used in order to reset the FIFO buffer when a different mode is operating (i.e. FIFO mode).
4.4.2 FIFO mode
In FIFO mode, the buffer continues filling data from the X, Y and Z accelerometer channels until it is full (a set of 32 samples stored). When the FIFO is full, it stops collecting data from the input channels and the FIFO content remains unchanged.
After the last read it is necessary to exit Bypass mode in order to reset the FIFO content. mode configuration (FM[1:0] bits) in register FIFO_CTRL_REG_A (2Eh).
4.4.3 Stream mode
continue to be overwritten until a read operation frees the FIFO slots. FIFO and leave memory slots free for incoming data. Figure 8. Stream mode
4.4.4 Stream-to-FIFO mode
mode and switches to FIFO mode when the selected interrupt occurs.
When an interrupt event is configured on the INT_1_XL pin, the FIFO operates in Stream mode if the INT_1_XL pin value is equal to ‘0’ and it operates in FIFO mode if the INT_1_XL pin value is equal to ‘1’. Switching modes is dynamically performed according to the INT_1_XL pin value. Stream-to-FIFO can be used in order to analyze the sampling history that generates an interrupt. The standard operation is to read the contents of FIFO when the FIFO mode is triggered and the FIFO buffer is full and stopped.
4.4.5 Retrieving data from FIFO
FIFO data is read from the OUT_X_L_A (28h), OUT_X_H_A (29h), OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh), and OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) registers. A read operation using a serial interface of the OUT_X_L_A (28h), OUT_X_H_A (29h), OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) or OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) output registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X_L_A (28h), OUT_X_H_A (29h), OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) and OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) registers and both single read and read_burst operations can be used.
4.4.6 FIFO multiple read (burst)
the system automatically restarts from Addr 28h. Figure 9. FIFO multiple read
4.5 Temperature sensor
enabled by setting the TEMP_EN[1:0] bits to ‘1’ in the TEMP_CFG_REG_A (1Fh) register. Both the OUT_TEMP_L_A (0Ch), OUT_TEMP_H_A (0Dh) registers must be read.
4.6 Factory calibration
and Zero-gauss level (M_TyOff). operation. This allows using the device without further calibration.
5 Application hints
Figure 10. LSM303AGR electrical connections be placed as near as possible to pin 9 of the device (common design practice). in this condition the measurement chain is powered off. due to the length of the copper strips. 2C or SPI interfaces. When using the I2C, CS must be tied high (i.e. and INT_MAG) can be completely programmed by the user through the I2C/SPI interface.
5.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standards. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering.
5.2 High-current wiring effects
High current in wiring and printed circuit traces can be culprits in causing errors in magnetic field measurements for compassing. Conductor-generated magnetic fields will add to the Earth’s magnetic field, leading to errors in compass heading computation. Keep currents higher than 10 mA a few millimeters away from the sensor IC.
6 Digital interfaces
CS line must be tied high (i.e. connected to Vdd_IO).
6.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. up resistor. When the bus is free, both the lines are high. Table 17. Serial interface pin description Table 18. I2C terminology
6.1.1 I 2C operation
7 LSb represent the actual register address while the MSB enables address auto increment. allow multiple data read/writes. SAD+read/write bit pattern is composed, listing all the possible configurations. Table 19. Transfer when master is writing one byte to slave Table 20. Transfer when master is writing multiple bytes to slave Table 21. Transfer when master is receiving (reading) one byte of data from slave Table 22. Transfer when master is receiving (reading) multiple bytes of data from slave
terminated by the generation of a STOP (SP) condition. Table 23. SAD + Read/Write patterns Magnetic field sensor: the default (factory setting) 7-bit slave address is 0011110b. Table 24. SAD + Read/Write patterns
6.2 SPI bus interface
6.2.1 Accelerometer SPI write
Figure 11. Accelerometer SPI write protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 2-7: address AD(5:0). This is the address field of the indexed register. Figure 12. Accelerometer multiple byte SPI write protocol (2-byte example)
6.2.2 Accelerometer SPI read in 3-wire mode
(SPI serial interface read enable). Figure 13. Accelerometer SPI read protocol in 3-wire mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode.
6.2.3 Magnetometer SPI write
Figure 14. Magnetometer SPI write protocol command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1-7: address AD(6:0). This is the address field of the indexed register.
Figure 15. Magnetometer multiple byte SPI write protocol (2-byte example)
6.2.4 Magnetometer SPI read
Figure 16. Magnetometer SPI read protocol bit 0: WRITE bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is available in 3-wire mode.
7 Register mapping
while registers 40h through 6Fh are dedicated to the magnetometer. Table 25. Register address map
Table 25. Register address map (continued)
permanent damage to the device.
- R = read-only register, R/W = readable/writable register
8 Register description
8.1 STATUS_REG_AUX_A (07h)
8.2 OUT_TEMP_L_A (0Ch), OUT_TEMP_H_A (0Dh)
enable and read the temperature sensor output data.
8.3 INT_COUNTER_REG_A (0Eh)
8.4 WHO_AM_I_A (0Fh)
Device identification register.
8.5 TEMP_CFG_REG_A (1Fh)
Table 26. STATUS_REG_AUX register Table 27. STATUS_REG_AUX description Table 28. INT_COUNTER_REG register Table 29. WHO_AM_I register Table 30. TEMP_CFG_REG register Table 31. TEMP_CFG_REG description
8.6 CTRL_REG1_A (20h)
the frequency of each combination of ODR[3:0].
8.7 CTRL_REG2_A (21h)
Table 32. CTRL_REG1 register Table 33. CTRL_REG1 description Table 34. Data rate configuration Table 35. CTRL_REG2 register
8.8 CTRL_REG3_A (22h)
Table 36. CTRL_REG2 description HPCLICK High-pass filter enable for CLICK function. HPIS2 High-pass filter enable for AOI function on Interrupt 2. HPIS1 High-pass filter enable for AOI function on Interrupt 1. Table 37. High-pass filter mode configuration Table 38. CTRL_REG3 register Table 39. CTRL_REG3 description I1_CLICK CLICK interrupt on INT1 pin. Default value 0. I1_AOI1 AOI1 interrupt on INT1 pin. Default value 0. I1_AOI2 AOI2 interrupt on INT1 pin. Default value 0. I1_DRDY1 DRDY1 interrupt on INT1 pin. Default value 0. I1_DRDY2 DRDY2 interrupt on INT1 pin. Default value 0. I1_WTM FIFO watermark interrupt on INT1 pin. Default value 0. I1_OVERRUN FIFO overrun interrupt on INT1 pin. Default value 0.
8.9 CTRL_REG4_A (23h)
8.10 CTRL_REG5_A (24h)
Table 40. CTRL_REG4 register
- The BLE function can be activated only in high-resolution mode
Table 41. CTRL_REG4 description Table 42. Self-test mode configuration Table 43. CTRL_REG5_A register
8.11 CTRL_REG6_A (25h)
8.12 REFERENCE/DATACAPTURE_A (26h)
Table 44. CTRL_REG5_A description cleared by reading INT1_SRC_A (31h) itself. Default value: 0. register cleared by reading INT2_SRC_A (35h) itself. Default value: 0. Table 45. CTRL_REG6_A register Table 46. CTRL_REG6_A description P2_ACT Activity interrupt enable on INT2 pin. Default value: 0. H_LACTIVE interrupt active. Default value: 0. Table 47. REFERENCE/DATACAPTURE_A register
8.13 STATUS_REG_A (27h)
8.14 OUT_X_L_A (28h), OUT_X_H_A (29h)
X-axis acceleration data. The value is expressed as two’s complement left-justified. Please refer to Section 4.2.1: Accelerometer power modes.
8.15 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh)
Y-axis acceleration data. The value is expressed as two’s complement left-justified. Please refer to Section 4.2.1: Accelerometer power modes.
8.16 OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh)
Z-axis acceleration data. The value is expressed as two’s complement left-justified. Please refer to Section 4.2.1: Accelerometer power modes. Table 48. REFERENCE/DATACAPTURE_A description Table 49. STATUS_REG_A register Table 50. STATUS_REG_A description
8.17 FIFO_CTRL_REG_A (2Eh)
8.18 FIFO_SRC_REG_A (2Fh)
Table 55. FIFO_SRC_REG_A description Table 51. FIFO_CTRL_REG_A register Table 52. FIFO_CTRL_REG_A description Table 53. FIFO mode configuration Table 54. FIFO_SRC_REG_A register WTM WTM bit is set high when FIFO content exceeds watermark level. EMPTY EMPTY flag is set high when all FIFO samples have been read and FIFO is empty.
8.19 INT1_CFG_A (30h)
The content of this register is loaded at boot. A write operation to this address is possible only after system boot. Table 56. INT1_CFG_A register Table 57. INT1_CFG_A description AOI And/Or combination of interrupt events. Default value: 0. Refer to Table 58. 6D 6-direction detection function enabled. Default value: 0. Refer to Table 58.
The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. inside a known zone. The interrupt signal remains while the orientation is inside the zone.
8.20 INT1_SRC_A (31h)
Interrupt 1 source register. Read-only register. Table 58. Interrupt mode Table 59. INT1_SRC_A register
0 I A Z HZ LY HY LX HX L
Table 60. INT1_SRC_A description
8.21 INT1_THS_A (32h)
8.22 INT1_DURATION_A (33h)
steps and maximum values depend on the ODR chosen. Duration time is measured in N/ODR, where N is the content of the duration register.
8.23 INT2_CFG_A (34h)
Table 61. INT1_THS_A register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 62. INT1_THS_A description
1 LSb = 16 mg @ FS = 2 g
1 LSb = 32 mg @ FS = 4 g
1 LSb = 62 mg @ FS = 8 g
1 LSb = 186 mg @ FS = 16 g
Table 63. INT1_DURATION_A register
0 D 6D 5D 4D 3D 2D 1D 0
Table 64. INT1_DURATION_A description
1 LSb = 1/ODR
Table 65. INT2_CFG_A register Table 66. INT2_CFG_A description 6D 6-direction detection function enabled. Default value: 0. Refer to Table 67.
The content of this register is loaded at boot. A write operation to this address is possible only after system boot. The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. inside a known zone. The interrupt signal remains while the orientation is inside the zone.
8.24 INT2_SRC_A (35h)
Table 67. Interrupt mode Table 66. INT2_CFG_A description (continued) Table 68. INT2_SRC_A register
Interrupt 2 source register. Read-only register.
8.25 INT2_THS_A (36h)
8.26 INT2_DURATION_A (37h)
Table 69. INT2_SRC_A description Table 70. INT2_THS_A register Table 71. INT2_THS_A description Table 72. INT2_DURATION_A register
time steps and maximum values depend on the ODR chosen.
8.27 CLICK_CFG_A (38h)
Table 73. INT2_DURATION_A description
1 LSb = 1/ODR(1)
- Duration time is measured in N/ODR, where N is the content of the duration register.
Table 74. CLICK_CFG_A register Table 75. CLICK_CFG_A description
8.28 CLICK_SRC_A (39h)
8.29 CLICK_THS_A (3Ah)
8.30 TIME_LIMIT_A (3Bh)
Table 76. CLICK_SRC_A register Table 77. CLICK_SRC_A description Table 78. CLICK_THS_A register Table 79. CLICK_SRC_A description Table 80. TIME_LIMIT_A register Table 81. TIME_LIMIT_A description
8.31 TIME_LATENCY_A (3Ch)
8.32 TIME_WINDOW_A (3Dh)
8.33 Act_THS_A (3Eh)
8.34 Act_DUR_A (3Fh)
Table 82. TIME_LATENCY_A register Table 83. TIME_LATENCY_A description Table 84. TIME_WINDOW_A register Table 85. TIME_WINDOW_A description Table 86. Act_THS_A register Table 87. Act_THS_A description Table 88. Act_DUR_A register Table 89. Act_DUR_A description
1 LSb = (8*1[LSb]+1)/ODR
8.35 OFFSET_X_REG_L_M (45h) and OFFSET_X_REG_H_M (46h)
magnetic output data value in order to delete the environmental offset.
8.36 OFFSET_Y_REG_L_M (47h) and OFFSET_Y_REG_H_M (48h)
magnetic output data value in order to delete the environmental offset.
8.37 OFFSET_Z_REG_L_M (49h) and OFFSET_Z_REG_H_M (4Ah)
magnetic output data value in order to delete the environmental offset.
8.38 WHO_AM_I_M (4Fh)
The identification register is used to identify the device (read-only register).
8.39 CFG_REG_A_M (60h)
Table 90. CFG_REG_A_M register Table 91. CFG_REG_A_M register description registers keep their values.
8.40 CFG_REG_B_M (61h)
Table 94. CFG_REG_B_M register Table 95. CFG_REG_B_M register description Table 92. Output data rate configuration Table 93. System mode performs measurements and places the result in the data register. the INT_MAG bit in CFG_REG_C_M (62h). single measurement, sets DRDY high and returns to idle mode. Mode register return to idle mode bit values. 1 1 Idle mode. Device is placed in idle mode. I 2C and SPI active. Set_FREQ Selects the frequency of the set pulse. OFF_CANC Enables offset cancellation. Table 96. Digital low-pass filter
8.41 CFG_REG_C_M (62h)
Table 97. CFG_REG_C_M register Table 98. CFG_REG_C_M register description
8.42 INT_CTRL_REG_M (63h)
The interrupt control register is used to enable and to configure the interrupt recognition. Table 99. INT_CRTL_REG_M register Table 100. INT_CTRL_REG_M register description
0 INT_MAG
- This bit must be set to ‘0’ for the correct operation of the device.
I2C_DIS If ‘1’, the I 2C interface is inhibited. Only the SPI interface can be used. one part is updated and the other one remains old. BLE If ‘1’, an inversion of the low and high parts of the data occurs. Self_test If ‘1’, the self-test is enabled. INT_MAG If ‘1’, the DRDY pin is configured as a digital output.
- This bit must be set to ‘0’ for the correct operation of the device.
IEL Controls whether the INT bit ( INT_SOURCE_REG_M (64h)) is latched or pulsed. If IEL = 0, then INT is pulsed. If IEL = 1, then INT is latched. Once latched, INT remains in the same state until INT_SOURCE_REG_M (64h) is read.
8.43 INT_SOURCE_REG_M (64h)
When interrupt latched is selected, reading this register resets all the bits in this register. Table 101. INT_SOURCE_REG_M register Table 102. INT_SOURCE_REG_M register description
8.44 INT_THS_L_REG_M (65h)
This register contains the least significant bits of the threshold value chosen for the interrupt. Table 103. INT_THS_L_REG_M register Table 104. INT_THS_L_REG_M register description
8.45 INT_THS_H_REG_M (66h)
Table 105. INT_THS_H_REG_M register Table 106. INT_THS_H_REG_M register description threshold is detected for both positive and negative sides. INT This bit signals when the interrupt event occurs. TH[7:0] Threshold value for the interrupt. TH[7:0] Threshold value for the interrupt.
8.46 STATUS_REG_M (67h)
status register. SR7 denotes the first bit of the data stream. Table 107. STATUS_REG_M register Table 108. STATUS_REG_M register description
8.47 OUTX_L_REG_M, OUTX_H_REG_M (68h - 69h)
output X LSB register (68h). otherwise hard-iron calibration is included. Table 109. OUTX_L_REG_M register Table 110. OUTX_H_REG_M register X component of the magnetic data. (0: no overrun has occurred; 1: a new set of data has overwritten the previous set). (0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data). (0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data). (0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data). (0: a new set of data is not yet available; 1: a new set of data is available).
8.48 OUTY_L_REG_M, OUTY_H_REG_M (6Ah - 6Bh)
output Y LSB register (6Ah). otherwise hard-iron calibration is included. Table 111. OUTY_L_REG_M register Table 112. OUTY_H_REG_M register Y component of the magnetic data.
8.49 OUTZ_L_REG_M, OUTZ_H_REG_M (6Ch - 6Dh)
output Z LSB register (6Ah). otherwise hard-iron calibration is included. Table 113. OUTZ_L_REG_M register Table 114. OUTZ_H_REG_M register Z component of the magnetic data.
9 Package information
specifications, grade definitions and product status are available at: www.st.com.
9.1 LGA-12 package information
Figure 17. LGA-12 2x2x1 mm package outline and mechanical data
Table 115. Document revision history