LSJ689 LINEAR | Alldatasheet
Document overview
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Technical content
Features
Reduced Noise due to process improvement Monolithic Design High slew rate Low offset/drift voltage Low gate leakage lgss & lg High CMRR 102 dB Benefits Tight differential voltage match vs. current Improved op amp speed settling time accuracy Minimum Input Error trimming error voltage Lower intermodulation distortion
Applications
Wide band differential Amps High speed temperature compensated single ended input amplifier amps High speed comparators Impedance Converters
Description
The LSJ689 high performance, P-Channel, monolithic dual JFET features extremely low noise, tight offset voltage and low drift over temperature. It is targeted for use in a wide range of precision instrumentation applications. The SOT-23, TO-71 and SO-8 packages provide ease of manufacturing and the symmetrical pinouts prevent improper orientation. The SOT-23 and SO-8 packages are available in tape and reel, compatible with automatic assembly methods. (See packaging data) LSJ689 LOW NOISE LOW CAPACITANCE MONOLITHIC DUAL P-CHANNEL JFET AMPLIFIER PRELIMINARY SOIC-A TOP VIEW TO-71 TOP VIEW SOT-23 TOP VIEW Three Decades of Quality Through Innovation
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201180 06/13/16 Rev#A7 ECN# LSJ689 LSJ689 PRELIMINARY MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated) SYMBOL CHARACTERISTIC MIN TYP MAX UNITS CONDITIONS GS2GS1 VV Differential Gate to Source Voltage 20 mV VDS = -15V, IG = -1mA DSS2 DSS1 I I Saturation Drain Current Ratio 0.90 1.0 VDS = -15V, VGS = 0V CMRR COMMON MODE REJECTION RATIO -20 log│∆VGS1-2/∆VDS│ 95 102 db VDS = -10V to -20V, ID = -200µA SYMBOL CHARACTERISTIC MIN TYP MAX UNITS CONDITIONS en Noise Voltage 2.0 nV/√Hz VDS = -15V, ID = -2.0mA, f = 1kHz, NBW = 1Hz en Noise Voltage 3.5 nV/√Hz VDS = -15V, ID = -2.0mA, f = 10Hz, NBW = 1Hz CISS Common Source Input Capacitance 8 pF VDS = -15V, ID = -200µA, f = 1MHz CRSS Common Source Reverse Transfer Capacitance 3 pF ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise stated) SYMBOL CHARACTERISTIC MIN TYP MAX UNITS CONDITIONS BVGSS Gate to Source Breakdown Voltage 50 V VDS = 0V, IG = 1µA V(BR)G1 - G2 Gate to Gate Breakdown Voltage ±30 ±45 V IG= ±1µA, ID=IS=0A (Open Circuit) VGS(OFF) Gate to Source Pinch-off Voltage 1.50 5.0 V VDS = -15V, ID = -1nA IDSS2 Drain to Source Saturation Current -2.5 -30 mA VDS = -15V, VGS = 0V IG Gate Operating Current 2 pA VDG = -15V, ID = -200µA IGSS Gate to Source Leakage Current 0.9 100 pA VGS = 15V, VDS = 0V Gfs Full Conductance Transconductance 1500 µS VDS = -15V, VGS = 0V, f = 1kHz Gfs Transconductance 1500 µS VDS = -15V, ID = -200µA, f = 1kHz GOS Full Output Conductance 38 µS VDS = -15V, VGS = 0V, f = 1kHz GOS Output Conductance 3 µS VDS = -15V, ID = -200µA, f = 1kHz NF Noise Figure 0.5 db VDS = -15V, VGS = 0V, RG = 10mΩ TYPICAL SPICE PARAMETERS FOR LSJ689 IN LT SPICE FORMAT: LSJ689_4 IDSS = 14.0mA RDS=112 .MODEL LSJ689_4 PJF (LEVEL=1 BETA=28E-4 VTO=-2.75 LAMBDA=2E-3 + IS=4.5E-16 N= 1 RD=73 RS=35 CGD=6E-12 CGS=11E-12 PB=0.25 MJ=0.3 FC=0.5 + KF=2E-18 AF=1 XTI=0)
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201180 06/13/16 Rev#A7 ECN# LSJ689 LSJ689 PRELIMINARY NOTES 1. Absolute maximum ratings are limiting values above which serviceability may be impaired. 2. Pulse width ≤2ms. 3. All MIN/TYP/MAX Limits are absolute values. Negative signs indicate electrical polarity only. 4. Derate 2.4 mW/°C above 25°C. 5. Derate 4 mW/°C above 25°C. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. PACKAGE DIMENSIONS DIMENSIONS IN INCHES SOT-23 DIMENSIONS IN MILLIMETERS 0.95 1.90 1.50 1.75 2.60 3.00 0.35 0.50 2.80 3.00 0.90 1.30 0.00 0.15 0.09 0.20 0.10 0.60 Six Lead 0.210 0.170 DIMENSIONS IN INCHES DIMENSIONS IN MILLIMETERS TO-71 SIX LEAD SOIC-A EIGHT LEAD SOT-23 SIX LEAD
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201180 06/13/16 Rev#A7 ECN# LSJ689 TYPICAL CHARACTERISTICS -16.0 -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 DRAIN CURRENT (mA) DRAIN-SOURCE VOLTAGE (V) Output Characteristics Tj=25 C VGS=0.4V VGS=2.0V VGS=0.8V VGS=1.2V VGS=0.0V VGS=0.2V VGS=0.6V VGS=1.0V -16.0 -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 DRAIN CURRENT (mA) DRAIN - SOURCE VOLTAGE (V) Output CharacteristicsTj=250C VGS=0.4V VGS=2.0V VGS=0.8V VGS=1.2V VGS=0.0V VGS=0.2V VGS=0.6V VGS=1.0V -5.0 -4.0 -3.0 -2.0 -1.0 0.0 DRAIN CURRENT (mA) DRAIN - SOURCE VOLTAGE (V) OUTPUT CHARACTERISTICS Tj=250C
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201180 06/13/16 Rev#A7 ECN# LSJ689 TYPICAL CHARACTERISTICS (CONT’D) 200 400 600 800 1,0000 Rds(on) - Drain-Source On-Resistance (Ω) VGS(off) - Gate-Source Cutoff Voltage (V) On-Resistance and Output Conductance vs. Gate-Source Cutoff Voltage Tj=250C 200 400 600 800 1,000 200 400 600 800 1,0000 Rds(on) - Drain-Source On-Resistance (Ω) VGS(off) - Gate-Source Cutoff Voltage (V) On-Resistance and Output Conductance vs. Gate-Source Cutoff Voltage Tj=250C Gos-Output Conductance (uS) Rds(on) - Drain-Source On-Resistance (Ω)
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201180 06/13/16 Rev#A7 ECN# LSJ689 TYPICAL CHARACTERISTICS (CONT’D) Linear Integrated Systems (LIS) is a 25 -year-old, third -generation precision semiconductor company providing high -quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, Co -Founder and Vice President of R&D at Intersil, and Founder/President of Micro Power Systems.