LSF0204 TI1 | Alldatasheet
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Vref_A Vref_B EN GND LSF0204 SW SW SW SW Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LSF0204,LSF0204D SLVSCP5D –JULY 2014–REVISED DECEMBER 2015 LSF0204x4-BitsBidirectionalMulti-VoltageLevelTranslatorforOpen-DrainandPush- PullApplication
1 Features 3 Description
The LSF family consists of bidirectional voltage level 1• Provides Bidirectional Voltage Translation With No Greater Than 100-MHz Down Translation 5.0 V without the need for a direction terminal in at ≤ 30-pF Capacitor Load and up to 40-MHz open-drain or push-pull applications. The LSF family Up/Down Translation at 50-pF Capacitor Load supports level translation applications with transmission speeds greater than 100 MHz for open-• Supports Ioff, Partial Power Down Mode (Refer to drain systems that utilize a 15-pF capacitance andFeature Description) 165-Ω pull-up resistor.• Allows Bidirectional Voltage Level Translation When the An or Bn port is LOW, the switch is in theBetween – 1.2 V ↔ 1.8, 2.5, 3.3, 5 V switch allows connections to be made with minimal propagation delay and signal distortion. The voltage– 1.8 V ↔ 2.5, 3.3, 5 V on the A or B side will be limited to Vref_A and can– 2.5 V ↔ 3.3, 5 V be pulled up to any level between Vref_A and 5 V.– 3.3 V ↔ 5 V This functionality allows a seamless translation
- Low Standby Current between higher and lower voltages selected by the user without the need for directional control.• 5 V Tolerance I/O Port to Support TTL
- Low Ron Provides Less Signal Distortion Device Information(1)
- High-Impedance I/O Terminals For EN = Low PART NUMBER PACKAGE BODY SIZE (NOM)
- Flow-Through Pinout for Ease PCB Trace Routing TSSOP (14) 5.00 mm × 4.40 mm
- Latch-Up Performance Exceeds 100 mA Per UQFN (12) 2.00 mm × 1.70 mm LSF0204xJESD17 VQFN (14) 3.50 mm × 3.50 mm
- –40°C to 125°C Operating Temperature Range DSBGA (12) 1.90 mm × 1.40 mm
- ESD Performance Tested Per JESD 22 (1) For all available packages, see the orderable addendum at the end of the datasheet.– 2000-V Human-Body Model (A114-B, Class II) – 200-V Machine Model (A115-A) Simplified Schematic – 1000-V Charged-Device Model (C101)
2 Applications
- GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and Other Interfaces in Telecom Infrastructure
- Industrial
- Automotive
- Personal Computing An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
LSF0204,LSF0204D SLVSCP5D –JULY 2014–REVISED DECEMBER 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2015) to Revision D Page Changes from Revision B (April 2015) to Revision C Page Changes from Revision A (December 2014) to Revision B Page Changes from Original (November 2014) to Revision A Page
- Changed text in the Description From: "transmission speeds greater than 100 Mbps" To: "transmission speeds
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Product Folder Links: LSF0204 LSF0204D
Vref_BVref_A NC ENGND 1 14 7 8 1 1 Vref_A GND Vref_B EN 5 6 7 1 112 7 8 1 1 14Vref_A NC GND Vref_B NC EN LSF0204,LSF0204D www.ti.com SLVSCP5D –JULY 2014–REVISED DECEMBER 2015
5 Description (continued)
The supply voltage (Vpu#) for each channel may be individually set up with a pull up resistor. For example, CH1 When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. The EN input circuit is designed to be supplied by Vref_A. EN must be LOW to ensure the high-impedance state during power-up or power-down.
6 Device Comparison Table
PART EN An Bn DESCRIPTIONNUMBER Place all data pins in 3 state modeLSF0204D H Place all data pins in 3 state mode (Hi-Z) 3-state output mode enable(Hi-Z) (active Low; referenced to Vref_A)LSF0204D L Input or output Input or output LSF0204 H Input or output Input or output 3-state output mode enable Place all data pins in 3 state mode (active High, referenced to Vref_A)LSF0204 L Place all data pins in 3 state mode (Hi-Z)(Hi-Z)
7 Pin Configuration and Functions
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LSF0204 LSF0204D
LSF0204,LSF0204D SLVSCP5D –JULY 2014–REVISED DECEMBER 2015 www.ti.com Pin Functions PIN NO. TYPE DESCRIPTION NAME PW, RGY RUT YZP Vref_A 1 1 B2 -- Reference supply voltage; see Application and Implementation section A1 2 2 A3 I/O Input/output 1. A2 3 3 B3 I/O Input/output 2. A3 4 4 C3 I/O Input/output 3. A4 5 5 D3 I/O Input/output 4. NC 6 – – -- No connection. Not internally connected. GND 7 6 D2 -- Ground Switch enable input; LSF0204: EN is high-active; LSF0204D: EN isEN 8 12 C2 I low-active NC 9 – – -- No connection. Not internally connected. B4 10 7 D1 I/O Input/output 4. B3 11 8 C1 I/O Input/output 3. B2 12 9 B1 I/O Input/output 2. B1 13 10 A1 I/O Input/output 1. Vref_B 14 11 A2 -- Reference supply voltage; see Application and Implementation section
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Product Folder Links: LSF0204 LSF0204D
LSF0204,LSF0204D www.ti.com SLVSCP5D –JULY 2014–REVISED DECEMBER 2015
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VI Input voltage (2) –0.5 7 V VI/O Input/output voltage (2) –0.5 7 V Continuous channel current 128 mA IIK Input clamp current VI < 0 –50 mA TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
8.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±1000C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VI/O Input/output voltage 0 5 V Vref_A/B/EN Reference voltage 0 5 V IPASS Pass transistor current 64 mA TA Operating free-air temperature –40 125 °C
8.4 Thermal Information
THERMAL METRIC(1) RGY (VQFN) RUT (UQFN) PW (TSSOP) UNIT
14 PINS 12 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 83.2 195.8 157.9 °C RθJC(top) Junction-to-case (top) thermal resistance 98.2 98.7 82.3 °C RθJB Junction-to-board thermal resistance 59.2 122.6 100.0 °C ψJT Junction-to-top characterization parameter 17.4 6.2 22.9 °C ψJB Junction-to-board characterization parameter 59.4 122.6 99.0 °C RθJC(bot) Junction-to-case (bottom) thermal resistance 38.7 N/A N/A °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LSF0204 LSF0204D
LSF0204,LSF0204D SLVSCP5D –JULY 2014–REVISED DECEMBER 2015 www.ti.com
8.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIK II = -18 mA, VEN = 0 –1.2 V IIH VI = 5 V, VEN = 0 5.0 µA Leakage fromICCBA Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or GND 3.5 µAVref_B to Vref_A Total CurrentICCA + ICCB (2) Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or GND 0.2 µAthrough GND IIN Control pin current Vref_B = 5.5 V, Vref_A = 4.5 V, VEN = 0 to Vref_A IO = 0 ±1 µA Power OffIoff Vref_B = Vref_A = 0 V, VEN = GND IO = 0, VI = 5 V or GND ±1 µALeakage Current CI(ref_A/B/EN) VI = 3 V or 0 7 pF Cio(off) VO = 3 V or 0, VEN = 0 5.0 6.0 pF Cio(on) VO = 3 V or 0, VEN = Vref_A 10.5 13 pF High-level input 0.7×Vref_(3)VIH (EN pin) Vref_A = 1.5 V to 4.5 V Vvoltage A Low-level input 0.3×Vref_VIL (EN pin) Vref_A = 1.5 V to 4.5 V Vvoltage A High-level input 0.8×Vref_VIH (EN pin) Vref_A= 1.0 V to 1.5 V Vvoltage A Low-level input 0.3×Vref_VIL (EN pin) Vref_A = 1.0 V to 1.5 V Vvoltage A Input transition rise ∆t/∆v (EN pin) or fall rate for EN 10 ns/V pin Vref_A = VEN = 3.3 V; Vref_B = 5 V 3 VI = 0, IO = 64 mA Ω Vref_A = VEN = 1.8 V; Vref_B = 5 V 4 Vref_A = VEN = 1.0 V; Vref_B = 5 V 9 VI = 0, IO = 32 mA Ω Vref_A = VEN = 1.8 V; Vref_B = 5 V 4 ron (4) VI = 0, IO = 32 mA , Vref_A = VEN = 2.5 V; Vref_B = 5 V 10 Ω VI = 1.8 V, IO = 15 mA, Vref_A = VEN = 3.3 V; Vref_B = 5 V 5 Ω VI = 1.0 V, IO = 10 mA, Vref_A = VEN = 1.8 V; Vref_B = 3.3 V 8 Ω VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 3.3 V 6 Ω VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 1.8 V 6 Ω (1) All typical values are at TA = 25°C. (2) The actual supply current for LSF0204 is ICCA + ICCB; the leakage from Vref_B to Vref_A can be measured on Vref_A and Vref_B pin (3) Enable pin test conditions are for the LSF0204. The enable pin test conditions for LSF0204D are oppositely set. (4) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. 8.6 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V) over recommended operating free-air temperature range, Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V, Vpu_2 = 1.8 V, RL = NA, VIH = 3.3 V, VIL = 0 VM = 1.15 V (unless otherwise noted) CL = 50 pF CL = 30 pF CL = 15 pF PARAMETER FROM (INPUT) TO (OUTPUT) UNIT TYP MAX TYP MAX TYP MAX tPLZ A or B B or A 13 18 12 16.5 11 15 ns tPZL 33 45 30 40 23 37 ns fMAX 50 100 100 MHz
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Product Folder Links: LSF0204 LSF0204D
8.10 Typical Characteristics
Figure 4. Signal Integrity (1.8 V to 3.3 V Translation Up at 50 MHz)
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR≤ ≤ ≤10 MHz, Z = 50 t 2 ns, tO r f Ω, 2□ns. C. The outputs are measured one at a time, with one transition per measurement.
9 Parameter Measurement Information
Figure 5. Load Circuit for Outputs Figure 6. Load Circuit for Enable/Disable Time Measurement
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9.1 Load Circuit AC Waveform for Outputs
Figure 7. tPLH, tPHL Figure 8. tPLZ, tPZL
Vref_A Vref_B EN 200 KΩ Level Converter LSF0204,LSF0204D SLVSCP5D –JULY 2014–REVISED DECEMBER 2015 www.ti.com
10 Detailed Description
10.1 Overview
The LSF Family may be used in level translation applications for interfacing devices or systems operating at different interface voltages with one another. The LSF Family is ideal for use in applications where an open-drain driver is connected to the data I/Os. LSF can achieve 100 MHz with the appropriate pull-up resistors and layout. The LSF Family may also be used in applications where a push-pull driver is connected to the data I/Os.
10.2 Functional Block Diagram
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Product Folder Links: LSF0204 LSF0204D
10.3 Feature Description
10.3.1 Support High Speed Translation, Greater than 100 MHz
Allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).
10.3.2 Bidirectional Voltage Translation Without DIR Terminal
Minimizes system effort to develop voltage translation for bidirectional interface (PMBus, I2C, or SMbus).
10.3.4 Channel Specific Translation
The LSF family is able to set up different voltage translation levels on each channel.
10.3.5 Ioff, Partial Power Down Mode
When Vref_A, Vref_B = 0, all of data pins and EN pin are Hi-Z. and EN ready. No power sequence is required to enable LSF0204 and operate function normally.
10.4 Device Functional Modes
Table 1 lists the device functional modes of the LSF0204x family of devices. Table 1. Function Table (1) EN is controlled by Vref_A logic levels.
validate and test their design implementation to confirm system functionality.
11.1 Application Information
interfaces as reference in regards to the different channel numbers that are supported by the LSF family. Table 2. Voltage Translator for Consumer/Telecom Interface
11.2 Typical Applications
11.2.1 I2C PMBus, SMBus, GPIO, Application
Figure 9. Bidirectional Translation to Multiple Voltage Levels
11.2.1.1 Design Requirements
11.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low. It is recommended to always enable LSF family for bidirectional application (I2C, SMBus, PMBus, or MDIO).
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Table 3. Application Operating Condition Also Vref_B is recommended to be at 1.0 V higher than Vref_A for best signal integrity. The LSF Family is able to set different voltage translation level on each channel. Vref_A must be set as lowest voltage level.
11.2.1.2 Detailed Design Procedure
11.2.1.2.1 Bidirectional Translation
output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu). In Figure 9, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage. output voltage equal to Vpu. mA, to calculate the pull-up resistor value use Equation 1.
Table 4. Pullup Resistor Values(1)(2)
5 V 310 341 465 512 1550 1705
3.3 V 197 217 295 325 983 1082
2.5 V 143 158 215 237 717 788
1.8 V 97 106 145 160 483 532
1.5 V 77 85 115 127 383 422
1.2 V 57 63 85 94 283 312
11.2.1.2.2 LS Family Bandwidth
100MHz gave the correct conditions. The maximum frequency is dependent upon the loading of the application.
resistance and on capacitance of the device. Figure 10 shows a bandwidth measurement of the LSF family using a two-port network analyzer. Figure 10. 3-dB Bandwidth The 3-dB point of the LSF family is ≈600MHz; however, this measurement is an analog type of measurement. greater than 100 MHz may be achieved. family on the sink side (1.8 V) to minimize signal degradation.
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very common in many of today's device specifications, fknee is equal to 0.4 divided by the rise time of the signal.
- Keep trace length to a minimum by placing the LSF family close to the I2C output of the processor.
- The trace length should be less than half the time of flight to reduce ringing and line reflections or non- monotonic behavior in the switching region.
- To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to be expected.
11.2.1.3 Application Curve
Figure 11. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz)
11.2.2 MDIO Application
Figure 12. Typical Application Circuit (MDIO/Bidirectional Interface)
11.2.2.1 Design Requirements
Refer to Design Requirements.
11.2.2.2 Detailed Design Procedure
11.2.2.3 Application Curve
Figure 13. Captured Waveform From Above MDIO Setup
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11.2.3 Multiple Voltage Translation in Single Device, Application
11.2.3.1 Design Requirements
Refer to Design Requirements.
11.2.3.2 Detailed Design Procedure
11.2.3.3 Application Curve
Figure 14. Translation Down (3.3 V to 1.8 V) at 150 MHz
12 Power Supply Recommendations
Voltage Guidelines for enabling and reference voltage guidelines.
13 Layout
13.1 Layout Guidelines
- Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
- Place LSF close to high voltage side.
- Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.
13.2 Layout Example
Figure 15. Short Trace Layout Figure 16. Device Placement
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Figure 17. Waveform From TP1 (Pullup Resistor: 160-Ω Figure 18. Waveform From TP2 (Pullup Resistor: 160-Ω
14 Device and Documentation Support
14.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 5. Related Links
14.2 Community Resources
solve problems with fellow engineers. contact information for technical support.
14.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
14.4 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
14.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 19-Nov-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LSF0204DPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LSF204D LSF0204DRGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LSF24D LSF0204DRUTR ACTIVE UQFN RUT 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIO LSF0204DYZPR ACTIVE DSBGA YZP 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 G6 LSF0204PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LSF204 LSF0204RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LSF24 LSF0204RUTR ACTIVE UQFN RUT 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIN LSF0204YZPR ACTIVE DSBGA YZP 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 G5 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
www.ti.com 19-Nov-2015 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LSF0204DPWR TSSOP PW 14 2000 364.0 364.0 27.0 LSF0204DRGYR VQFN RGY 14 3000 367.0 367.0 35.0 LSF0204DRUTR UQFN RUT 12 3000 184.0 184.0 19.0 LSF0204DYZPR DSBGA YZP 12 3000 182.0 182.0 20.0 LSF0204PWR TSSOP PW 14 2000 364.0 364.0 27.0 LSF0204RGYR VQFN RGY 14 3000 367.0 367.0 35.0 LSF0204RUTR UQFN RUT 12 3000 184.0 184.0 19.0 LSF0204YZPR DSBGA YZP 12 3000 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2015 Pack Materials-Page 2
D: Max = E: Max = 1.972 mm, Min = 1.472 mm, Min = 1.912 mm 1.412 mm
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