LSF0204DRUTR.B

LSF0204_V01 TI | Alldatasheet

Document overview

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Technical content

LSF0204x 4-Bits Bidirectional Multi-Voltage Level Translator for Open-Drain and Push-Pull Application

1 Features

• Provides bidirectional voltage translation with no direction terminal
• Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30-pF capacitor load and up to 40-MHz up/ down translation at 50-pF capacitor load
• Supports Ioff, partial power-down mode (refer to Feature Description)
• Allows bidirectional voltage level translation between – 2.5 V ↔ 3.3, 5 V – 3.3 V ↔ 5 V
• Low standby current
• 5 V Tolerance I/O port to support TTL
• Low Ron provides less signal distortion
• High-impedance I/O terminals for EN = Low
• Flow-through pinout for easy PCB trace routing
• Latch-up performance exceeds 100 mA per JESD17
• –40°C to 125°C operating temperature range
• ESD performance tested per JESD 22 – 2000-V human-body model (A114-B, Class II) – 200-V machine model (A115-A) – 1000-V charged-device model (C101)

2 Applications

• GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and other interfaces in telecom infrastructure
• Industrial
• Automotive
• Personal computing

3 Description

The LSF family consists of bidirectional voltage level translators that operate from 0.8 V to 4.5 V (Vref_A) and 1.8 V to 5.5 V (Vref_B). This range allows for bidirectional voltage translations between 0.8 V and 5.0 V without the need for a direction terminal in open-drain or push-pull applications. The LSF family supports level translation applications with transmission speeds greater than 100 MHz for open- drain systems that utilize a 15-pF capacitance and 165-Ω pull-up resistor. When the An or Bn port is LOW, the switch is in the ON-state and a low resistance connection exists between the An and Bn ports. The low R on of the switch allows connections to be made with minimal propagation delay and signal distortion. The voltage on the A or B side will be limited to Vref_A and can be pulled up to any level between Vref_A and 5 V. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LSF0204x TSSOP (14) 5.00 mm × 4.40 mm UQFN (12) 2.00 mm × 1.70 mm VQFN (14) 3.50 mm × 3.50 mm DSBGA (12) 1.90 mm × 1.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Vref_A Vref_B EN GND LSF0204 SW SW SW SW Simplified Schematic LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

7.6 Switching Characteristics: AC Performance

7.7 Switching Characteristics: AC Performance

7.8 Switching Characteristics: AC Performance

7.9 Switching Characteristics: AC Performance

13.1 Receiving Notification of Documentation Updates..21

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (November 2019) to Revision H (April 2021) Page Changes from Revision F (January 2019) to Revision G (November 2019) Page Changes from Revision E (December 2018) to Revision F (January 2019) Page Changes from Revision D (December 2015) to Revision E (December 2018) Page Changes from Revision C (August 2015) to Revision D (December 2015) Page Changes from Revision B (April 2015) to Revision C (August 2015) Page Changes from Revision A (December 2014) to Revision B (April 2015) Page LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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Changes from Revision * (November 2014) to Revision A (December 2014) Page

• Changed text in the Section 3 From: "transmission speeds greater than 100 Mbps" To: "transmission speeds www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LSF0204 LSF0204D

5 Description (continued)

The supply voltage (V pu#) for each channel may be individually set up with a pull up resistor. For example, CH1 When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. The EN input circuit is designed to be supplied by Vref_A. EN must be LOW to ensure the high-impedance state during power-up or power-down. Device Comparison Table PART NUMBER EN An Bn DESCRIPTION LSF0204D H Place all data pins in 3 state mode (Hi-Z) Place all data pins in 3 state mode (Hi-Z) 3-state output mode enable (active Low; referenced to Vref_A) LSF0204D L Input or output Input or output LSF0204 H Input or output Input or output 3-state output mode enable (active High, referenced to Vref_A)LSF0204 L Place all data pins in 3 state mode (Hi-Z) Place all data pins in 3 state mode (Hi-Z)

6 Pin Configuration and Functions

14Vref_A NC GND Vref_B NC EN Figure 6-1. PW Package, 14-Pin TSSOP (Top View) NC Vref_BVref_A NC ENGND 1 14 7 8 1 1 13 Figure 6-2. RGY Package, 14-Pin VQFN (Transparent Top View) Vref_A GND Vref_B EN 5 6 7 1 112 Figure 6-3. RUT Package, 12-Pin UQFN (Transparent Top View) Figure 6-4. YZP Package, 12-Pin DSBGA (Transparent Top View) LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. PW, RGY RUT YZP Vref_A 1 1 B2 — Reference supply voltage; see Application and Implementation section A1 2 2 A3 I/O Input/output 1. A2 3 3 B3 I/O Input/output 2. A3 4 4 C3 I/O Input/output 3. A4 5 5 D3 I/O Input/output 4. NC 6 – — — No connection. Not internally connected. GND 7 6 D2 — Ground EN 8 12 C2 I Switch enable input; LSF0204: EN is high-active; LSF0204D: EN is low-active NC 9 – — — No connection. Not internally connected. B4 10 7 D1 I/O Input/output 4. B3 11 8 C1 I/O Input/output 3. B2 12 9 B1 I/O Input/output 2. B1 13 10 A1 I/O Input/output 1. Vref_B 14 11 A2 — Reference supply voltage; see Application and Implementation section (1) I = input, O = output www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LSF0204 LSF0204D

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VI Input voltage (2) –0.5 7 V VI/O Input/output voltage (2) –0.5 7 V Continuous channel current 128 mA IIK Input clamp current VI < 0 –50 mA TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VI/O Input/output voltage 0 5.5 V Vref_A/B/EN Reference voltage 0 5.5 V IPASS Pass transistor current 64 mA TA Operating free-air temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) LSF0204 UNITRGY (VQFN) RUT (UQFN) PW (TSSOP) YZP (DSBGA)

14 PINS 12 PINS 14 PINS 12 BALLS

RθJA Junction-to-ambient thermal resistance 83.2 195.8 157.9 83.7 °C RθJC(top) Junction-to-case (top) thermal resistance 98.2 98.7 82.3 0.6 °C RθJB Junction-to-board thermal resistance 59.2 122.6 100.0 23.7 °C ψJT Junction-to-top characterization parameter 17.4 6.2 22.9 0.4 °C ψJB Junction-to-board characterization parameter 59.4 122.6 99.0 23.7 °C RθJC(bot) Junction-to-case (bottom) thermal resistance 38.7 N/A N/A N/A °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIK II = -18 mA, VEN = 0 –1.2 V IIH VI = 5 V, VEN = 0 5.0 µA ICCBA Leakage from Vref_B to Vref_A Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or GND 3.5 µA ICCA + ICCB (4) Total Current through GND Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or GND 0.2 µA IIN Control pin current Vref_B = 5.5 V, Vref_A = 4.5 V, VEN = 0 to Vref_A IO = 0 ±1 µA Ioff Power Off Leakage Current Vref_B = Vref_A = 0 V, VEN = GND IO = 0, VI = 5 V or GND ±1 µA CI(ref_A/B/EN) VI = 3 V or 0 7 pF Cio(off) VO = 3 V or 0, VEN = 0 5.0 6.0 pF Cio(on) VO = 3 V or 0, VEN = Vref_A 10.5 13 pF (3)VIH (EN pin) High-level input voltage Vref_A = 1.5 V to 4.5 V 0.7×Vref_A V VIL (EN pin) Low-level input voltage Vref_A = 1.5 V to 4.5 V 0.3×Vref_A V VIH (EN pin) High-level input voltage Vref_A= 1.0 V to 1.5 V 0.8×Vref_A V VIL (EN pin) Low-level input voltage Vref_A = 1.0 V to 1.5 V 0.3×Vref_A V ∆t/∆v (EN pin) Input transition rise or fall rate for EN pin 10 ns/V ron (2) VI = 0, IO = 64 mA Vref_A = VEN = 3.3 V; Vref_B = 5 V 3 Ω Vref_A = VEN = 1.8 V; Vref_B = 5 V 4 VI = 0, IO = 32 mA Vref_A = VEN = 1.0 V; Vref_B = 5 V 9 Ω Vref_A = VEN = 1.8 V; Vref_B = 5 V 4 VI = 0, IO = 32 mA , Vref_A = VEN = 2.5 V; Vref_B = 5 V 10 Ω VI = 1.8 V, IO = 15 mA, Vref_A = VEN = 3.3 V; Vref_B = 5 V 5 Ω VI = 1.0 V, IO = 10 mA, Vref_A = VEN = 1.8 V; Vref_B = 3.3 V 8 Ω VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 3.3 V 6 Ω VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 1.8 V 6 Ω (1) All typical values are at TA = 25°C. (2) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. (3) Enable pin test conditions are for the LSF0204. The enable pin test conditions for LSF0204D are oppositely set. (4) The actual supply current for LSF0204 is ICCA + ICCB; the leakage from Vref_B to Vref_A can be measured on Vref_A and Vref_B pin 7.6 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V) over recommended operating free-air temperature range, Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V, Vpu_2 = 1.8 V, RL = NA, VIH = 3.3 V, VIL = 0 VM = 1.15 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A tPLZ 13 18 12 16.5 11 15 ns tPZL 33 45 30 40 23 37 ns fMAX 50 100 100 MHz www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LSF0204 LSF0204D

7.7 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V) over recommended operating free-air temperature range Vrev-A = 1.2 V, Vrev-B = 3.3 V, VEN = 1.2 V, Vpu_1 = 3.3 V, Vpu_2 = 1.2 V, RL = NA, VIH = 3.3 V, VIL = 0 VM = 0.85 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A fMAX 50 100 100 MHz 7.8 Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V) over recommended operating free-air temperature range Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V, Vpu_2 = 1.8 V, RL = 500 Ω, VIH = 1.8 V,VIL = 0 VM = 0.9 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A tPLZ 13 18 12 16.5 11 15 ns tPZL 33 45 30 40 23 37 ns fMAX 50 100 100 MHz 7.9 Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V) over recommended operating free-air temperature range, Vrev-A = 1.2 V, Vrev-B = 1.8 V, VEN = 1.2 V, Vpu_1 = 1.8 V, Vpu_2 = 1.2 V, RL = 500 Ω, VIH = 1.2 V, VIL = 0 VM = 0.6 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A fMAX 50 100 100 MHz

7.10 Typical Characteristics

Time (ns) Voltage (V) 0 5 10 15 -0.5 1.5 2.5 3.5 0.5 Figure 7-1. Signal Integrity (1.8 V to 3.3 V Translation Up at 50 MHz) LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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8 Parameter Measurement Information

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR≤ ≤ ≤10 MHz, Z = 50 t 2 ns, tO r f Ω, 2□ns. C. The outputs are measured one at a time, with one transition per measurement. From Output Under Test CL (see Note A) LOAD CIRCUIT TRANSLATING UP TRANSLATING DOWN RL Translating up Translating down USAGE SWITCH VM VM 3.3 V VIL Input VM VM 5 V VOL Output VM VM 5 V VIL Input VM VM 2 V VOL Output VT Open Figure 8-1. Load Circuit for Outputs From Output Under Test 500 Ω S1 Vref_B Open 15 pF TEST S1 t /tPZL PLZ Vref_B Figure 8-2. Load Circuit for Enable/Disable Time Measurement www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LSF0204 LSF0204D

8.1 Load Circuit AC Waveform for Outputs

(An, Bn) Output (Bn, An) t 2.0 nsr t 2.0 nsf 90% 50% 10% VCCA GND VOH VOL tpHLtpLH 90% 50% 10% Figure 8-3. tPLH, tPHL VCCA GND VOH tpZLtpLZ t 2.0 nsr t 2.0 nsf 10% 50% Outputs enabled Outputs disabled Outputs enabled Output Enabled Control OE, OE Output (An or Bn) Low to off to Low 90% 50% 10% Figure 8-4. tPLZ, tPZL LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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9 Detailed Description

9.1 Overview

The LSF Family may be used in level translation applications for interfacing devices or systems operating at different interface voltages with one another. The LSF Family is ideal for use in applications where an open-drain driver is connected to the data I/Os. LSF can achieve 100 MHz with the appropriate pull-up resistors and layout. The LSF Family may also be used in applications where a push-pull driver is connected to the data I/Os.

9.2 Functional Block Diagram

Vref_A Vref_B EN 200 KΩ Level Converter www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LSF0204 LSF0204D

9.3 Feature Description

9.3.1 Support High Speed Translation, Greater than 100 MHz

Allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

9.3.2 Bidirectional Voltage Translation Without DIR Terminal

Minimizes system effort to develop voltage translation for bidirectional interface (PMBus, I2C, or SMbus). 9.3.3 5-V Tolerance on IO Port and 125°C Support The LSF family, with 5-V tolerance and 125°C support, is flexible and compliant with TTL levels in industrial and telecom applications.

9.3.4 Channel Specific Translation

The LSF family is able to set up different voltage translation levels on each channel.

9.3.5 Ioff, Partial Power Down Mode

When Vref_A, Vref_B = 0, all of data pins and EN pin are Hi-Z. EN logic circuit is supplied by Vref_A, once Vref_A power up first and all of data pins are unknown state until V ref_B and EN ready. No power sequence is required to enable LSF0204 and operate function normally.

9.4 Device Functional Modes

Table 9-1 lists the device functional modes of the LSF0204x family of devices. Table 9-1. Function Table INPUT EN(1) TERMINAL FUNCTION H An = Bn L Hi-Z (1) EN is controlled by Vref_A logic levels. LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

10.1 Application Information

LSF performs voltage translation for open-drain or push-pull interface. Table 10-1 provides some consumer/ telecom interfaces as reference in regards to the different channel numbers that are supported by the LSF family. Table 10-1. Voltage Translator for Consumer/Telecom Interface PART NAME CH# INTERFACE LSF0101 1 GPIO LSF0102 2 GPIO, MDIO, SMBus, PMBus, I2C LSF0204 4 GPIO, SPI. MDIO, SMBus, PMBus, I2C, UART, SVID LSF0108 8 GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, SPI

10.2 Typical Applications

10.2.1 I2C PMBus, SMBus, GPIO, Application

1.8 V enable signal SW SW SW SW LSF0204 Vpu_2 = 1.8 V Vrev_A = 1.8 V Vrev_B = 3.3 V Vpu_1 = 3.3 V Figure 10-1. Bidirectional Translation to Multiple Voltage Levels www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LSF0204 LSF0204D

10.2.1.1 Design Requirements

10.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines

The LSF family has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low. It is recommended to always enable LSF family for bidirectional application (I2C, SMBus, PMBus, or MDIO). Table 10-2. Application Operating Condition SYMBOL PARAMETER MIN TYP MAX UNIT Vref_A Reference voltage (A) 0.8 4.5 V Vref_B Reference voltage (B) Vref_A + 0.8 5.5 V VI(EN) (1) Input voltage on EN terminal 0 Vref_A V Vpu Pull-up supply voltage 0 Vref_B V (1) Refer VIH and VIL for VI(EN) Also Vref_B is recommended to be at 1.0 V higher than Vref_A for best signal integrity. The LSF Family is able to set different voltage translation level on each channel. Note Vref_A must be set as lowest voltage level.

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Bidirectional Translation

The controller output driver may be push-pull or open-drain (pull-up resistors may be required) and the peripheral device output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu). Note However, if either output is push-pull, data must be unidirectional or the outputs must be 3-state and be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no direction control is needed. In Figure 10-1, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage. When Vref_B is connected through to a 3.3 V Vpu power supply, and Vref_A is set 1.0V. The output of A3 and B4 has a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2, MDIO) has a maximum output voltage equal to Vpu. The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15 mA, to calculate the pull-up resistor value use Equation 1. Table 10-3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the LSF family device. LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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Table 10-3. Pullup Resistor Values PULLUP RESISTOR VALUE (Ω) VDPU 15 mA 10 mA 3 mA NOMINAL +10%(1) NOMINAL +10%(1) NOMINAL +10%(1)

5 V 310 341 465 512 1550 1705

3.3 V 197 217 295 325 983 1082

2.5 V 143 158 215 237 717 788

1.8 V 97 106 145 160 483 532

1.5 V 77 85 115 127 383 422

1.2 V 57 63 85 94 283 312

(1) +10% to compensate for VDD range and resistor tolerance

10.2.1.2.2 LS Family Bandwidth

The maximum frequency of the LSF family is dependent on the application. The device may operate at speeds of >100 MHz gave the correct conditions. The maximum frequency is dependent upon the loading of the application. The LSF family behaves like a standard switch where the bandwidth of the device is dictated by the on resistance and on capacitance of the device. Figure 10-2 shows a bandwidth measurement of the LSF family using a two-port network analyzer. – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0.1 1 10 100 1000 Gain (dB) Frequency (MHz) Figure 10-2. 3-dB Bandwidth The 3-dB point of the LSF family is ≈600 MHz; however, this measurement is an analog type of measurement. For digital applications, the signal should not degrade up to the fifth harmonic of the digital signal. The frequency bandwidth should be at least five times the maximum digital clock rate. This component of the signal is important in determining the overall shape of the digital signal. In the case of the LSF family, a digital clock frequency of greater than 100 MHz may be achieved. The LSF family does not provide any drive capability. Therefore higher frequency applications will require higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the LSF family is being driven by standard CMOS totem pole output driver. Best practice is to minimize the trace length from the LSF family on the sink side (1.8 V) to minimize signal degradation. All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than f knee are insignificant in determining the shape of the signal. www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LSF0204 LSF0204D

To calculate the maximum practical frequency component, or the knee frequency (f knee), use the following equations: fknee = 0.5/RT (10–80%) (2) fknee = 0.4/RT (20–80%) (3) For signals with rise time characteristics based on 10- to 90-percent thresholds, f knee is equal to 0.5 divided by the rise time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is very common in many of today's device specifications, fknee is equal to 0.4 divided by the rise time of the signal. Some guidelines to follow that will help maximize the performance of the device:

• Keep trace length to a minimum by placing the LSF family close to the I2C output of the processor.
• The trace length should be less than half the time of flight to reduce ringing and line reflections or non- monotonic behavior in the switching region.
• To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to be expected.

10.2.1.3 Application Curve

Time (ns) Voltage (V) 0 50 100 150 200 250 350 400 500 450 300 Figure 10-3. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz) LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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10.2.2 MDIO Application

1.0 V enable signal SW SW SW SW LSF0204 Vpu_2 = 1.0 V Vrev_A = 1.0 V Vrev_B = 3.3 V Vpu_1 = 3.3 V Figure 10-4. Typical Application Circuit (MDIO/Bidirectional Interface)

10.2.2.1 Design Requirements

Refer to Design Requirements.

10.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure

10.2.2.3 Application Curve

Input (3.3V) Output (1.0V) Figure 10-5. Captured Waveform From Above MDIO Setup www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LSF0204 LSF0204D

10.2.3 Multiple Voltage Translation in Single Device, Application

1.8 V enable signal SW SW SW SW LSF0204 Vpu_2 = 1.8 V Vrev_A = 1.8 V Vrev_B = 3.3 V Vpu_1 = 3.3 V Vcc GPIO GPIO Vpu = 1.0 V Rpu

10.2.3.1 Design Requirements

Refer to Design Requirements.

10.2.3.2 Detailed Design Procedure

Refer to Detailed Design Procedure

10.2.3.3 Application Curve

Time (ns) Voltage (V) -0.5 0.5 1.5 2.5 3.5 1.92E+12.16E+1 Figure 10-6. Translation Down (3.3 V to 1.8 V) at 150 MHz LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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11 Power Supply Recommendations

reference voltage guidelines.

12 Layout

12.1 Layout Guidelines

The signal integrity is highly related with pull-up resistor and PCB capacitance condition because LSF Family is switch-type level translator

• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
• Place LSF close to high voltage side.
• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

12.2 Layout Example

Vref_A EN Vref_B LSF0102 Short Signal Trace as possible Minimize Stub as possible 4 5 Figure 12-1. Short Trace Layout SDIO Connector (3.3V IO) SD Controller (1.8V IO) LSF0108 SDIO level translator Device PCB TP1 TP2 Figure 12-2. Device Placement www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LSF0204 LSF0204D

Time (ns) Voltage (V) 2.5E+0 5E+0 7.5E+0 1E+1 2E+1 2.25E+12.5E+1 -5E-1 5E-1 1E+0 1.5E+0 2E+0 2.5E+0 3E+0 3.5E+0 Figure 12-3. Waveform From TP1 (Pullup Resistor: 160-Ω and 50-pF Capacitance 3.3 to 1.8 V at 100 MHz) Output Input Time (ns) Voltage (V) -0.5 0.5 1.5 2.5 3.5 2.7E+1 3E+1 Figure 12-4. Waveform From TP2 (Pullup Resistor: 160-Ω and 50-pF Capacitance 1.8 to 3.3 V at 100 MHz) LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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13 Device and Documentation Support

13.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LSF0204 LSF0204D

www.ti.com PACKAGE OUTLINE C0.5 MAX 0.19 0.15 1.5 TYP

1 TYP

0.5 TYP

0.5 TYP

12X 0.25 0.21 B E A D DSBGA - 0.5 mm max heightYZP0012-C01 DIE SIZE BALL GRID ARRAY 4224761/A 01/2019 D: Max = 1.972 mm, Min = 1.912 mm E: Max = 1.472 mm, Min = 1.412 mm NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. LSF0204/LSF0204D BALL A3 INDEX AREA SEATING PLANE BALL TYP 0.05 C 1 2 3

0.015 C A B

D C B A SCALE 8.000 LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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www.ti.com EXAMPLE BOARD LAYOUT 12X ( 0.225) (0.5) TYP (0.5) TYP ( 0.225) METAL

0.05 MAX

( 0.225) SOLDER MASK OPENING

0.05 MIN

DSBGA - 0.5 mm max heightYZP0012-C01 DIE SIZE BALL GRID ARRAY 4224761/A 01/2019 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). SYMM LSF0204/LSF0204D SYMM LAND PATTERN EXAMPLE SCALE:30X D C 2 3 A B NON-SOLDER MASK DEFINED (PREFERRED) NOT TO SCALE SOLDER MASK DETAILS SOLDER MASK DEFINED www.ti.com LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LSF0204 LSF0204D

www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP METAL TYP DSBGA - 0.5 mm max heightYZP0012-C01 DIE SIZE BALL GRID ARRAY 4224761/A 01/2019 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. D C 1 2 3 A B SYMM LSF0204/LSF0204D SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X LSF0204, LSF0204D SLVSCP5H – JULY 2014 – REVISED APRIL 2021 www.ti.com

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Product Folder Links: LSF0204 LSF0204D

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LSF0204DPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LSF204D LSF0204DPWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LSF204D LSF0204DRGYR Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 LSF24D LSF0204DRGYR.B Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 LSF24D LSF0204DRGYRG4 Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 LSF24D LSF0204DRGYRG4.B Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 LSF24D LSF0204DRUTR Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SIO LSF0204DRUTR.B Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SIO LSF0204DRUTRG4 Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SIO LSF0204DRUTRG4.B Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SIO LSF0204DYZPR Active Production DSBGA (YZP) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 G6 LSF0204DYZPR.B Active Production DSBGA (YZP) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 G6 LSF0204PWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LSF204 LSF0204PWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LSF204 LSF0204RGYR Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LSF24 LSF0204RGYR.B Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LSF24 LSF0204RGYRG4 Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LSF24 LSF0204RGYRG4.B Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LSF24 LSF0204RUTR Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SIN LSF0204RUTR.B Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SIN LSF0204RUTRG4 Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SIN LSF0204RUTRG4.B Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SIN LSF0204YZPR Active Production DSBGA (YZP) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 G5 LSF0204YZPR.B Active Production DSBGA (YZP) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 G5 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. Addendum-Page 1

www.ti.com 7-Oct-2025 (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LSF0204 :

• Automotive : LSF0204-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LSF0204DPWR TSSOP PW 14 2000 364.0 364.0 27.0 LSF0204DRGYR VQFN RGY 14 3000 346.0 346.0 33.0 LSF0204DRGYRG4 VQFN RGY 14 3000 346.0 346.0 33.0 LSF0204DRUTR UQFN RUT 12 3000 184.0 184.0 19.0 LSF0204DRUTRG4 UQFN RUT 12 3000 184.0 184.0 19.0 LSF0204DYZPR DSBGA YZP 12 3000 182.0 182.0 20.0 LSF0204PWR TSSOP PW 14 2000 364.0 364.0 27.0 LSF0204RGYR VQFN RGY 14 3000 346.0 346.0 33.0 LSF0204RGYRG4 VQFN RGY 14 3000 346.0 346.0 33.0 LSF0204RUTR UQFN RUT 12 3000 184.0 184.0 19.0 LSF0204RUTRG4 UQFN RUT 12 3000 184.0 184.0 19.0 LSF0204YZPR DSBGA YZP 12 3000 182.0 182.0 20.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGY 14 PLASTIC QUAD FLATPACK - NO LEAD3.5 x 3.5, 0.5 mm pitch 4231541/A

www.ti.com PACKAGE OUTLINE C 14X 0.30 0.18 14X 0.5 0.3

1 MAX

0.05 0.00 8X 0.5 2.05 0.1 2X 1.5 A 3.65 3.35 B 3.65 3.35 (0.2) TYP VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 PIN 1 INDEX AREA 0.08 SEATING PLANE 1 14 (OPTIONAL) PIN 1 ID 0.05 7 8 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

(3.3) (3.3) 8X (0.5) 14X (0.6) 14X (0.24) ( 2.05) (0.775) (0.775) 2X (1.5) ( ) VIA TYP 0.2 (R ) TYP0.05 VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 SYMM1 14 SYMM LAND PATTERN EXAMPLE SCALE:20X 7 8 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 14X (0.24) 14X (0.6) (3.3) (3.3) 8X (0.5) 4X ( 0.92) (0.56) (0.56) 2X (1.5) (R ) TYP0.05 VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED SOLDER COVERAGE BY AREA SCALE:20X SYMM 1 14 7 8

www.ti.com PACKAGE OUTLINE C 12X 0.25 0.15 12X 0.6 0.4 1.6 10X 0.4

0.55 MAX

0.05 0.00 B 1.8 1.6 A 2.1 1.9 0.6 0.4 0.25 0.15 (0.15) (0.15) TYP 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.08 C (OPTIONAL) PIN 1 ID

0.1 C B A

0.05 C SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 6.800 OPTIONAL TERMINAL & PIN 1 ID PIN 1 ID

www.ti.com EXAMPLE BOARD LAYOUT 12X (0.2) (1.4) 8X (0.4) (1.7) 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE:30X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 12X (0.7) 12X (0.2) 8X (0.4) (1.7) (1.4) (R0.05) TYP 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 30X

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