LSF0108PWR

LSF0101 TI1 | Alldatasheet

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Vref_A EN Vref_B 6-Pin SON (Top View) 3 4 A1A2A3A4A5A6A7 B1B2B3B4B5B6B7 Vref_A Vref_B EN GND 23456789 1 1 12 13 14 15 16 17 18 19 LSF0108LSF0102 GND EN Vref_A Vref_B 8-Pin X2SON (Top View) Vref_A A2 B2 A1 B1 Vref_B GND EN 8-Pin DSBGA (Bottom View) 4 5 8D1 20-Pin VQFN (Top View) Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LSF0101,LSF0102,LSF0108 SDLS966G –DECEMBER 2013–REVISED FEBRUAURY 2016 LSF010x1/2/8ChannelBidirectionalMulti-VoltageLevelTranslatorforOpen-Drainand Push-PullApplication

1 Features

1• Provides Bidirectional Voltage Translation With No Direction Pin

• Supports Up to 100 MHz Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz Up/Down Translation at 50 pF Cap Load
• Supports Hot Insertion
• Allow Bidirectional Voltage Level Translation Between – 2.5 V ↔ 3.3/5 V – 3.3 V ↔ 5 V
• Low Standby Current
• 5 V Tolerance I/O Port to Support TTL
• Low Ron Provides Less Signal Distortion
• High-Impedance I/O pins For EN = Low
• Flow-Through Pinout for Ease PCB Trace Routing
• Latch-Up Performance Exceeds 100 mA Per JESD 17
• –40°C to 125°C Operating Temperature Range
• ESD Performance Tested Per JESD 22 – 2000 V Human-Body Model (A114-B, Class II) – 200 V Machine Model (A115-A) – 1000 V Charged-Device Model (C101)

2 Applications

• GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and Other Interfaces in Telecom Infrastructure
• Industrial
• Automotive
• Personal Computing

3 Description

LSF family supports up to 100 MHz up translation and greater than 100 MHz down translation at ≤ 30pF cap load and up to 40 MHz up/down translation at 50 pF cap load which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO). The LSF family has bidirectional voltage translation without the need for DIR pin which minimizes system effort (for PMBus, I2C, or SMbus). LSF family supports 5 V tolerance on IO port which makes it compatible with TTL levels in industrial and telecom applications. The LSF family is able to set up different voltage translation levels on each channel which makes it very flexible. Device Information(1) PART NUMBER PACKAGE(PINS) BODY SIZE (NOM) LSF0101 SON (6) 1.45 mm × 1.00 mm LSF0102 X2SON (8) 1.40 mm × 1.00 mm DSBGA (8) 1.90 mm × 1.00 mm SM8 (8) 2.80 mm × 2.95 mm VSSOP (8) 2.30 mm × 2.00 mm LSF0108 VQFN (20) 4.50 mm × 2.50 mm TSSOP (20) 4.40 mm × 6.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.

LSF0101,LSF0102,LSF0108 SDLS966G –DECEMBER 2013–REVISED FEBRUAURY 2016 www.ti.com Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Table of Contents

6.7 LSF0101/02 AC Performance (Translating Down)

6.8 LSF0108 AC Performance (Translating Down)

6.9 LSF0101/02 AC Performance (Translating Down)

6.10 LSF0108 AC Performance (Translating Down)

6.11 LSF0101/02 AC Performance (Translating Up)

6.12 LSF0108 AC Performance (Translating Up)

6.13 LSF0101/02 AC Performance (Translating Up)

6.14 LSF0108 AC Performance (Translating Up)

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (October 2015) to Revision G Page Changes from Revision E (July 2015) to Revision F Page

• Changed Features from "Supports High Speed Translation, Greater Than 100 MHz" to "Supports Up to 100 MHz Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz Up/Down Changes from Revision D (October 2014) to Revision E Page Changes from Revision C (May 2014) to Revision D Page

Vref_A EN Vref_B 3 4 Vref_A A2 B2 A1 B1 Vref_B GND EN EN Vref_B GND Vref_A GND EN Vref_A Vref_B 4 5 LSF0101,LSF0102,LSF0108 www.ti.com SDLS966G –DECEMBER 2013–REVISED FEBRUAURY 2016 Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated Changes from Revision B (May 2014) to Revision C Page Changes from Revision A (January 2014) to Revision B Page Changes from Original (December 2013) to Revision A Page

5 Pin Configuration and Functions

LSF0102 DCT or DCU Package 8-Pin SM8 or VSSOP Top View 8-Pin X2SON Top View 8-Pin DSBGA Bottom View 6-Pin SON Top View

Vref_A Vref_B ENGND 10 1 1 201 Vref_A Vref_B ENGND 10 1 1 LSF0101,LSF0102,LSF0108 SDLS966G –DECEMBER 2013–REVISED FEBRUAURY 2016 www.ti.com Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated 20-Pin TSSOP Top View 20-Pin VQFN Top View Pin Functions PIN

DESCRIPTION

NAME DCT, DCU, DQE, YZT NO. DRY NO. PW or RKS NO. An 3, 4 3 3 to 10 Data port Bn 6, 5 4 18 to 11 EN 8 6 20 Switch enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ). GND 1 1 1 Ground Vref_A 2 2 2 Reference supply voltage; see Application and Implementation. Vref_B 7 5 19 Reference supply voltage; see Application and Implementation.

LSF0101,LSF0102,LSF0108 www.ti.com SDLS966G –DECEMBER 2013–REVISED FEBRUAURY 2016 Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7.

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature (unless otherwise noted) MIN MAX UNIT VI Input voltage(2) –0.5 7 V VI/O Input/output voltage(2) –0.5 7 V Continuous channel current 128 mA IIK Input clamp current VI < 0 –50 mA RθJA Package thermal impedance(3) DCT package 220 °C/W DCU package 227 Tstg Storage temperature range –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VI/O Input/output voltage 0 5 V Vref_A/B/EN Reference voltage 0 5 V IPASS Pass transistor current 64 mA TA Operating free-air temperature –40 125 °C

LSF0101,LSF0102,LSF0108 SDLS966G –DECEMBER 2013–REVISED FEBRUAURY 2016 www.ti.com Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information: LSF0101, LSF0108

THERMAL METRIC(1) LSF0101 LSF0108 LSF0108 UNITDRY (SON) RKS (VQFN) PW (TSSOP)

6 PINS 20 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance 407.0 49.3 106.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 285.2 45.9 41.0 °C/W RθJB Junction-to-board thermal resistance 271.6 20.6 57.6 °C/W ψJT Junction-to-top characterization parameter 113.5 2.5 4.2 °C/W ψJB Junction-to-board characterization parameter 271.0 20.6 47.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 3.4 n/a °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information: LSF0102

THERMAL METRIC(1) LSF0102 LSF0102 LSF0102 LSF0102 UNITDCU (US8) DCT (SM8) DQE (X2SON) YZT (DSBGA)

8 PINS 8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 210.1 189.6 246.5 125.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 89.1 119.6 149.1 1.0 °C/W RθJB Junction-to-board thermal resistance 88.8 102.1 100.0 62.7 °C/W ψJT Junction-to-top characterization parameter 8.3 44.5 17.1 3.4 °C/W ψJB Junction-to-board characterization parameter 88.4 101.0 99.8 62.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W (1) All typical values are at TA = 25°C. (2) Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) pins.

6.6 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIK II = –18 mA, VEN = 0 –1.2 V IIH VI = 5 V VEN = 0 5.0 µA ICC Vref_B = VEN = 5.5 V, Vref_A = 4.5 V or 1 V, IO = 0, VI = VCC or GND 1 µA CI(ref_A/B/EN) VI = 3 V or 0 11 pF Cio(off) VO = 3 V or 0, VEN = 0 4.0 6.0 pF Cio(on) VO = 3 V or 0, VEN = 3 V 10.5 12.5 pF ron (2) VI = 0, IO = 64 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 8.0 ΩVref_A = 1.8 V; Vref_B = VEN = 5 V 9.0 Vref_A = 1.0 V; Vref_B = VEN = 5 V 10 VI = 0, IO = 32 mA Vref_A = 1.8 V; Vref_B = VEN = 5 V 10 Ω Vref_A = 2.5 V; Vref_B = VEN = 5 V 15 VI = 1.8 V, IO = 15 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 9.0 Ω VI = 1.0 V, IO = 10 mA Vref_A = 1.8 V; Vref_B = VEN = 3.3 V 18 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 3.3 V 20 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 1.8 V 30 Ω

LSF0101,LSF0102,LSF0108 www.ti.com SDLS966G –DECEMBER 2013–REVISED FEBRUAURY 2016 Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated 6.7 LSF0101/02 AC Performance (Translating Down) Switching Characteristics , VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.1 0.7 0.3 ns tPHL 1.2 0.8 0.4 6.8 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.9 1.4 0.75 ns tPHL 2 1.5 0.85 6.9 LSF0101/02 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.2 0.8 0.35 ns tPHL 1.3 1 0.5 6.10 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 2 1.45 0.8 ns tPHL 2.1 1.55 0.9 6.11 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL = 300 (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1 0.8 0.4 ns tPHL 1 0.9 0.4 6.12 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL = 300 (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 2.1 1.55 0.9 ns tPHL 2.2 1.65 1

6.15 Typical Characteristics

Figure 1. Signal Integrity (1.8 to 3.3 V Translation Up at 50 MHz)

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR≤ ≤ ≤10 MHz, Z = 50 t 2 ns, tO r f Ω, 2□ns. C. The outputs are measured one at a time, with one transition per measurement.

7 Parameter Measurement Information

Figure 2. Load Circuit for Outputs

8 Detailed Description

8.1 Overview

driver is connected to the data I/Os. With appropriate pull-up resistors and layout, LSF can achieve 100 MHz. The LSF family can also be used in applications where a push-pull driver is connected to the data I/Os.

8.2 Functional Block Diagrams

Figure 3. LSF0101 Functional Block Diagram Figure 4. LSF0102 Functional Block Diagram

Figure 5. LSF0108 Functional Block Diagram

8.3 Feature Description

greater than 100 Mbps for open-drain systems using a 30-pF capacitance and 250-Ω pullup resistor. and lower voltages selected by the user without the need for directional control. state during power-up or power-down, EN must be LOW.

8.4 Device Functional Modes

Table 1 expresses the functional modes of the LSF devices. higher than Vref_A for best translator. Table 1. Function Table

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Table 2. Voltage Translator for Consumer/Telecom Interface

9.2 Typical Application

9.2.1 I2C PMBus, SMBus, GPIO

Figure 6. Bidirectional Translation to Multiple Voltage Levels

9.2.1.1 Design Requirements

9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines

the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low. It is recommended to always enable LSF family for bidirectional application (I2C, SMBus, PMBus, or MDIO).

(1) Vref_A have to be the lowest voltage level across all of inputs and outputs. Table 3. Application Operating Condition

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Bidirectional Translation

output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu). controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no direction control is needed. In Figure 6, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage. MDIO) has a maximum output voltage equal to Vpu.

9.2.1.2.2 Pull-up Resistor Sizing

Table 4. Pull-up Resistor Values(1)(2)

5 V 310 341 465 512 1550 1705

3.3 V 197 217 295 325 983 1082

2.5 V 143 158 215 237 717 788

1.8 V 97 106 145 160 483 532

1.5 V 77 85 115 127 383 422

1.2 V 57 63 85 94 283 312

9.2.1.2.3 LSF Family Bandwidth

on resistance and on capacitance of the device. Figure 7 shows a bandwidth measurement of the LSF family using a two-port network analyzer. Figure 7. 3-dB Bandwidth The 3-dB point of the LSF family is ≈ 600 MHz; however, this measurement is an analog type of measurement. frequency of greater than 100 MHz can be achieved. family on the sink side (1.8 V) to minimize signal degradation. common in many of today's device specifications, ƒknee is equal to 0.4 divided by the rise time of the signal.

• Keep trace length to a minimum by placing the LSF family close to the I2C output of the processor.
• The trace length should be less than half the time of flight to reduce ringing and line reflections or non- monotonic behavior in the switching region.
• To reduce overshoots, a pull-up resistor can be added on the 1.8 V side; be aware that a slower fall time is to be expected.

9.2.1.3 Application Curve

Figure 8. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz)

9.2.2 MDIO

Figure 9. Typical Application Circuit (MDIO/Bidirectional Interface)

9.2.2.1 Design Requirements

Refer to Design Requirements.

9.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure.

9.2.2.3 Application Curve

Figure 10. Captured Waveform From Above MDIO Setup

Vref_A Vref_B EN LSF0108 200KΩ Vcc Vcc Rpu GPIO GPIO GPIO GPIO Vref(A) = 1.8V Vpu= 5.0V RpuRpu Vpu=3.3V GPIO GPIO 1.8V SCL SDA GPIO GPIO MDIO MDC SCL SDA MDIO MDC RpuRpu SW SW SW SW SW SW SW SW Vcc LSF0101,LSF0102,LSF0108 www.ti.com SDLS966G –DECEMBER 2013–REVISED FEBRUAURY 2016 Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated

9.2.3 Multiple Voltage Translation in Single Device

9.2.3.1 Design Requirements

Refer to Design Requirements.

9.2.3.2 Detailed Design Procedure

Refer to Detailed Design Procedure.

9.2.3.3 Application Curve

Figure 11. Translation Down (3.3 to 1.8 V) at 150 MHz

10 Power Supply Recommendations

please refer to the Enable, Disable, and Reference Voltage Guidelines.

11 Layout

11.1 Layout Guidelines

resistor and PCB capacitance condition.

• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
• Place LSF close to high voltage side.
• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

11.2 Layout Example

Figure 12. Short Trace Layout Figure 13. Device Placement

12 Device and Documentation Support

12.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 5. Related Links

12.2 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 4-Feb-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LSF0101DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VD LSF0102DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NG2 Y LSF0102DCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (G2 ~ NG2P ~ NG2S) NY LSF0102DQER ACTIVE X2SON DQE 8 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 RV LSF0102YZTR ACTIVE DSBGA YZT 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 RV LSF0108PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LSF0108 LSF0108RKSR ACTIVE VQFN RKS 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LSF0108 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 4-Feb-2016 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LSF0101DRYR SON DRY 6 5000 184.0 184.0 19.0 LSF0102DCTR SM8 DCT 8 3000 182.0 182.0 20.0 LSF0102DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 LSF0102DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 LSF0102DCUR VSSOP DCU 8 3000 182.0 182.0 20.0 LSF0102DQER X2SON DQE 8 5000 184.0 184.0 19.0 LSF0102YZTR DSBGA YZT 8 3000 182.0 182.0 20.0 LSF0108PWR TSSOP PW 20 2000 364.0 364.0 27.0 LSF0108RKSR VQFN RKS 20 3000 202.0 201.0 28.0 PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2016 Pack Materials-Page 2

MPDS049B – MAY 1999 – REVISED OCTOBER 2002 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 0,60 0,20 0,25 0° – 8° 0,15 NOM Gage Plane 4188781/C 09/02 4,25 0,30 0,15 2,90 3,752,70 3,15 2,75 0,10 0,00 1,30 MAX Seating Plane 0,10 M0,130,65 PIN 1 INDEX AREA NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion D. Falls within JEDEC MO-187 variation DA.

D: Max = E: Max = 1.918 mm, Min = 0.918 mm, Min = 1.858 mm 0.858 mm

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