LSF0108DGSR

LSF0108 TI | Alldatasheet

Document overview

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Technical content

LSF010x 1/2/8 Channel Auto-Bidirectional Multi-Voltage Level Translator for Open- Drain and Push-Pull Applications

1 Features

• Provides bidirectional voltage translation with no direction pin
• Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30 pF cap load and up To 40-MHz up/down translation at 50 pF cap load
• Allows bidirectional voltage-level translation between – 2.5 V ↔ 3.3/5 V – 3.3 V ↔ 5 V
• Low standby current
• 5-V tolerance I/O port to support TTL
• Low RON provides less signal distortion
• High-impedance I/O pins for EN = Low
• Flow-through pinout for easy PCB trace routing
• Latch-up performance >100 mA per JESD 17
• –40°C to 125°C operating temperature range

2 Applications

• GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and other interfaces in telecom infrastructure
• Enterprise systems
• Communications equipment
• Personal electronics
• Industrial applications

3 Description

The LSF family of devices supports bidirectional voltage translation without the need for DIR pin which minimizes system effort (for PMBus, I 2C, SMBus, and so forth). The LSF family of devices supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30 pF cap load and up to 40- MHz up/down translation at 50 pF cap load which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO). LSF family supports 5-V tolerance on I/O port which makes it compatible with TTL levels in industrial and telecom applications. The LSF family is able to set up different voltage translation levels on each channel which makes it very flexible.

Package Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM) LSF0101 SON (DRY, 6) 1.45 mm × 1.00 mm X2SON (DTQ, 6) 1.00 mm x 0.80 mm LSF0102 X2SON (DQE, 8) 1.40 mm × 1.00 mm DSBGA (YZT, 8) 1.90 mm × 1.00 mm SM8 (DCT, 8) 2.80 mm × 2.95 mm VSSOP (DCU, 8) 2.30 mm × 2.00 mm SOT-23 (DDF, 8) 1.60 mm x 2.90 mm LSF0108 VQFN (RKS, 20) 4.50 mm × 2.50 mm TSSOP (PW, 20) 4.40 mm × 6.50 mm VSSOP (DGS, 20) 3.00 mm x 5.10 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Vref_A Vref_B 2 19 20 EN GND SW SW SW SW SW SW SW SW Functional Block Diagram LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

6.8 LSF0101/02 AC Performance (Translating

6.9 LSF0108 AC Performance (Translating Down)

6.10 LSF0101/02 AC Performance (Translating

6.11 LSF0108 AC Performance (Translating Down)

6.12 LSF0101/02 AC Performance (Translating Up)

6.13 LSF0108 AC Performance (Translating Up)

6.14 LSF0101/02 AC Performance (Translating Up)

6.15 LSF0108 AC Performance (Translating Up)

12.2 Receiving Notification of Documentation Updates..24

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (May 2021) to Revision L (November 2022) Page Changes from Revision J (April 2020) to Revision K (May 2021) Page LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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Changes from Revision I (June 2019) to Revision J (April 2020) Page Changes from Revision H (June 2019) to Revision I (July 2019) Page Changes from Revision G (February 2016) to Revision H (June 2019) Page Changes from Revision F (October 2015) to Revision G (October 2015) Page Changes from Revision E (July 2015) to Revision F (October 2015) Page

• Changed Features from "Supports High Speed Translation, Greater Than 100 MHz" to "Supports Up to 100 MHz Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz Changes from Revision D (October 2014) to Revision E (July 2015) Page Changes from Revision C (May 2014) to Revision D (August 2014) Page Changes from Revision B (May 2014) to Revision C (May 2014) Page Changes from Revision A (January 2014) to Revision B (February 2014) Page Changes from Revision * (December 2013) to Revision A (January 2014) Page www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LSF0108

5 Pin Configuration and Functions

Pinout drawings are not to scale Figure 5-1. LSF0101 DRY Package, 6-Pin SON (Transparent Top View) Figure 5-2. LSF0101 DTQ Package, 6-Pin X2SON (Transparent Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME DRY, DTQ NO. An 3 I/O Auto-Bidirectional Data port Bn 4 I/O EN 6 I Enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ). See Using the Enable Pin with the LSF Family GND 1 — Ground Vref_A 2 — Reference supply voltage. For proper device biasing, see Section 9 and Understanding the Bias Circuit for the LSF Family.Vref_B 5 — (1) I= input, O = output Pinout drawings are not to scale Figure 5-3. LSF0102 DCT, DCU or DDF Package, 8-Pin SM8, VSSOP, SOT-23 (Top View) Figure 5-4. LSF0102 DQE Package, 8-Pin X2SON (Transparent Top View) Table 5-2. Pin Functions PIN TYPE(1) DESCRIPTION NAME DCT, DCU, DDF, DQE NO. An 3, 4 I/O Auto-Bidirectional Data port Bn 6, 5 I/O EN 8 I Enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ). See Using the Enable Pin with the LSF Family GND 1 — Ground Vref_A 2 — Reference supply voltage. For proper device biasing, see Section 9 and Understanding the Bias Circuit for the LSF Family.Vref_B 7 — (1) I= input, O = output LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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D C B A Not to scale A2 B2 A1 B1 Vref_A Vref_B GND EN Figure 5-5. LSF0102 YZT Package, 8-Pin DSBGA (Bottom View) Legend Input Input or Output Ground Table 5-3. Pin Functions PIN TYPE(1) DESCRIPTION YZT NO. NAME C1 A1 I/O Auto-Bidirectional Data port D1 A2 I/O C2 B1 I/O D2 B2 I/O B1 Vref_A — Reference supply voltage. For proper device biasing, see Section 9 and Understanding the Bias Circuit for the LSF Family.B2 Vref_B — A2 EN I Enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ). See Using the Enable Pin with the LSF Family A1 GND — Ground (1) I= input, O = output www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LSF0108

Pinout drawings are not to scale Figure 5-6. LSF0108 PW or DGS Package, 20-Pin TSSOP or VSSOP (Top View) Figure 5-7. LSF0108 RKS Package, 20-Pin VQFN (Transparent Top View) Table 5-4. Pin Functions PIN TYPE(1) DESCRIPTION NAME PW, DGS RKS NO. An 3 to 10 I/O Auto-Bidirectional Data port Bn 18 to 11 I/O EN 20 I Enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ). See Using the Enable Pin with the LSF Family GND 1 — Ground Vref_A 2 — Reference supply voltage. For proper device biasing, see Section 9 and Understanding the Bias Circuit for the LSF Family.Vref_B 19 — (1) I= input, O = output LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1) MIN MAX UNIT VI Input voltage(2) –0.5 7 V VI/O Input/output voltage(2) –0.5 7 V Continuous channel current 128 mA IIK Input clamp current VI < 0 –50 mA TJ Junction Temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VI/O Input/output voltage 0 5 V Vref_A/B/EN Reference voltage 0 5 V IPASS Pass transistor current 64 mA TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LSF0101 UNITDTQ (X2SON) DRY (SON)

6 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 294.4 407.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 188.9 285.2 °C/W RθJB Junction-to-board thermal resistance 216.8 271.6 °C/W ψJT Junction-to-top characterization parameter 26.5 113.5 °C/W ψJB Junction-to-board characterization parameter 216.0 271.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LSF0108

6.5 Thermal Information

THERMAL METRIC(1) LSF0102 UNITDCU (US8) DCT (SM8) DQE (X2SON) YZT (DSBGA) DDF (SOT-23)

8 PINS 8 PINS 8 PINS 8 PINS 8 PINS

ψJB Junction-to-board characterization RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.6 Thermal Information

THERMAL METRIC(1) LSF0108 UNITRKS (VQFN) PW (TSSOP) DGS (VSSOP)

20 PINS 20 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance 49.3 106.6 123.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 45.9 41.0 62.2 °C/W RθJB Junction-to-board thermal resistance 20.6 57.6 77.4 °C/W ψJT Junction-to-top characterization parameter 2.5 4.2 8.8 °C/W ψJB Junction-to-board characterization parameter 20.6 47.0 77.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.4 n/a n/a °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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6.7 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIK II = –18 mA, VEN = 0 –1.2 V IIH VI = 5 V VEN = 0 5.0 µA ICC Vref_B = VEN = 5.5 V, Vref_A = 4.5 V, IO = 0, VI = VCC or GND 6 µA CI(ref_A/B/EN) VI = 3 V or 0 11 pF Cio(off) VO = 3 V or 0, VEN = 0 4.0 6.0 pF Cio(on) VO = 3 V or 0, VEN = 3 V 10.5 12.5 pF ron (2) VI = 0, IO = 64 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 8.0 ΩVref_A = 1.8 V; Vref_B = VEN = 5 V 9.0 Vref_A = 1.0 V; Vref_B = VEN = 5 V 10 VI = 0, IO = 32 mA Vref_A = 1.8 V; Vref_B = VEN = 5 V 10 Ω Vref_A = 2.5 V; Vref_B = VEN = 5 V 15 VI = 1.8 V, IO = 15 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 9.0 Ω VI = 1.0 V, IO = 10 mA Vref_A = 1.8 V; Vref_B = VEN = 3.3 V 18 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 3.3 V 20 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 1.8 V 30 Ω (1) All typical values are at TA = 25°C. (2) Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) pins. 6.8 LSF0101/02 AC Performance (Translating Down) Switching Characteristics , VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.1 0.7 0.3 ns tPHL 1.2 0.8 0.4 6.9 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.9 1.4 0.75 ns tPHL 2 1.5 0.85 6.10 LSF0101/02 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.2 0.8 0.35 ns tPHL 1.3 1 0.5 www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LSF0108

6.11 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 2 1.45 0.8 ns tPHL 2.1 1.55 0.9 6.12 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL = 300 (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1 0.8 0.4 ns tPHL 1 0.9 0.4 6.13 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL = 300 (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 2.1 1.55 0.9 ns tPHL 2.2 1.65 1 6.14 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL = 300 (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.1 0.9 0.45 ns tPHL 1.3 1.1 0.6 6.15 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL = 300 (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.8 1.35 0.8 ns tPHL 1.9 1.45 0.9 LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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6.16 Typical Characteristics

Figure 6-1. Signal Integrity (1.8 to 3.3 V Up Translation at 50 MHz) www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LSF0108

7 Parameter Measurement Information

Figure 7-1. Load Circuit for Outputs LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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8 Detailed Description

8.1 Overview

The LSF family can be used in level-translation applications for interfacing devices or systems operating with one another that operate at different interface voltages. The LSF family is ideal for use in applications where an open-drain driver is connected to the data I/Os. With appropriate pull-up resistors and layout, LSF can achieve 100 MHz. The LSF family can also be used in applications where a push-pull driver is connected to the data I/Os. For an overview of device setup and operation, see The Logic Minute training series on Understanding the LSF Family of Bidirectional, Multi-Voltage Level Translators.

8.2 Functional Block Diagram

Vref_A Vref_B 2 19 EN GND SW SW SW SW SW SW SW SW

8.3 Feature Description

8.3.1 Auto Bidirectional Voltage Translation

All devices in the LSF family are auto bidirectional voltage level translators that are operational from 0.95 to 4.5 V on the Vref_A supply and from 1.8 to 5.5 V on the Vref_B supply. This allows bidirectional voltage translation between 0.95 V and 5.5 V without the need for a direction pin in open-drain or push-pull applications. The LSF family supports level translation applications with transmission speeds greater than 100 Mbps for open-drain systems using a 30-pF capacitance and 250- Ω pullup resistor. Both the output driver of the controller and the peripheral device output can be push-pull or open-drain (pull-up resistors may be required). In both up and down translation, the B-side is often referred to as the high side and refers to devices connected to the B ports. The A-side can be referred to as the low side. www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LSF0108

8.3.2 Output Enable

To enable the I/O pins, the EN input should be tied directly to Vref_B during operation and both pins must be pulled up to the HIGH side (Vpu or VCCB) through a pull-up resistor (typically 200 k Ω). To ensure the high impedance state during power-up, power-down, or during operation, the EN pin must be LOW. The EN pin should always be tied directly to the Vref_B pin and is recommended to be disabled by an open-drain driver without a pullup resistor. This allows Vref_B to regulate the EN input and bias the channels for proper translation. A filter capacitor on Vref_B is recommended for a stable supply at the device. 1.8 V Vref_A V CCB EN 200 kΩ Vref_B 3.3 V A1B1 0.1 μF Figure 8-1. Enable Pin Tied to Vref_B Directly and to VCCB Through a Pull-Up Resistor The supply voltage of open drain I/O devices can be completely different from the supplies used for the LSF and has no impact on the operation. For additional details on how to use the enable pin, see the Using the Enable Pin with the LSF Family video. Table 8-1. Enable Pin Function Table INPUT EN(1) PIN Data Port State Tied directly to Vref_B An = Bn L Hi-Z (1) EN is controlled by Vref_B logic levels.

8.4 Device Functional Modes

For each channel (n), when either the An or Bn port is LOW, the switch provides a low impedance path between the An and Bn ports; the corresponding Bn or An port will be pulled LOW. The low R ON of the switch allows connections to be made with minimal propagation delay and signal distortion. Table 8-1 provides a summary of device operation. For additional details on the functional operation of the LSF family of devices, see the Down Translation with the LSF Family and Up Translation with the LSF Family videos. Table 8-2. Device Functionality Signal Direction(1) Input State Switch State Functionality B to A (Down Translation) B = LOW ON (Low Impedance) A-side voltage is pulled low through the switch to the B-side voltage B = HIGH OFF (High Impedance) A-side voltage is clamped at Vref_A (2) A to B (Up Translation) A = LOW ON (Low Impedance) B-side voltage is pulled low through the switch to the A-side voltage A = HIGH OFF (High Impedance) B-side voltage is clamped at Vref_A and then pulled up to the Vpu# supply voltage (1) The downstream channel should not be actively driven through a low impedance driver, or else bus contention may occur. (2) The A-side can have a pullup to Vref_A for additional current drive capability or may also be pulled above Vref_A with a pullup resistor. Specifications in the Recommended Operating Conditions section should always be followed. LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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8.4.1 Up and Down Translation

Up Translation: When the signal is being driven from A to B and the An port is HIGH, the switch will be OFF and the Bn port will then be driven to a voltage higher than Vref_A by the pullup resistor that is connected to the pull-up supply voltage (Vpu#). This functionality allows seamless translation between higher and lower voltages selected by the user, without the need for directional control. Pull-up resistors are always required on the high side, and pull-ups are only required on the low side if the low side device's output is open drain or its input has a leakage greater than 1 µA. Vref_A VCCB EN 200 kΩ GND LSF0108 Vref_B 3.3 V Device 3.3 V RB1 0.1 μF RA1 1.8 V Device 1.8 V VCCA Figure 8-2. Up Translation Example Schematic with Push-Pull and Open Drain Configuration Up translation with the LSF requires attention to two important factors: maximum data rate and sink current. Maximum data rate is directly related to the rising edge of the output signal. Sink current depends on supply values and the chosen pull-up resistor values. Equation 1 below shows the maximum data rate formula and equation 2 presents the maximum sink current formula, both of which are estimations. A low RC value is needed to reach high speeds, which also require strong drivers. Please see the Up Translation with the LSF Family video for estimated data rate and sink current calculations based on circuit components. Down Translation: 3 × 2 R B 1 C B 1 = 1

6 R B 1 C B 1 bi ts

s ec o nd (1) I OL ≅ V C C A R A 1 + V C CB R B 1 A (2) When the signal is being driven HIGH from the Bn port to An port, the switch will be OFF, clamping the voltage on the An port to the voltage set by Vref_A. A pull-up resistor can be added on either side of the device. There are special circumstances that allow the removal of one or both of the pull-up resistors. If the signal is always going to be down translated from a push-pull transmitter, then the resistor on the B-side can be removed. If the leakage current into the receiver on the A-side is less than 1 µA, then the resistor on the A-side can also be removed. This arrangement with no external pull-up resistors can be used when down translating from a push-pull output to a low-leakage input. For an open drain transmitter, the pull-up resistor on the B-side is necessary because an open drain output can't drive high by itself. Refer to Table 8-2 for a summary of device operation. For additional details on the functional operation of the LSF family of devices, see the Up Translation with the LSF Family and Down Translation with the LSF Family videos. www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LSF0108

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The LSF devices are able to perform voltage translation for open-drain or push-pull interfaces. Table 9-1 provides common interfaces and the corresponding device recommendation from the LSF family which supports the corresponding bit count. Table 9-1. Voltage Translator for Common Interfaces Part Name Channel Number Interface LSF0101 1 GPIO LSF0102 2 GPIO, MDIO, SMBus, PMBus, and I2C LSF0108 8 GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, and SPI Please find below some important reminders regarding the LSF family of devices:

• LSF devices are switch-based, not buffer-based (please see the TXB family for buffer-based devices).
• Specific data rates cannot be calculated by using 1/Tpd.
• VCCB/VCCA are not the same as Vref_B or Vref_A: VCCB refers to the B-side supply voltage supplied to the LSF device, while Vref_B refers to the voltage at the Vref_B pin (pin 7 of Figure 9-1.) on the other side of the 200k resistor.

9.2 Typical Applications

9.2.1 Open-Drain Interface (I2C, PMBus, SMBus, and GPIO)

Vref_AVref_B27348EN651GNDA1A2B1B2LSF0108Rpu200 KΩONOffRpuRpuRpuVref(A) = 1.8 V Vpu = 3.3 V GND GND

3.3 V enable signal

Figure 9-1. Typical Application Circuit for Open-Drain Translation (MDIO Shown as an Example) LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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9.2.1.1 Design Requirements

9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines

When Vref_B is connected through a 200-k Ω resistor to a 3.3-V Vpu power supply and Vref_A is set 1.8 V, as shown in Figure 9-1, the A1 and A2 channels have a maximum output voltage equal to Vref_A, and the B1 and B2 channels have has a maximum output voltage equal to Vpu. The LSF family has an EN input that is used to disable the device by setting EN LOW, placing all I/Os in the high-impedance state. Since the LSF family of devices are switch-type voltage translators, the power consumption is very low. TI recommends always enabling the LSF family for bidirectional applications (I 2C, SMBus, PMBus, or MDIO). Table 9-2. Application Operating Condition PARAMETER MIN TYP MAX UNIT Vref_A(1) reference voltage (A) 0.95 5.0 V Vref_B reference voltage (B) Vref_A + 0.8 5.0 V VI(EN) input voltage on EN pin Vref_A + 0.8 5.0 V Vpu pull-up supply voltage 0 Vref_B V (1) Vref_A is required to be the lowest voltage level across all inputs and outputs. Note The 200 kΩ, pull-up resistor is required to allow Vref_B to regulate the EN input and properly bias the device for translation.

9.2.1.1.2 Bias Circuitry

For proper operation, VCCA must always be at least 0.8 V less than VCCB (VCCA + 0.8 ≦ VCCB). The 200 k Ω pull-up resistor is required to allow Vref_B to regulate the EN input and properly bias the device for translation. A 0.1 µF capacitor is recommended for providing a path from Vref_B to ground for high frequency noise. Vref_B and VI (EN) are recommended to be 1.0 V higher than Vref_A for best signal integrity. Attempting to drive the EN pin directly with a push-pull output device is a very common design error with the LSF01 series of devices. It is also very important to note that current does flow into the A-side voltage supply during normal operation. Not all voltage sources can sink current, so be sure that applicable designs can handle this current. For more design details, see the Understanding the Bias Circuit for the LSF Family video. 1.8 V Vref_A V CCB EN 200 kΩ Vref_B 3.3 V A1B1 0.1 µF Figure 9-2. Bias Circuitry Inside the LSF0108 Devices www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LSF0108

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Bidirectional Translation

For the bidirectional translation configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to Vref_B and both pins must be pulled up to the HIGH side Vpu through a pull-up resistor (typically 200 k Ω). This allows Vref_B to regulate the EN input and bias the channels for proper translation. A filter capacitor on Vref_B is recommended for a stable supply at the device. The controller output driver can be push-pull or open-drain (pull-up resistors may be required) and the peripheral device output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu). Note If either output is push-pull, data must be unidirectional or the outputs must be tri-state and be controlled by some direction-control mechanism to prevent HIGH-to-LOW bus contention in either direction. If both outputs are open-drain, no direction control is needed.

9.2.1.2.2 Pull-Up Resistor Sizing

The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about 15 mA. This ensures a voltage drop of 260 mV to 350 mV to have a valid LOW signal on the downstream channel. If the current through the pass transistor is higher than 15 mA, the voltage drop is also higher in the ON state. To set the current through each pass transistor at 15 mA, calculate the pull-up resistor value using the following equation: Rp u = Vpu − 0.35 V

0.015 A (3)

Table 9-3 summarizes resistor values, reference voltages, and currents at 8 mA, 5 mA, and 3 mA. The resistor value shown in the +10% column (or a larger value) should be used to ensure that the voltage drop across the transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the LSF family device. The device driving the low state at 0.175 V must sink current from one or more of the pull-up resistors and maintain VOL. A decrease in resistance will increase current, and thus result in increased VOL. Table 9-3. Pull-Up Resistor Values VDPU (1) (2) 8 mA 5 mA 3 mA NOMINAL (Ω) +10%(3) (Ω) NOMINAL (Ω) +10%(3) (Ω) NOMINAL (Ω) +10%(3) (Ω)

5 V 581 639 930 1023 1550 1705

3.3 V 369 406 590 649 983 1082

2.5 V 269 296 430 473 717 788

1.8 V 181 199 290 319 483 532

1.5 V 144 158 230 253 383 422

1.2 V 106 117 170 187 283 312

(1) Calculated for VOL = 0.35 V (2) Assumes output driver VOL = 0.175 V at stated current (3) +10% to compensate for VDD range and resistor tolerance LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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9.2.1.3 Application Curve

Figure 9-3. Open Drain Translation (1.8 V to 3.3 V at 2.5 MHz)

9.2.2 Mixed-Mode Voltage Translation

The supply voltage (V pu#) for each channel can be individually set with a pull-up resistor. Figure 9-4 shows an example of this mixed-mode multi-voltage translation. For additional details on multi-voltage translation, see the Multi-voltage Translation with the LSF Family video. With the Vref_B pulled up to 5 V and Vref_A connected to 1.8 V, all channels will be clamped to 1.8 V at which point a pullup can be used to define the high level voltage for a given channel.

• Push-Pull Down Translation (5 V to 1.8 V): Channel 1 is an example of this setup. When B1 is 5 V, A1 is clamped to 1.8 V, and when B1 is LOW, A1 is driven LOW through the switch.
• Push-Pull Up Translation (1.8 V to 5 V): Channel 2 is an example of this setup. When A2 is 1.8 V, the switch is high impedance and the B2 channel is pulled up to 5 V. When A2 is LOW, B2 is driven LOW through the switch.
• Push-Pull Down Translation (3.3 V to 1.8 V): Channels 3 and 4 are examples of this setup. When either B3 or B4 are driven to 3.3 V, A3 or A4 are clamped to 1.8 V, and when either B3 or B4 are LOW, A3 or A4 are driven LOW through the switch.
• Open-Drain Bidirectional Translation (3.3 V ↔ 1.8 V): Channels 5 through 8 are examples of this setup. These channels are for bidirectional operation for I2C and MDIO to translate between 1.8 V and 3.3 V with open-drain drivers. www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LSF0108

Figure 9-4. Multi-Voltage Translation with the LSF0108

9.2.3 Single Supply Translation

Sometimes, an external device will have an unknown voltage that could be above or below the desired translation voltage, preventing a normal connection of the LSF. Resistors are added on the A side in place of the second supply in this case – this is an example of when LSF single supply operation is utilized, shown in Figure 9-5. In the following figure, a single 3.3 V supply is used to translate between a 3.3 V device and a device that can change between 1.8 V and 5.0 V. R1 and R2 are added in place of the second supply. Note that due to some current coming out of the Vref_A pin, this cannot be treated as a simple voltage divider. LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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Vref_A V CCB EN 200 kΩ GND LSF0108 Vref_B 3.3 V Device 3.3 V R B1 0.1 μF R A1 1.8 V Device 1.8 V V CCA Figure 9-5. Single Supply Translation with 3.3 V Supply The steps to select the resistor values for R1 and R2 are as follows: 1. Select a value for R1. Typically, 1 MΩ is used to reduce current consumption. 2. Plug in values for your system into the the following equation. Note that Vref_A is the lowest voltage in the system. VCCB is the primary supply and R1 is the selected value from step 1. R 2 = 200 10 3 × R 1 × V R EF A 200 10 3 + R 1 V C C B − V R EF A − 0.85 × R 1 (4) The single supply used must be at least 0.8 V larger than the lowest desired translation voltage. The voltage at Vref_A must be selected as the lowest voltage to be used in the system. The LSF evaluation module (LSF-EVM) contains unpopulated pads to place R1 and R2 for single supply operation testing. For an example single supply translation schematic and details, see the Single Supply Translation with the LSF Family video. www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LSF0108

9.2.4 Voltage Translation for Vref_B < Vref_A + 0.8 V As described in the Enable, Disable, and Reference Voltage Guidelines section, it is generally recommended that Vref_B > Vref_A + 0.8 V; however, the device can still operate in the condition where Vref_B < Vref_A + 0.8 V as long as additional considerations are made for the design. Typical Operation (Vref_B > Vref_A + 0.8 V): in this scenario, pullup resistors are not required on the A-side for proper down-translation as is shown for channels 1 and 2 of Figure 9-4. The typical operating mode of the device ensures that when down translating from B to A, the A-side I/O ports will clamp at Vref_A to provide proper voltage translation. For further explanation of device operation, see the Down Translation with the LSF Family video. Requirements for Vref_B < Vref_A + 0.8 V Operation: in this scenario, there is not a large enough voltage difference between Vref_A and Vref_B to ensure that the A side I/O ports will be clamped at Vref_A, but rather at a voltage approximately equal to Vref_B – 0.8 V. For example, if Vref_B = 1.8 V and Vref_A = 1.2 V, the A-side I/Os will clamp to a voltage around 1.0 V. Therefore, to operate in such a condition, the following additional design considerations must be met:

• Vref_B must be greater than Vref_A during operation (Vref_B > Vref_A)
• Pullup resistors should be populated on A-side I/O ports to ensure the line will be fully pulled up to the desired voltage Figure 9-6 shows an example of this setup, where 1.2 V ↔ 1.8 V translation is achieved with the LSF0108. This type of setup also applies for other voltage nodes such as 1.8 V ↔ 2.5 V, 1.05 V ↔ 1.5 V, and others as long as the Recommended Operating Conditions table is followed. 1.8 V SW SW 1.8 V Device1.2 V Device 200 kΩ Vref_B R PU(B1) Vref_A 1.2 V R PU(B2) EN B2A2 R PU(A2) R PU(A1) 0.1 μF Figure 9-6. 1.2 V to 1.8 V Level Translation with LSF0108 LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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10 Power Supply Recommendations

There are no power sequence requirements for the LSF family. Table 10-1 provides recommended operating voltages for all supply and input pins. Table 10-1. Recommended Operating Voltages PARAMETER MIN TYP MAX UNIT Vref_A(1) reference voltage (A) 0.95 5.0 V Vref_B reference voltage (B) Vref_A + 0.8 5.0 V VI(EN) input voltage on EN pin Vref_A + 0.8 5.0 V Vpu pull-up supply voltage 0 Vref_B V (1) Vref_A is required to be the lowest voltage level across all inputs and outputs.

11 Layout

11.1 Layout Guidelines

Because the LSF family is a switch-type level translator, the signal integrity is highly related with a pull-up resistor and PCB capacitance condition.

• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
• Place LSF close to high voltage side.
• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

11.2 Layout Example GNDVref_AENVref_BA1A2B1B2 Short Signal Trace as possible

Figure 11-1. Short Trace Layout Device PCB TP1SD Controller (1.8 V IO) TP2 LSF0108 SDIO level translator SDIO Connnector (3.3 V IO) Figure 11-2. Device Placement www.ti.com LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LSF0108

12 Device and Documentation Support

12.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, LSF Translator Family Evaluation Module user's guide
• Texas Instruments, Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators application note
• Texas Instruments, Voltage Level Translation with the LSF Family application note
• The Logic Minute Video Training Series on Understanding the LSF Family of Devices: – Texas Instruments, Introduction - Voltage Level Translation with the LSF Family – Texas Instruments, Understanding the Bias Circuit for the LSF Family – Texas Instruments, Using the Enable Pin with the LSF Family – Texas Instruments, Translation Basics with the LSF Family – Texas Instruments, Down Translation with the LSF Family – Texas Instruments, Up Translation with the LSF Family – Texas Instruments, Multi-Voltage Translation with the LSF Family – Texas Instruments, Single Supply Translation with the LSF Family

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LSF0108 SDLS966L – DECEMBER 2013 – REVISED DECEMBER 2022 www.ti.com

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www.ti.com 21-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LSF0101DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VD Samples LSF0101DTQR ACTIVE X2SON DTQ 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FC Samples LSF0102DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NG2 (S, Y) Samples LSF0102DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (G2, NG2J, NG2P, N G2S) NY Samples LSF0102DQER ACTIVE X2SON DQE 8 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 RV Samples LSF0102YZTR ACTIVE DSBGA YZT 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 RV Samples LSF0108DGSR ACTIVE VSSOP DGS 20 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LSF08 Samples LSF0108PWR ACTIVE TSSOP PW 20 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LSF0108 Samples LSF0108RKSR ACTIVE VQFN RKS 20 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 LSF0108 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

www.ti.com 21-Dec-2022 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LSF0102, LSF0108 :

• Automotive : LSF0102-Q1 , LSF0108-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 22-Dec-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 22-Dec-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LSF0101DRYR SON DRY 6 5000 184.0 184.0 19.0 LSF0101DTQR X2SON DTQ 6 3000 189.0 185.0 36.0 LSF0102DCTR SM8 DCT 8 3000 183.0 183.0 20.0 LSF0102DCTR SM8 DCT 8 3000 182.0 182.0 20.0 LSF0102DCUR VSSOP DCU 8 3000 182.0 182.0 20.0 LSF0102DCUR VSSOP DCU 8 3000 180.0 180.0 18.0 LSF0102DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 LSF0102DQER X2SON DQE 8 5000 184.0 184.0 19.0 LSF0102YZTR DSBGA YZT 8 3000 182.0 182.0 20.0 LSF0108DGSR VSSOP DGS 20 5000 356.0 356.0 35.0 LSF0108PWR TSSOP PW 20 2000 364.0 364.0 27.0 LSF0108RKSR VQFN RKS 20 3000 202.0 201.0 28.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRKS 20 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 4.5, 0.5 mm pitch 4226872/A

www.ti.com PACKAGE OUTLINE C 20X 0.30 0.18 1 0.1 20X 0.5 0.3 1.0 0.8 (0.2) TYP 0.05 0.00 14X 0.5 3.5 2X 0.5 3 0.1 A 2.6 2.4 B 4.6 4.4 VQFN - 1 mm max heightRKS0020A PLASTIC QUAD FLATPACK - NO LEAD 4222490/B 02/2021 PIN 1 INDEX AREA 0.08 C SEATING PLANE 0.1 C (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 EXPOSED THERMAL PAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.300

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

20X (0.6) 20X (0.24) 16X (0.5) (4.3) (2.3) (R0.05) TYP (1.25) ( 0.2) VIA TYP (1) (3) VQFN - 1 mm max heightRKS0020A PLASTIC QUAD FLATPACK - NO LEAD 4222490/B 02/2021 SYMM 129 10 11 SYMM LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 20X (0.6) 20X (0.24) 16X (0.5) (2.3) (4.3) 2X (0.95) (0.76) (R0.05) TYP 2X (1.31) VQFN - 1 mm max heightRKS0020A PLASTIC QUAD FLATPACK - NO LEAD 4222490/B 02/2021 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 83% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 10 11

www.ti.com PACKAGE OUTLINE C 4X 0.25 0.17 4X 0.30 0.22

0.40 MAX

0.05 0.00 2X 0.6 0.25 TYP+0.05 -0.03 0.4 B 1.05 0.95 A 0.85 0.75 (0.1) TYP (0.1) (0.08) (0.027) TYP X2SON - 0.4 mm max heightDTQ0006A PLASTIC SMALL OUTLINE - NO LEAD 4224056/A 11/2017 PIN 1 INDEX AREA SEATING PLANE 0.05 C 3 4 0.05 C NOTE 5 (OPTIONAL) PIN 1 ID PKG PKG NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance. 4. The size and shape of this feature may vary. 5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes. SCALE 12.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

4X (0.25) 4X (0.4) (0.25) TYP (R0.05) TYP (0.6) (0.8) (0.4) (0.2) TYP (0.027) TYP (0.2) TYP EXPOSED METAL CLEARANCE X2SON - 0.4 mm max heightDTQ0006A PLASTIC SMALL OUTLINE - NO LEAD 4224056/A 11/2017 NOTES: (continued) 6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SYMM SYMM LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:50X METAL UNDER SOLDER MASK TYP TYP SOLDER MASK OPEING

www.ti.com EXAMPLE STENCIL DESIGN (0.21) (0.8) 4X (0.6) 4X (0.4) 4X (0.25) (R0.05) TYP (0.367) (0.279) TYP (0.2) TYP (0.2) TYP (0.027) TYP X2SON - 0.4 mm max heightDTQ0006A PLASTIC SMALL OUTLINE - NO LEAD 4224056/A 11/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.07 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:50X SYMM SYMM SOLDER MASK EDGE, 2X METAL UNDER SOLDER MASK TYP

www.ti.com PACKAGE OUTLINE C 4.25

3.75 TYP

1.3 1.0 6X 0.65 8X 0.30 0.15 1.95 (0.15) TYP 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.2 A 3.15 2.75 NOTE 3 B 2.9 2.7 NOTE 4 4220784/C 06/2021 SSOP - 1.3 mm max heightDCT0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 1 8

0.13 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.500

www.ti.com EXAMPLE BOARD LAYOUT (3.8) 8X (1.1) 8X (0.4) 6X (0.65) (R0.05) TYP 4220784/C 06/2021 SSOP - 1.3 mm max heightDCT0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (3.8) 6X (0.65) 8X (0.4) 8X (1.1) 4220784/C 06/2021 SSOP - 1.3 mm max heightDCT0008A SMALL OUTLINE PACKAGE NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

www.ti.com PACKAGE OUTLINE C 1.05 0.95 1.45 1.35 0.40 0.34 0.05 0.00 2X 1.05 6X 0.35 7X 0.35 0.25 8X 0.20 0.15 0.45 0.35 (0.13) TYP X2SON - 0.4 mm max heightDQE0008A PLASTIC SMALL OUTLINE - NO LEAD 4225204/A 08/2019 0.05 C

0.07 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package complies to JEDEC MO-287 variation X2EAF. PIN 1 INDEX AREA SEATING PLANE 0.05 C PIN 1 ID SYMM SYMM 4 5 SCALE 9.000 AB

www.ti.com EXAMPLE BOARD LAYOUT 6X (0.35) (R0.05) TYP

0.05 MAX

7X (0.5) 8X (0.175) (0.9) (0.6) X2SON - 0.4 mm max heightDQE0008A PLASTIC SMALL OUTLINE - NO LEAD 4225204/A 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 40X SEE SOLDER MASK DETAIL 4 5 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 7X (0.5) 8X (0.175) 6X (0.35) (0.9) (R0.05) TYP (0.6) X2SON - 0.4 mm max heightDQE0008A PLASTIC SMALL OUTLINE - NO LEAD 4225204/A 08/2019 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.075 MM THICK STENCIL SCALE: 40X SYMM SYMM 4 5

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4207181/G

www.ti.com PACKAGE OUTLINE C 6X 0.25 0.15 0.5 5X 0.35 0.25

0.6 MAX

0.05 0.00 3X 0.6 0.4 0.3 B 1.05 0.95 A 1.5 1.4 (0.05) TYP (0.127) TYP 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.08 C 3 4 (OPTIONAL) PIN 1 ID 0.05 C SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 8.500

www.ti.com EXAMPLE BOARD LAYOUT 5X (0.3) 6X (0.2) 4X (0.5) (0.6) (R0.05) TYP (0.35) 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD SYMM 3 4 SYMM LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X NOTES: (continued) METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 5X (0.3) 6X (0.2) 4X (0.5) (0.6)(R0.05) TYP (0.35) 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X SYMM 3 4 SYMM

www.ti.com PACKAGE OUTLINE C 18X 0.65 5.85 20X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 6.6 6.4 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 10 11 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 10 11

D: Max = E: Max = 1.918 mm, Min = 0.918 mm, Min = 1.858 mm 0.858 mm

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