FAN53730 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Input V oltage Range: 2.3 V to 5.5 V
- Output V oltage: ♦ Programmable from 0.3 V to 2 V ♦ Pin Selectable Defaults
- Low Quiescent Current: 12 /C0109A
- Internal Soft−Start Limits Input Current During Turn−On
- 2.5 MHz Switching Frequency in Continuous Conduction Operation
- 1.2 V and 1.8 V Logic Compatible
- Fault Protection (Input Under V oltage, Short Circuit, Over Current, and Thermal)
- Power Good Output (PG)
- Forced Continuous Conduction Mode (FCCM)
- Audio Reduction Mode Eliminates Audible Tones Due to Switching
- −40°C to +85°C Ambient Temperature Range
- This is a Pb−Free Device
Applications
- LPDDR Memory
- Mobile and Smart Devices
- RF Modules MARKING DIAGRAM See detailed ordering and shipping information on page 2 of this data sheet.
ORDERING INFORMATION
WLCSP12 1.07 x 1.36 x 0.432, 0.35P CASE 567GK SW OUTIN GND SDA/FCCM SCL EN 2.3 V to 5.5 V
0.3 V to 2 V
2 × 4.7 /C0109F 2 x 22 /C0109F 0.24 /C0109H FAN53730 VSEL PG VI/O Figure 1. Typical Application Circuit
www.onsemi.com Option Default VSEL I2C Address Ambient Temperature Range Package Shipping† Specific Device Code FAN53730UCX I2C Controlled VSET1 = 1.00 V VSET2 = 1.05 V 7 h’20 −40°C to 85°C 1.07 mm × 1.36 mm, 0.35 mm pitch, 12−bump WLCSP 3000 / Tape & Reel MH FAN53730UC01X I2C Controlled VSET1 = 1.00 V VSET2 = 1.05 V 7 h’22 3000 / Tape & Reel WE FAN53730UC02X I2C Controlled VSET1 = 1.00 V VSET2 = 1.05 V 7 h’30 3000 / Tape & Reel WF TBD Logic Controlled VSET1 = TBD VSET2 = TBD Not Applicable TBD / Tape & Reel TBD †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NOTE: Additional options available upon request. PIN CONFIGURATION Figure 2. Bumps Facing Down force continuous conduction at all loads. Connect to GND for variable frequency operation. A2, A3 IN Input voltage connection. Connect to a 2.3 V to 5.5 V input supply. B1 SCL SCL input in I2C controlled device. In the logic controlled device this pin is unused and should connect to GND. B2, B3 SW Device switching node. Connect to inductor. C1 VSEL Voltage select input. Drive VSEL low to select VSET1. Drive VSEL high to select VSET2. D1 PG Power good output. PG goes open drain when VOUT is in regulation (I2C device can change polarity of PG). D2 EN Device logic high enable input. Drive EN high to enable the device. I2C bus remains active when EN is low. D3 OUT Output voltage sense input. Connect to positive terminal of output capacitor.
Figure 3. Simplified Block Diagram should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com RECOMMENDED OPERATING CONDITIONS Symbol Parameter Conditions Min Typ Max Unit VIN Input Voltage Range 2.3 − 5.5 V VOUT Output Voltage Range 0.3 − 2 V L Inductor (Nominal Value) −20% 0.24 +20% /C0109H CIN Input Capacitor − 4.7 − /C0109F COUT Output Capacitor (Typical Derated Value) COUT = 2 × 22 /C0109F (0402), VOUT = 1 V, DC bias derated −20% 36 − /C0109F TA Ambient Temperature Range −40 − +85 °C TJ Junction Temperature −40 − +125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at 2.3 V ≤ VIN ≤ 5.5 V, 0.3 V ≤ VOUT ≤ 2V , −40°C ≤ TA ≤ +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.8 V, VOUT = 1.0 V (Note 1, Note 2) Symbol Parameter Test Condition Min Typ Max Unit GENERAL RPD Output Discharge Resistance EN = Low 72 93 131 /C0087 IOUT_SENSE OUT Sense Input Leakage Current VOUT = 1 V − − 1 /C0109A TSD Thermal Shutdown Die Temperature Rising − 150 − °C TSD_HYST Thermal Shutdown Hysteresis − 30 − °C fCLK Fault Clock Frequency 450 500 550 kHz REN Enable Input Pull−Down Resistance VIN = 3.8 V − 300 − k/C0087 RPG PG Output Pull−down − − 133 /C0087 VPG_TH VOUT Rising Threshold for PG Going Open Drain, PG_POL = 1 VOUT = 0.3 V − 93 − % IPG_POL PG Leakage Current EN = Low, VPG = 5.5 V − 0.01 − /C0109A IEN_L EN Input Leakage Current EN = 5.5 V − 0.01 − /C0109A VIH Logic High Voltage (VSEL, EN, FCCM) 0.825 − − V VIL Logic Low Voltage (VSEL, EN, FCCM) − − 0.4 V VOUT ACCURACY VOUT_ACC Output Voltage Accuracy VOUT < 1 V, No Load, VIN ≥ VOUT +1 . 5V −20 − 9 mV VOUT ≥ 1 V, No Load, VIN ≥ VOUT +1 . 5V −16 − 12 mV VOUT < 1 V, FCCM, No Load, VIN ≥ VOUT +1 . 5V −14 − 13 mV VOUT ≥ 1 V, FCCM, No Load, VIN ≥ VOUT +1 . 5V −1 − 1.1 % OPERATING CURRENT ISHDN Shutdown Supply Current I2C Controlled device, EN = Low, SDA = SCL = 1.2 V − 1.5 3.5 /C0109A ISHDN Shutdown Supply Current Logic Controlled device, EN = Low − 1.5 3.5 /C0109A IQ_ACTIVE Active Supply Current VOUT = 1 V, EN = High, No Load, No Switching − 12.8 19.3 /C0109A CURRENT LIMIT IVALLEY Valley Current Limit VOUT = 1 V, [VAL_ILIM] = 1 3.5 4.2 4.8 A IVALLEY Valley Current Limit VOUT = 1 V, [VAL_ILIM] = 0 1.9 2.3 2.6 A ILIM_NEG Negative Current limit − 1.5 − A tSHORT Short−Circuit Timeout VOUT < 0.1 V (Note 3) − 40 − /C0109s VSHORT Output Short Circuit Threshold t < tSHORT 68 140 212 mV
www.onsemi.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum values are at 2.3 V ≤ VIN ≤ 5.5 V, 0.3 V ≤ VOUT ≤ 2V , −40°C ≤ TA ≤ +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.8 V, VOUT = 1.0 V (Note 1, Note 2) Symbol UnitMaxTypMinTest ConditionParameter SWITCH ON TIME tON High side switch on−time VIN = 2.3 V, VOUT = 1 V 181 196 202 ns tON High side switch on−time VIN = 3.8 V, VOUT = 1 V 104 113 116 ns tON High side switch on−time VIN = 5.5 V, VOUT = 1 V 70 78 80 ns UVLO DETECTION VUVLO_R Under−Voltage Lockout Threshold Rising VIN − − 2.3 V VUVLO_F Under−Voltage Lockout Threshold Falling VIN 2.1 − − V VUVLO_H UVLO Hysteresis − 100 − mV POWER MOSFETs RDSON RDSON_LOW Low Side NMOS Resistance (Ball−to−Ball) VIN = VGS = 3.8 V − 23 − m/C0087 RDSON_HIGH High Side NMOS Resistance (Ball−to−Ball) VIN = VGS = 3.8 V − 33 − m/C0087 AUDIO MODE RAUDIO Pull−down FET for Output Discharge VIN = 3.8 V − 5 − /C0087 tAUDIO Maximum Dead Time in Audio Mode [ARM_TO] = 0 − 25 − /C0109s tAUDIO Maximum Dead Time in Audio Mode [ARM_TO] = 1 − 40 − /C0109s I2C TIMING AND PERFORMANCE − FOR I2C VERSION (Note 4) VIL SDA and SCL Logic Low threshold − − 0.4 V VIH SDA and SCL Logic High threshold 0.825 − 5.5 V VOL SDA Logic Low Output 3 mA sink − − 0.4 V fSCL SCL Clock Frequency Fast Mode Plus − − 1000 kHz tBUF Bus−Free Time Between STOP and START Conditions Fast Mode Plus 0.5 − − /C0109s tHD; STA START or Repeated START Hold Time Fast Mode Plus 260 − − ns tLOW SCL LOW Period Fast Mode Plus 0.5 − − /C0109s tHIGH SCL HIGH Period Fast Mode Plus 260 − − ns tR SDA and SCL Rise Time Fast Mode Plus − − 120 ns tF SDA and SCL Fall Time Fast Mode Plus, VDD = 1.8 V 6.55 − 120 ns tSU; STO Stop Condition Setup Time Fast Mode Plus 260 − − ns CI SDA and SCL Input Capacitance − − 10 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Refer to Typical Characteristics waveforms/graphs for closed loop data and variation with input supply and temperature. 2. Electrical Characteristics reflects open loop steady state data. System Characteristics reflects both steady state and dynamic close loop data associated with the recommended external components. 3. Short −Circuit timeout is the time after VOUT falls below VSHORT to when the FAN53730 is placed into the Fault state. 4. Guaranteed by Design. Characterized on the ATE or Bench.
www.onsemi.com SYSTEM CHARACTERISTICS The following system specifications are guaranteed by designed and verified during bench evaluation, but are not performed in production −40°C ≤ TA ≤ 85°C. Typical values are based on VIN = 3.8 V, VOUT = 1.0 V and TA = 25°C. System Specifications are based on the Typical Application Circuit, L = 0.24 /C0109H, CIN = 10 /C0109F, COUT = 2 x 22 /C0109F (nominal) Symbol Parameter Test Condition Min Typ Max Unit GENERAL IQIN_DCM DCM Quiescent Current EN = High, 2.3 V ≤ VIN ≤ 5.5 V, VOUT = 1 V, [BIAS_MODE] = 00, No Load − 12.8 19.3 /C0109A EN = High, [BIAS_MODE] = 1X, No Load − 262 − /C0109A IQCCM CCM Quiescent Current EN = High, FCCM, No Load − 13.9 − mA tss Soft−Start From EN High to 95% of VOUT Target, No Load, [RR_DVS] = 001 − 800 − /C0109s EFFICIENCY eff Efficiency IOUT = 1 mA, VOUT = 1.0 V, VIN = 3.8 V − 82.1 − % eff Efficiency IOUT = 10 mA, VOUT = 1.0 V, VIN = 3.8 V − 86.8 − % eff Efficiency IOUT = 100 mA, VOUT =1.0 V, VIN = 3.8 V − 87.5 − % eff Efficiency IOUT = 500 mA, VOUT = 1.0 V, VIN = 3.8 V − 88.2 − % eff Efficiency IOUT = 1000 mA, VOUT = 1.0 V, VIN = 3.8 V − 89.3 − % eff Efficiency IOUT = 3000 mA, VOUT = 1.0 V, VIN = 3.8 V − 83 − % IOUT MAX IOUT_MAX Maximum Output Current (Note 6) VIN from 2.5 V to 5.5 V, VOUT from 0.3 V to 1 V 3 − − A VOUT LOAD REGULATION VLO_REG Load Regulation IOUT = 10 /C0109A to 3 A, VIN = 2.5 V to 5.5 V, VOUT = 1 V, [BIAS_MODE] = 00 − − 0.6 %/A VLO_REG Load Regulation IOUT = 10 /C0109A to 3 A, VIN = 2.5 V to 5.5 V, VOUT = 1 V, [BIAS_MODE] = 1X − − 0.4 %/A VLO_REG Load Regulation (CCM) IOUT = 10 /C0109A to 3 A, VIN = 2.5 V to 5.5 V, VOUT = 1 V, FCCM − − 0.4 %/A VOUT LINE REGULATION VLREG_CCM Line Regulation 10 /C0109A IOUT = 10 /C0109A, VOUT = 1 V, VIN = 2.5 V to 5.5 V − − 0.12 %/V VLREG_DCM Line Regulation 10 mA IOUT = 10 mA, VOUT = 1 V, VIN = 2.5 V to 5.5 V − − 0.08 %/V VLREG_DCM Line Regulation 3 A IOUT = 3 A, VOUT = 1 V, VIN = 2.5 V to 5.5 V − − 0.08 %/V SWITCHING VRIPPLE_DCM Output Ripple VIN = 2.3 V to 5.5 V, IOUT = 10 mA, FCCM, VOUT = 1 V − 12 − mVpp VRIPPLE_CCM Output Ripple VIN = 2.3 V to 5.5 V, IOUT = 3 A, VOUT = 1 V − 6 − mVpp fCCM Switching Frequency in CCM Mode IOUT = 1 A, FCCM − 2.5 − MHz
www.onsemi.com SYSTEM CHARACTERISTICS (continued) The following system specifications are guaranteed by designed and verified during bench evaluation, but are not performed in production −40°C ≤ TA ≤ 85°C. Typical values are based on VIN = 3.8 V, VOUT = 1.0 V and TA = 25°C. System Specifications are based on the Typical Application Circuit, L = 0.24 /C0109H, CIN = 10 /C0109F, COUT = 2 x 22 /C0109F (nominal) Symbol UnitMaxTypMinTest ConditionParameter CURRENT LIMIT IVALLEY_CL Closed Loop Valley Current Limit (Note 5) VIN ≥ 2.5 V, [VAL_ILIM] = 1 − 4.6 − A VIN ≥ 2.5 V, [VAL_ILIM] = 0 − 2.3 − A VIN = 2.3 V, [VAL_ILIM] = 1 − 2.8 − A VIN = 2.3 V, [VAL_ILIM] = 0 − 1.8 − A 5. Closed loop current limit reflects the maximum control loop error amplifier voltage output, which can mean that the inductor valley current limit has reached its maximum value, or that the control loop has reached a maximum duty cycle. 6. Refer to Fig. 19 Typical Derating Curve for additional I OUT(MAX) guidance.
Unless otherwise specified VIN = 3.8 V, VOUT = 1 V, TA = 25°C, Circuit of Figure 34 and components from Applications Circuit Components Table.
0.3 VOUT
0.5 VOUT
1.0 VOUT
Figure 8. Quiescent Current (DCM) vs. VIN, Figure 9. Quiescent Current (DCM) vs. VIN,
1.8 VOUT
0.8 VOUT
1.3 VOUT
1.5 VOUT
2.0 VOUT
www.onsemi.com FUNCTIONAL SPECIFICATIONS Device Options Options and Features The FAN53730 has two options: 1. A fully programmable I2C version. 2. A logic controlled fixed output voltage version. The following table lists the differences between the two: FAN53730 FEATURE BREAKDOWN Feature Logic Controlled Device I2C Controlled Device Enable (EN) Logic Enable Input Only Logic Enable Input and Enable Bit Thermal Shutdown Yes, 150°C Yes, 150°C Under Voltage Lockout (UVLO) Yes Yes Power Good Output (PG) Yes (goes open drain when VOUT > 93% of target) Yes (programmable active high or active low) Output Pull−Down Yes, In shutdown (100 /C0087) Yes, In shutdown (100 /C0087). Can be disabled via I2C Forced Continuous Conduction (FCCM) Yes, via FCCM input Yes, via I2C or when VSEL = High and [VSEL_FCCM] = 1 Voltage Select Input (VSEL) Yes, VSET1 and VSET2 are fixed by device voltage options Yes, VSET1 and VSET2 targets are programmable Audio Reduction Mode (ARM) No (disabled) Yes, can be enabled via I2C Valley Current Limit Fixed at 4.6 A (typ) Programmable to 4.6 A or 2.3 A to accommodate different sized inductors Dynamic Voltage Scaling Yes Yes, 8 programmable slew rates. Can be disabled via I Low Power Mode (PFM) During Light Load Yes Yes, can be disabled via I2C Output Short Fault Yes Yes Fault Auto−Restart / Shutdown Auto−Restart Can be programmed to auto−restart after a fault, or go into shutdown Overview Constant On−Time Operation (COT) The FAN53730 is a constant on−time (COT) synchronous buck which regulates a 0.3 V to 2 V output voltage from a 2.3 V to 5.5 V input voltage. The COT controller operates as follows: When the output voltage falls out of regulation the input power switch turns on for the fixed on time (t ON) and ramps the inductor current. At the end of tON the input switch turns off and the low side synchronous FET turns on and discharges the inductor into the output. If the inductor current reaches 0 before the load pulls the output voltage out of regulation, both the input FET and the synchronous FET will turn off and the device enters an idle state where it will remain until the output falls below the regulation target. Once the output falls below the regulation target the switching action starts again. This results in a variable frequency operation (load dependent) for light currents. At higher load currents (dependent on V IN, and V OUT) the inductor current will no longer hit 0 before the output voltage falls out of regulation. This results in an approximate constant switching frequency at heavy loads. On−Time and Maximum Switching Frequency The Buck switch on−time (t ON) varies with VIN and VOUT in order to approximately target a 2.5 MHz switching frequency at VIN = 3.8 V and VOUT = 1 V , when the device is operating in continuous conduction mode. Although this switching frequency will have some variation due to delays and non−linearities in the timing circuit, as well as load dependence effects due to resistive drops that make the effective V IN lower. Typical CCM frequency variation is shown in the typical operating characteristic graphs. Efficiency The load dependent switching frequency allows the buck converter to only switch as necessary to keep the load in regulation. This provides for an optimum efficiency response vs load, as the light load switching losses are
the idle period. This results in low quiescent current. The Enable input (EN) is an active high device enable. active state and the output is regulating at its target voltage. the ENABLE (REG 06h[0]) bit set to 1 to enable the device. PG when set for active high operation.
- EN goes high and the bias and reference are enabled.
- After the 400 /C0109s start −up delay, V
during the de−glitch timer, PG is pulled high.
- When a voltage change occurs which forces VOUT to
a higher level, PG goes low.
- After the V OUT ramp completes and the 128 /C0109s
de−glitch timer expires, PG goes high.
- When V OUT is set to a new lower voltage, PG
- If VOUT is forced below 93% of the target voltage for
t > 128 /C0109s (or if any fault occurs PG will pull−low).
- PG will go high again if the condition which forced
- When enable is brought low, the PG output will pull
than the 128 /C0109s de−glitch time (see below). Figure 25. PG Operation
programmable using RR_DVS (Reg 02h [4:2]).
0 XXX Immediate
set−point (10 mV/step) with a pause at each step of 10 /C0109s. immediately change to the new value without a ramp. high to low voltage transitions. Figure 32. DVS Voltage Ramp
higher switching losses in the converter. has a dedicated pin, called FCCM, for this feature. OUT will continue to discharge the output capacitor. buck converter operating conditions. Figure 33. DCM vs. CCM Operation the output voltage will shift to the fixed VSET1 target.
www.onsemi.com VSEL AND FCCM FORCE_CCM bit VSEL_FCCM bit VSEL Input Result
0 X 0 VOUT = VSET1 target and buck is in Auto DCM/CCM
0 0 1 VOUT = VSET2 target and buck is in Auto DCM/CCM 0 1 1 VOUT = VSET2 target and buck is in FCCM
1 X 0 VOUT = VSET1 target and buck is in FCCM
1 X 1 VOUT = VSET2 target and buck is in FCCM
The I2C controlled device has three programmable bias mode options for reducing the device’s quiescent current. These BIAS_MODE (Reg 03h [2:1]) bits disable infrequently used internal logic blocks during long SW idle periods, as described below: High Bias Mode All circuitry active when the part is enabled. Under certain conditions this mode can provide for a faster response to transient disturbances, but at the expense of higher quiescent current. Low Bias Mode Forces some of the FAN53730’s circuitry into shutdown during the DCM idle state. This will greatly reduce no load quiescent current, but under certain conditions can lead to a slower response to a transient event. Ultra Low Bias Mode This mode is the default selection and will provide the lowest no load quiescent current. The logic version of the device also has the Low Bias Mode option enabled. Protection Features Fault Protection The FAN53730 contains 4 fault modes consisting of:
- VIN UVLO Fault
- Current Limit Fault
- Output Short Fault
- Thermal Fault When any of these faults occur, the FAN53730 is placed in the fault state and is shutdown. By default, the OUT_DISCHARGE (Reg 06h [3]) bit enables the output discharge resistor during shutdown. During Current Limit and Output Short faults the converter will auto−restart every 20 ms. This feature can be disabled by setting FAULT_SHDN (Reg 03h [3]) = 1, and instead the ENABLE bit will be reset to 0 (device remains in shutdown). Under Voltage Fault A V IN UVLO is detected if VIN falls below the UVLO_F threshold for 40 /C0109s. Once this happens, the device stops switching and is placed in the Fault State. In the I2C version the UVLO_FAULT Flag is set. If VIN continues to fall past the UVLO threshold and crosses the power on reset threshold, the FAN53730 will immediately shutdown. Current Limit Timeout During valley current limit events, when I L is clamped at IV ALLEY, the fault clock begins counting. If the fault clock reaches 40 /C0109s of a continuous valley current limit condition, the device is placed into the fault state. During the fault count, if a period occurs without a valley current limit clamp event then the count is reset to 0. In the I 2C version, when the part is placed into the fault state, the ILIM_FAULT flag is set. Output Short Fault If the output voltage falls below 100 mV for 40 /C0109s, after the device has reached the active state (power good), the device will detect an output short fault and be forced into the fault state. In the I 2C version, when the part is placed into the fault state, the SHORT_FAULT flag is set. Thermal Shutdown When the die temperature increases due to a high load condition and/or a high ambient temperature, the FAN53730 can reach a thermal fault condition and be placed in the Fault State. In the I2C version the OVER_TEMP_FAULT flag is set. The device will restart after it cools below the hysteresis level.
www.onsemi.com Operation I2C Interface The I2C interface is compatible with Standard, Fast, and Fast Plus I2C bus specifications. The SCL line is an input and the SDA line is a bi −directional open−drain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first. I 2C Slave Address The equivalent 7 bit slave identification for the FAN53730UCX device version is 7h’20. This is followed by the read/write bit (0 = Write) and (1 = Read). 7−Bit Binary Hex 7h’20 0100000 8h’40 REGISTER MAP REGISTER MAPPING TABLE Read Only Write Only Read / Write Read / Clear Write/Clear Address Name Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] 0x01 FAULT FLAGS 0 POWER_GOOD 0 UVLO_FAULT OVER_TEMP _FAULT SHORT_FAULT ILIM_FAULT 0x02 CONFIG1 0 ARM_TO DVS_FCCM RR_DVS HIGH_BANDWIDTH VAL_ILIM 0x03 CONFIG2 0 Transient_ Enhancement FAULT_SHDN BIAS_MODE PG_POL 0x04 VOUT_SET_1 VSET1 0x05 VOUT_SET_2 VSET2 0x06 ENABLE 0 ARM_EN DVS_EN OUT_DISCHA RGE VSEL_FCCM FORCE_CCM ENABLE 0x09 RESET SOFT_RESET
Table 1. REGISTER DETAILS − 0 /C0121 01 FAULT FLAGS
5 POWER_GOOD 0 Read Reset condition: 0
0 Power good output is not active
1 Power good output is active
4 UNUSED
3 UVLO_FAULT 0 R/CLR Reset condition: 0
Displays UVLO fault status. This flag is set when a UVLO fault occurs. The flag is cleared upon read.
0 No UVLO fault occurred
1 A UVLO fault occured
2 OVER_TEMP_FAULT 0 R/CLR Reset condition: 0
Displays over temp fault status. This flag is set when a die over temp fault occurs. The flag is cleared upon read.
0 No over temp fault
1 An over temp fault occurred
1 SHORT_FAULT 0 R/CLR Reset condition: 0
Displays VOUT short fault status. This flag is latched when a VOUT short fault occurs. The flag is cleared upon read.
0 The output has not shorted
0 ILIM_FAULT 0 R/CLR Reset condition: 0
The ILIM flag is set if the valley current limit is triggered continuously for 40 /C0109s. The flag is cleared upon read.
0 No ILIM fault
1 ILIM triggered event for 40 /C0109s
Table 2. REGISTER DETAILS − 0 /C0121 02 CONFIG1
7 UNUSED
6 ARM_TO 0 R/W Reset condition: 0
5 DVS_FCCM 0 R/W Reset condition: 0
and the voltage is programmed from high to low.
0 Force CCM is not active during negative V OUT transitions
1 Force CCM is active during negative V OUT transitions
1 HIGH_BANDWIDTH 1 R/W Reset condition: 1
Control loop high bandwidth adjust. Set to “0” when VOUT < 0.8 V.
0 Low Bandwidth setting
1 High Bandwidth setting
0 VAL_ILIM 1 R/W Reset condition: 1
current to the IVALLEY target.
Table 3. REGISTER DETAILS − 0 /C0121 03 CONFIG2
4 TRANSIENT_ENHANCEMENT 1 R/W Reset condition: 1
0 Transient Enhancement Disabled
1 Transient Enhancement Enabled
3 FAULT_SHDN 0 R/W Reset condition: 0
This register enables/disables the shutdown option for faults.
0 The converter will auto −restart after 20 ms if a fault occurs
1 The converter will be placed into shutdown if a fault occurs
current vs. output accuracy and response time.
00 Ultra Low Bias Mode
01 Low Bias Mode
0 PG_POL 1 R/W Reset condition: 1
0 PG output is active low
1 PG output is active high
Table 4. REGISTER DETAILS − 0 /C0121 04 VOUT_SET_1 Sets the buck regulation target voltage when VSEL = low.
Table 4. REGISTER DETAILS − 0 /C0121 04 VOUT_SET_1 (continued) Sets the buck regulation target voltage when VSEL = low.
Table 5. REGISTER DETAILS − 0 /C0121 05 VOUT_SET_2 Sets the buck regulation target voltage when VSEL = high.
Table 5. REGISTER DETAILS − 0 /C0121 05 VOUT_SET_2 (continued) Sets the buck regulation target voltage when VSEL = high.
Table 6. REGISTER DETAILS − 0 /C0121 06 ENABLE
5 ARM_EN 0 R/W Reset condition: 0
0 Audio Reduction Mode Disabled
1 Audio Reduction Mode Enabled
4 DVS_EN 1 R/W Reset condition: 0
0 DVS disabled
1 DVS enabled
3 OUT_DISCHARGE 1 R/W Reset condition: 1
0 Output discharge is disabled
1 Output discharge is enabled when device is placed in shutdown
2 VSEL_FCCM 0 R/W Reset condition: 0
0 FCCM and VSEL are separate functions
1 FCCM will be enabled when VSEL is at a logic high
1 FORCE_CCM 0 R/W Reset condition: 0
0 Auto (DCM/CCM depending on load current)
1 Force CCM at all loads
0 ENABLE 0 R/W Reset condition: 0
EN input must be driven high to enable the device.
0 Device disabled
1 Device enabled
Table 7. REGISTER DETAILS − 0 /C0121 09 RESET faults when 0 × 45h code is written to it.
Figure 34. Typical Application Circuit which can feed into VOUT and other nodes. capacitance may have to be increased. similar inductors for the specific application.
WLCSP12 1.07x1.36x0.432, 0.35P CASE 567GK ISSUE O DATE 09 NOV 2021 XXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “/C0071”, may or may not be present. Some products may not follow the Generic Marking. GENERIC MARKING DIAGRAM* XXXX XXXX AYWW MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. 98AON82480GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1WLCSP12 1.07x1.36x0.432, 0.35P © Semiconductor Components Industries, LLC, 2021 www.onsemi.com
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