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Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201130 05/07/2014 Rev#A11 ECN# LS3954A LS3954 LS3955 LS3956 LS3958
FEATURES
LOW DRIFT IΔVGS1-2/ΔT│=5µV/°C max. LOW LEAKAGE IG=20pA TYP. LOW NOISE en=10Nv/√Hz TYP. ABSOLUTE MAXIMUM RATINGS1 @ 25 °C (unless otherwise noted) Maximum Temperatures Storage Temperature -55 to +150°C Operating Junction Temperature -55 to +150°C Maximum Voltage and Current for Each Transistor1 -VGSS Gate Voltage to Drain or Source 60V -IG(f) Gate Forward Current 50mV Maximum Power Dissipation Device Dissipation @ Free Air - Total 400mW @ 25ºC2 ELECTRICAL CHARACTERISTICS @ 25ºC (unless otherwise noted) SYMBOL CHARACTERISTIC LS3954A LS3954 LS3955 LS3956 LS3958 UNITS CONDITIONS │∆VGS1-2/∆T│max. Drift vs. Temperature 5 10 25 50 100 µV/ºC VDG = 20V, ID=200µA TA = -55ºC to +125ºC │VGS1-2│max. Offset Voltage 5 5 10 15 25 mV VDG =20V, ID=200µA SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS CONDITIONS BVGSS Breakdown Voltage 60 -- -- V VDS= 0 IG= 1µA BVGGO Gate-to-Gate Breakdown 60 -- -- V IGG= ±1µA ID= 0 IS= 0 TRANSCONDUCTANCE gfss Full Conduction 1000 2000 4000 µS VDG= 20V VGS= 0 f = 1kHz gfs Typical Operation 500 700 1250 µS VDG= 20V ID= 200µA │gfs1-2/gfs│ Differential -- ±0.6 ±3 % DRAIN CURRENT IDSS Full Conduction 0.5 2 5 mA VDS= 20V VGS= 0 │IDSS1-2/IDSS│ Differential -- ±1 ±5 % GATE VOLTAGE VGS(off) Pinchoff Voltage -1 -2 -4.5 V VDS= 20V ID= 1nA VGS Operating Range -0.5 -- -4 V VDS= 20V ID= 200µA GATE CURRENT -IG Operating -- 20 50 pA VDG= 20V ID= 200µA -IG High Temperature -- -- 50 nA VDG= 20V ID= 200µA TA=+125 ºC -IG Reduced VDG -- 5 -- pA VDG= 10V ID= 200µA -IGSS At Full Conduction -- -- 100 pA VDG= 20V VDS= 0 LS3954A LS3954 LS3955 LS3956 LS3958 LOW NOISE LOW DRIFT MONOLITHIC DUAL N-CHANNEL JFET AMPLIFIER Top View SOIC Top View TO-71 & TO-78
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201130 05/07/2014 Rev#A11 ECN# LS3954A LS3954 LS3955 LS3956 LS3958 SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS CONDITIONS OUTPUT CONDUCTANCE goss Full Conduction -- -- 35 µS VDG= 20V VGS= 0 gos Operating -- 0.5 1 µS VDG= 20V ID= 200µA │gos1-2│ Differential -- 0.05 µS COMMON MODE REJECTION CMRR -20 log │ΔVGS1-2/ΔVDS│ -- 100 -- dB ΔVDS= 10 to 20V ID=200µA CMRR -20 log │ΔVGS1-2/ΔVDS│ -- 75 -- dB ΔVDS= 5 to 10V ID=200µA NOISE NF Figure -- -- 0.5 dB VDS= 20V VGS= 0 RG=10MΩ f= 100Hz NBW=6Hz en Voltage -- -- 15 nV/√Hz VDS= 20V ID= 200µA f= 10Hz NBW=1Hz CAPACITANCE CISS Input -- -- 6 pF VDS= 20V VGS= 0 f= 1MHz CRSS Reverse Transfer -- -- 2 pF CDD Drain-to-Drain -- 0.1 -- pF VDG= 20V ID= 200µA Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products develo ped at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, Co-Founder and Vice President of R&D at Intersil, and Founder/President of Micro Power Systems. TO-71 TO-78 SOIC SS SS SS SS Note: All Dimensions in inches 1. These ratings are limiting values above which the serviceability of any semiconductor may be impaired. 2. Derate 4mWºC above 25ºC Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. NOTES: P-DIP 0.210 0.170