LS173A

SN74LS173A TI | Alldatasheet

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SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00683-State Outputs Interface Directly With System Bus /C0068Gated Output-Control LInes for Enabling or Disabling the Outputs /C0068Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) /C0068For Application as Bus Buffer Registers /C0068Package Options Include Plastic Small-Outline (D) Packages, Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz

description

The ’173 and ’LS173A 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G 1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table. The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C. Copyright  1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. M N CLK GND V CC CLR G G 1 SN54173, SN54LS173A ...J O R W PACKAGE SN74173 ...N PACKAGE SN74LS173A ...D o r N PACKAGE (TOP VIEW) 321 2 0 1 9 91 01 11 21 3 NC NC SN54LS173A . . . FK PACKAGE (TOP VIEW)N M NC CLR GND NC CCV NC – No internal connection CLK On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

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Q H X X X X L L LX XX Q 0 L ↑ HX X Q 0 L ↑ XH X Q 0 L ↑ L L L L L ↑ L L H H When either M or N (or both) is (are) high, the output is disabled to the high-impedance state; however, sequential operation of the flip-flops is not affected. logic symbol† G 2 G 1 G 2 G 1 R CLR 2D 2Q 3D 3Q 4D 4Q M CLK † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, N, and W packages. EN N 1D 1Q R CLR 2D 2Q 3D 3Q 4D 4Q M CLK EN N ’173 ’LS173A

SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) R R R R M N CLR CLK Output Control Data Enable G 1 G 2 Pin numbers shown are for D, J, N, and W packages.

SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

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schematics of inputs and outputs Equivalent of Each Input Equivalent of Each Input Typical of All Outputs VCC Input 4 kΩ NOM VCC Input 20 kΩ NOM VCC Output 90 Ω NOM VCC Output 100 Ω NOM ’173 ’LS173A Typical of All Outputs absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.

SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) SN54173 SN74173 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V IOH High-level output current –2 –5.2 mA IOL Low-level output current 16 16 mA TA Operating free-air temperature –55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † SN54173 SN74173 UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VIK Input clamp voltage VCC = MIN, II = –12 mA –1.5 –1.5 V VOH High-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOH = MAX 2.4 2.4 V VOL Low-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOL = 16 mA 0.4 0.4 V IO( ff) Off-state (high-impedance state)VCC = MAX, VO = 2.4 V 150 40 µAIO(off) (g ) output current CC , VIH = 2 V VO = 0.4 V –150 –40 µA II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 1 mA IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 µA IIL Low-level input current VCC = MAX, VI = 0.4 V –1.6 –1.6 mA IOS Short-circuit output current§ VCC = MAX –30 –70 –30 –70 mA ICC Supply current VCC = MAX, See Note 4 50 72 50 72 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V, N, G1, G2, and all data inputs grounded; and CLK and M at 4.5 V. timing requirements over recommended operating conditions (unless otherwise noted) SN54173 SN74173 UNIT MIN MAX MIN MAX UNIT fclock Input clock frequency 25 25 MHz tw Pulse duration CLK or CLR 20 20 ns Data enable (G1, G2) 17 17 tsu Setup time Data 10 10 ns CLR (inactive state) 10 10 th Hold time Data enable (G1, G2) 2 2 nsth Hold time Data 10 10 ns

SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, TA = 25°C, RL = 400 Ω (see Figure 1) PARAMETER TEST CONDITIONS SN54173 SN74173 UNITPARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT fmax Maximum clock frequency 25 35 25 35 MHz tPHL Propagation delay time, high-to-low-level output from clear input 18 27 18 27 ns tPLH Propagation delay time, low-to-high-level output from clock inputC L = 50 pF 28 43 28 43 ns tPHL Propagation delay time, high-to-low-level output from clock input L 19 31 19 31 ns tPZH Output enable time to high level 7 16 30 7 16 30 ns tPZL Output enable time to low level 7 21 30 7 21 30 ns tPHZ Output disable time from high level C L =5 pF 3 5 14 3 5 14 ns tPLZ Output disable time from low level C L = 5 pF 3 11 20 3 11 20 ns

SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions SN54LS173A SN74LS173A UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V IOH High-level output current –1 –2.6 mA IOL Low-level output current 12 24 mA TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † SN54LS173A SN74LS173A UNIT PARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V VOH High-level output voltage VCC = MIN, VIL = VILmax, VIH = 2 V, IOH = MAX 2.4 3.4 2.4 3.1 V VOL Low level output voltage VCC = MIN, IOL = 12 mA 0.25 0.4 0.25 0.4 V VOL Low-level output voltage CC , VIL = 0.8 V, IOL = 24 mA 0.35 0.5 V IO( ff) Off-state (high-impedance state)VCC = MAX, VO = 2.7 V 20 20 VIO(off) (g ) output current CC , VIH = 2 V VO = 0.4 V –20 –20 V II Input current at maximum input voltage VCC = MAX, VI = 7 V 0.1 0.1 mA IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 µA IIL Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA IOS Short-circuit output current§ VCC = MAX –30 –130 –30 –130 mA ICC Supply current VCC = MAX, See Note 4 19 30 19 24 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V, N, G1, G2, and all data inputs grounded; and CLK and M at 4.5 V. timing requirements over recommended operating conditions (unless otherwise noted) SN54LS173A SN74LS173A UNIT MIN MAX MIN MAX UNIT fclock Input clock frequency 30 25 MHz tw Pulse duration CLK or CLR 25 25 ns Data enable (G1, G2) 35 35 tsu Setup time Data 17 17 ns CLR (inactive state) 10 10 th Hold time Data enable (G1, G2) 0 0 nsth Hold time Data 3 3 ns

SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, TA = 25°C, RL = 667 Ω (see Figure 2) PARAMETER TEST CONDITIONS SN54LS173A SN74LS173A UNITPARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT fmax Maximum clock frequency 30 50 30 50 MHz tPHL Propagation delay time, high-to-low-level output from clear input 26 35 26 35 ns tPLH Propagation delay time, low-to-high-level output from clock inputC L = 45 pF 17 25 17 25 ns tPHL Propagation delay time, high-to-low-level output from clock input L 22 30 22 30 ns tPZH Output enable time to high level 15 23 15 23 ns tPZL Output enable time to low level 18 27 18 27 ns tPHZ Output disable time from high level C L =5 pF 11 20 11 20 ns tPLZ Output disable time from low level C L = 5 pF 11 17 11 17 ns

NOTES: A. C L includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH , tPHL , tPHZ , and tPLZ ; S1 is open and S2 is closed for tPZH ; S1 is closed and S2 is open for tPZL . 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH , tPHL , tPHZ , and tPLZ ; S1 is open and S2 is closed for tPZH ; S1 is closed and S2 is open for tPZL . E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω , tr ≤ 15 ns, tf ≤ 6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms

www.ti.com 29-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) JM38510/36101BEA Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 36101BEA JM38510/36101BEA.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 36101BEA JM38510/36101BFA Active Production CFP (W) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 36101BFA JM38510/36101BFA.A Active Production CFP (W) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 36101BFA M38510/36101BEA Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 36101BEA M38510/36101BFA Active Production CFP (W) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 36101BFA SN54173J Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54173J SN54173J.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54173J SN54LS173AJ Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54LS173AJ SN54LS173AJ.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54LS173AJ SN74LS173AD Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LS173A SN74LS173AD.A Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LS173A SN74LS173AN Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 SN74LS173AN SN74LS173AN.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 SN74LS173AN SNJ54173J Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54173J SNJ54173J.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54173J SNJ54LS173AFK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54LS 173AFK SNJ54LS173AFK.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54LS 173AFK SNJ54LS173AJ Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54LS173AJ SNJ54LS173AJ.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54LS173AJ (1) Status: For more details on status, see our product life cycle. Addendum-Page 1

www.ti.com 29-May-2025 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LS173A, SN74LS173A :

• Catalog : SN74LS173A
• Military : SN54LS173A NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) JM38510/36101BFA W CFP 16 25 506.98 26.16 6220 NA JM38510/36101BFA.A W CFP 16 25 506.98 26.16 6220 NA M38510/36101BFA W CFP 16 25 506.98 26.16 6220 NA SN74LS173AD D SOIC 16 40 507 8 3940 4.32 SN74LS173AD.A D SOIC 16 40 507 8 3940 4.32 SN74LS173AN N PDIP 16 25 506 13.97 11230 4.32 SN74LS173AN N PDIP 16 25 506 13.97 11230 4.32 SN74LS173AN.A N PDIP 16 25 506 13.97 11230 4.32 SN74LS173AN.A N PDIP 16 25 506 13.97 11230 4.32 SNJ54LS173AFK FK LCCC 20 55 506.98 12.06 2030 NA SNJ54LS173AFK.A FK LCCC 20 55 506.98 12.06 2030 NA Pack Materials-Page 1

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\

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