LS1021A NXP | Alldatasheet
Document overview
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Technical content
Features
- Arm® Cortex®-A7 MPCore compliant with Armv7- A™ architecture
- LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and Arm TrustZone®
- Snoop Control Unit (SCU)
- 512 KB unified I/D L2 Cache (ECC protection)
- Hierarchical interconnect fabric – The platform has a single 128-bit AMBA 4 AXI Coherency Extensions (ACE) master port, which connects to CCI-400 Interconnect.
- One 8/16/32-bit DDR3L/DDR4 SDRAM memory controllers – ECC and interleaving support
- VeTSEC Ethernet complex – Up to 3x Gigabit Ethernet – MII, RMII, RGMII, and SGMII support – QoS, lossless flow control, and IEEE® 1588
- Up to 4 SerDes lanes for high-speed peripheral interfaces – Two PCI Express Gen2 controllers – One Serial ATA 3.0 (SATA 1.5, 3.0, 6.0 Gbps) controller – Two SGMII interfaces supporting 1000 Mbps
- Integrated audio block – Four synchronous audio interfaces (SAI) – I2S, AC97, and Codec/DSP interfaces – Sony/Philips Digital Interconnect Format (S/PDIF) – Asynchronous Sample Rate Converter (ASRC)
- Additional peripheral interfaces – One high-speed USB 3.0 controller with integrated PHY – One high-speed USB 2.0 controller with ULPI – Enhanced secure digital host controller (eSDHC/MMC/eMMC) – Three I2C controllers – Four FlexCAN modules – FlexTimer/PWM – SPI interface – QuadSPI controller – Two DUARTs – Six LPUART interfaces – Integrated flash controller supporting NAND and NOR flash – Display controller unit (2D-ACE) 24-bit RGB (12- bit DDR pin interface) – TDM interface – Four GPIO controllers supporting up to 109 general purpose I/O signals – One 4-channel qDMA controller and one eDMA controller – Global programmable interrupt controller (GIC) – Thermal monitoring unit (TMU)
- QUICC Engine ULite block – 32-bit RISC controller for flexible support of the communications peripherals – Serial DMA channel for receive and transmit on all serial channels – Two universal communication controllers (TDM and HDLC) supporting 64 multichannels, each running at 64 Kbps
- 525 FC-PBGA package, 19 mm x 19 mm NXP Semiconductors Document Number LS1021A Data Sheet: Technical Data Rev. 5, 09/2017 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
3.11 Ethernet interface, Ethernet management interface, IEEE Std
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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1 Introduction
A member of the Layerscape (LS1) series, the LS102xA family is a cost-effective, power-efficient, and highly integrated system-on-chip (SoC) design that extends the reach of the NXP value-performance line of QorIQ communications processors. Featuring a pair of extremely power-efficient 32-bit Arm® Cortex®-A7 cores with ECC- protected L1 and L2 cache memories for high reliability, running up to 1 GHz, and providing pre-silicon CoreMark® performance of over 5,000, the LS102xA family delivers greater performance than any previous sub-4W communication processor. This chip can be used for networking and wireless access points, industrial gateways, industrial automation, printing, imaging, and M2M for enterprise and consumer networking and router applications. This figure shows the block diagram of the LS1021A chip. Introduction QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 3
512 KB Coherent L2 Cache
Figure 1. LS1021A block diagram
2 Pin assignments
4, Figure 5, and Figure 6 show quadrant views.
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Figure 2. Complete BGA Map for the LS1021A
Figure 3. Detail A
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Figure 4. Detail B
Figure 5. Detail C
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Figure 6. Detail D
2.1.2 Pinout list
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- Functionally, this pin is an output or an input, but structurally it is an I / O because it
test functions. This pin will therefore be described as an I / O for boundary scan.
- This output is actively driven during reset rather than being tri-stated during reset.
- MDIC[0] is grounded through an 162Ω precision 1% resistor and MDIC[1] is
IOs. The MDIC[0:1] pins must be connected to 162Ω precision 1% resistors.
- This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. The internal pull-up resistor value for applicable IFC pins is ~33kΩ. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed. 5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset. 6. Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the respective power supply. 7. This pin is an open-drain signal. 8. Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply. 9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled. 10. These are test signals for factory use only and must be pulled up (100Ω to 1-kΩ) to the respective power supply for normal operation. 11. This pin requires a 200Ω pull-up to respective power-supply. 12. Do not connect. These pins should be left floating. 14. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 15. These pins must be pulled to ground (GND). 16. This pin requires a 698Ω pull-up to respective power-supply. 17. CLK12 is connected to CLK8 internally. 19. These pins should be tied to ground if the diode is not utilized for temperature monitoring. 20. These pins must be connected to S1GND. 21. Must be pulled down during power-on reset. 22. This pin has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. This pin should have an optional pull down resistor 4.7 kΩ on board. This is required to support DIFF_SYSCLK/DIFF_SYSCLK_B. LS1021A Ball Map and Pin List QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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- Connect to ground when fuses are read-only. 24. For boundary scan, TEST_SEL_B and PORESET_B pins must be pulled to ground (GND), and SCAN_MODE_B and EVT2_B pins must be pulled up. 27. The prime DQ bit of the DRAM must connect to 1 of the ECC[0:3] pins. In addition, if using a 16-bit data bus in DDR4 mode, then DQ[0:1] of the DRAM must connect to ECC[0:1] pins. The prime DQ bit of the DRAM is defined as DQ[0] for some DRAM vendors and any of DQ bits for other DRAM vendors. 28. TH_VDD must be tied to the recommended supply level per the Recommended operating conditions section. 31. The permissible voltage range is 0-5.5 V. Warning See "Connection Recommendations" for additional details on properly connecting these pins for specific applications.
3 Electrical characteristics
This section describes the DC and AC electrical specifications for the chip. The chip is currently targeted to these specifications, some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer design specifications.
3.1 Overall DC electrical characteristics
This section describes the ratings, conditions, and other characteristics.
3.1.1 Absolute maximum ratings
This table provides the absolute maximum ratings. Table 2. Absolute maximum ratings 1 Table continues on the next page...
Electrical characteristics
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 51
Table 2. Absolute maximum ratings 1 (continued) Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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- Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional
- Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
- Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
- Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
- (S,B,L,O,D,E)VIN, USBn_HVIN, and Dn_MVREF may overshoot/undershoot to a voltage and for a maximum duration as
- Caution: DVIN must not exceed DVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
- Caution: EVIN must not exceed EVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
- Caution: BVIN must not exceed BVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
- Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
- See the power supply column in Table 1 to determine which power supply rail is used for each interface.
- Typical DDR interface uses ODT enabled mode. For tests purposes with ODT off mode, simulation should be done first
undershoot period should comply with JEDEC standards.
3.1.2 Recommended operating conditions
This table provides the recommended operating conditions for this chip. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 53
The values shown are the recommended operating conditions and proper device operation outside these conditions is not guaranteed. Table 3. Recommended operating conditions
1.8 V ± 90 mV V —
1.35 V ± 67 mV V —
3.3 V ± 165 mV
1.8 V ± 90 mV
1.8 V ± 90mV
2.5 V ± 125 mV
Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 3. Recommended operating conditions (continued) QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 55
- TA_PROG_SFP must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range
to the power sequencing constraints shown in Power sequencing.
- Refer to Core and platform supply voltage filtering for additional information.
- Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
- Operation at 1.1 V is allowable for up to 25 ms at initial power on.
- See the power supply column in Table 1 to determine which power supply rail is used for each interface.
- LVDD and L1VDD must always be the same voltage. This also applies to DVDD and D1VDD
- AVDD_PLAT, AVDD_CGA1 and AVDD_D1 are measured at the input to the filter (as shown in AN4971) and not at the pin
This figure shows the undershoot and overshoot voltages at the interfaces of the chip. less than 10% of the SYSCLK period. Figure 7. Overshoot/undershoot voltage for G1VDD/L1VDD/O1VDD/OVDD/X1VDD/ QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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See Table 3 for actual recommended core voltage. Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. DVDD-, OVDD-, and LVDD-based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied Dn_MVREF signal (nominally set to G1VDD/2) as is appropriate for the SSTL_1.35/SSTL_1.2 electrical signaling standard. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
3.1.3 Output driver characteristics
This table provides information on the characteristics of the output driver strengths. Note that these values are preliminary estimates. Table 4. Output driver capability
- The drive strength of the DDR4 or DDR3L interface in half-strength mode is at Tj = 105 °C and at G1VDD (min).
- Estimated number based on best case processed device.
- Estimated number based on worst case processed device.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 57
3.2 Power sequencing
Apply the power rails in a specific sequence to ensure proper device operation. The required power-up sequence is as follows: Table 5. Power-up sequence
- BVDD, AVDD_CGA1, AVDD_PLAT, AVDD_D1, O1VDD, OVDD, D1VDD, DVDD, L1VDD, LVDD, EVDD,
TH_VDD, USB_HVDD. Drive PROG_SFP = GND.
- VDDC, VDD, S1VDD, TA_BB_VDD, USB1_SPVDD, USB1_SDVDD, USB1_SXVDD 2, 3
- G1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2, X1VDD 4, 5
- PORESET_B should be driven, asserted, and held during this step.
- When deep sleep mode is used, VDDC should ramp up before VDD. Alternatively, VDD may ramp up together with VDDC
provided that the relative timing between VDDC and VDD ramp up conforms to Figure 8.
- When deep sleep is not used, it is recommended source VDD and VDDC from the same power supply.
- When using DDR4, AVDD_SD1_PLL1, AVDD_SD1_PLL2, X1VDD may ramp up with step 1 supplies.
- When using DDR3L, all supplies in step 3 above may be sourced from the same supply.
Table 6. Sequence for exiting deep sleep mode
- USB_HVDD, BVDD, AVDD_CGA1, AVDD_D1, DVDD, LVDD, EVDD, TH_VDD 1
- VDD, S1VDD, TA_BB_VDD, USB1_SPVDD, USB1_SDVDD, USB1_SXVDD
- G1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2, X1VDD 2, 3
- PORESET_B should be driven, asserted, and held during this step.
- When using DDR4, AVDD_SD1_PLL1, AVDD_SD1_PLL2, X1VDD may ramp up with step 1 supplies.
- When using DDR3L, all supplies in step 3 above may be sourced from the same supply.
All supplies must be at their stable values within 400 ms. table in section Power-on ramp rate. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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The supplies mentioned as OFF in the "Power Domain in Deep Sleep" column of Table 3 are switched ON during exit from deep sleep power management mode. These supplies should also follow the same power up sequence as mentioned above. NOTE
- While VDD is ramping, current may be supplied from VDD through the LS1021A to G1VDD.
- EVT2_B may be unstable when PORESET_B is asserted. The signal should not be used to enable switchable power supplies during this period.
- Ramp rate requirements should be met per section Power- on ramp rate. NOTE Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary. This figure shows the VDDC and VDD ramp-up diagram. VDD VDDC 10% 90% 90% 10% T1 <= 1 us T2 <= 1 us
Figure 8. VDDC and VDD ramp-up diagram QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 59
For secure boot fuse programming, use the following steps: 1. After negation of PORESET_B, drive TA_PROG_SFP = 1.8 V after a required minimum delay per Table 7. 2. After fuse programming is complete, it is required to return TA_PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 7. See Security fuse processor for additional details. 3. If using trust architecture security monitor battery backed features, prior to VDD ramping up to the 0.5V level, ensure that OVDD is ramped to recommended operational voltage and SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B is running. These clocks should have a minimum frequency of 800Hz and a maximum frequency no greater than the supported system clock frequency for the device. Warning No activity other than that required for secure boot fuse programming is permitted while TA_PROG_SFP is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while TA_PROG_SFP = GND. This figure shows the TA_PROG_SFP timing diagram. TA_PROG_SFP VDD PORESET_B 90% OVDD Fuse programming tTA_PROG_SFP_PROG NOTE: TA_PROG_SFP must be stable at 1 .8 V prior to initiating fuse programming. tTA_PROG_SFP_DELAY 10% TA_PROG_SFP tTA_PROG_SFP_RST tTA_PROG_SFP_VDD 10% TA_PROG_SFP 90% VDD 90% OVDD Figure 9. TA_PROG_SFP timing diagram Table 7. TA_PROG_SFP timing 5 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 7. TA_PROG_SFP timing 5 (continued)
- Delay required from the deassertion of PORESET_B to driving TA_PROG_SFP ramp up. Delay measured from
PORESET_B deassertion at 90% OVDD to 10% TA_PROG_SFP ramp up.
- Delay required from fuse programming completion to TA_PROG_SFP ramp down start. Fuse programming must complete
- Delay required from TA_PROG_SFP ramp-down complete to VDD ramp-down start. TA_PROG_SFP must be grounded to
minimum 10% TA_PROG_SFP before VDD reaches 90% VDD.
- Delay required from TA_PROG_SFP ramp-down complete to PORESET_B assertion. TA_PROG_SFP must be grounded
to minimum 10% TA_PROG_SFP before PORESET_B assertion reaches 90% OVDD.
- Only two secure boot fuse programming events are permitted per lifetime of a device.
3.3 Power-down requirements
before a new power-up cycle can be started. specified in Power sequencing.
3.4 Power characteristics
operating platform clock frequencies versus the core and DDR clock frequencies. Table 8. Core power dissipation Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 61
Table 8. Core power dissipation (continued)
- Combined power of VDD, VDDC, S1VDD, and TA_BB_VDD with DDR controller and all SerDes banks active. Does not
- Typical power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform
- Typical power based on nominal processed device.
- Maximum power assumes multicore Dhrystone running with a 100% activity factor and executing DMA on the platform with
- Maximum power is provided for power supply design sizing.
- Thermal power assumes multicore Dhrystone running with an 80% activity factor and executing DMA on the platform with
- Thermal and maximum power are based on worst-case processed device.
3.4.1 Low power mode saving estimation
Refer to this table for low power mode savings. Table 9. Low power mode savings, 1.0 V, 65C 1, 2, 3
800 MHz
1.0 GHz
1.2 GHz
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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- Typical power assumes Dhrystone running with activity factor of 80%
- Typical power based on nominal process distribution for this device.
- PW15 power savings with 1 core. Maximum savings would be N times, where N is the number of used cores.
- LPM20 has all platform clocks disabled.
- VDD and S1VDD are switched off during deep sleep mode.
3.5 I/O DC power supply recommendation
numbers listed below are based on design estimates only. Table 10. Estimated I/O power supply values values Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 63
Table 10. Estimated I/O power supply values values (continued) Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 65
- The maximum values are dependent on actual use case such as what application, external components used,
simulations at 105 °C junction temperature.
- Typical DDR power numbers are based on one 2-rank DIMM with 40% utilization.
- Assuming 15pF total capacitance load.
- Maximum DDR power numbers are based on one 2-rank DIMM with 100% utilization.
- The typical values are estimates and based on simulations at nominal recommended voltage for the IO power supply and
assuming at 65° C junction temperature.
- The total power numbers of X1VDD is dependent on customer application use case. This table lists all the SerDes
to the total SerDes Lanes used, not simply multiply the power numbers by the number of lanes.
- The maximum values are dependent on actual use case such as what application, external components used,
simulations at 105°C junction temperature. Table 11. TA_BB_VDD power dissipation
- When SoC is off, TA_BB_VDD may be supplied by battery power to retain the Zeroizable Master Key and other trust
the Device reference manual trust architecture chapter for more information. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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3.6 Power-on ramp rate
This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum power-on ramp rate is required to avoid excess in-rush current. This table provides the power supply ramp rate specifications. Table 12. Power supply ramp rate
- Ramp rate is specified as a linear ramp from 10% to 90%. If non-linear (for example, exponential), the maximum rate of
change from 200 mV to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
- Over full recommended operating temperature range. See Table 3.
3.7 Input clocks
3.7.1 System clock (SYSCLK)
3.7.1.1 SYSCLK DC electrical characteristics
This table provides the SYSCLK DC characteristics. Table 13. SYSCLK DC electrical characteristics 3
- The min VILand max VIH values are based on the respective min and max O1VIN values found in Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 67
- The symbol OVIN, in this case, represents the O1VIN symbol referenced in Table 3.
- At recommended operating conditions with O1VDD = 1.8 V. See Table 3.
3.7.1.2 SYSCLK AC timing specifications
This table provides the SYSCLK AC timing specifications. Table 14. SYSCLK AC timing specifications 1, 5
- Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequencies do not exceed their
respective maximum or minimum operating frequencies.
- Measured at the rising edge and/or the falling edge at O1VDD/2.
- Slew rate as measured from 0.35 x O1VDD to 0.65 x O1VDD.
- Phase noise is calculated as FFT of TIE jitter.
- At recommended operating conditions with O1VDD = 1.8 V. See Table 3.
3.7.2 Spread-spectrum sources
diffuse the EMI spectral content. The jitter specification given in this table considers short-term (cycle-to-cycle) jitter only. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Frequency modulation and spread are separate concerns; the chip is compatible with spread-spectrum sources if the recommendations listed in this table are observed. Table 15. Spread-spectrum clock source recommendations 3
- SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Table 14.
- Maximum spread-spectrum frequency may not result in exceeding any maximum operating frequency of the device.
- At recommended operating conditions with O1VDD = 1.8 V. See Table 3.
3.7.3 Real-time clock timing (RTC)
This table provides the real-time clock recommendations. Table 16. Real-time clock recommendations
3.7.4 Gigabit Ethernet reference clock timing
Table 17. EC n_GTX_CLK125 DC electrical characteristics (L1VDD/LVDD = 1.8 V)1 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 69
- For recommended operating conditions, see Table 3.
- The min VIL and max VIH values are based on the respective min and max VIN values found in Table 3.
- The symbol VIN, in this case, represents the L1VIN/LVIN symbol referenced in Table 3.
Table 18. EC n_GTX_CLK125 DC electrical characteristics (L1VDD/LVDD = 2.5 V)1
- For recommended operating conditions, see Table 3.
- The min VIL and max VIH values are based on the respective min and max VIN values found in Table 3.
- The symbol VIN, in this case, represents the L1VIN/LVIN symbol referenced in Table 3.
This table provides the Ethernet gigabit reference clock AC timing specifications. Table 19. EC n_GTX_CLK125 AC timing specifications 1, 4 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 19. EC n_GTX_CLK125 AC timing specifications 1, 4 (continued)
- ECn_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter with 2% degradation. The
- The frequency of ECn_RX_CLK (input) should not exceed the frequency of EC_GTX_CLK125/ECn_TX_CLK (input) by
3.7.5 DDR clock (DDRCLK)
3.7.5.1 DDRCLK DC electrical characteristics
This table provides the DDRCLK DC electrical characteristics. Table 20. DDRCLK DC electrical characteristics 3
- The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
- The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3.
- At recommended operating conditions with OVDD = 1.8 V. See Table 3.
3.7.5.2 DDRCLK AC timing specifications
This table provides the DDRCLK AC timing specifications. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 71
Table 21. DDRCLK AC timing specifications 5
- Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequencies do not exceed
their respective maximum or minimum operating frequencies.
- Measured at the rising edge and/or the falling edge at OVDD/2.
- Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD.
- Phase noise is calculated as FFT of TIE jitter.
- At recommended operating conditions with OVDD = 1.8V. See Table 3.
3.7.6 Differential system clock (DIFF_SYSCLK/DIFF_SYSCLK_B)
clock input to the differential system clock pair, DIFF_SYSCLK/DIFF_SYSCLK_B. Figure 10. LVDS receiver
3.7.6.1 Differential system clock DC electrical characteristics
are specified in Recommended operating conditions. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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The differential system clock can also be single-ended. For this, DIFF_SYSCLK_B should be connected to O1VDD/2. Table 22. Differential system clock DC electrical characteristics
- At recommended operation conditions with O1VDD=1.8V.
- The die capacitance may cause reflection of the clock signal through the package back to the pin. This should not affect
the signal quality seen by internal PLL. Recommend verifying signal quality using IBIS simulations.
- Input differential voltage swing (Vid) specified is equal to |VDIFF_SYSCLK_P - VDIFF_SYSCLK_N|
3.7.6.2 Differential system clock AC timing specifications
Spread-spectrum clocking is not supported on differential system clock pair input. Table 23. Differential system clock AC electrical characteristics 2, 3
- At recommended operating conditions with O1VDD=1.8 V.
- This is evaluated with supply noise profile at ±5% sine wave.
- The 100 MHz reference frequency is needed if USB is used. The reference clock to USB PHY is selectable between
SYSCLK or DIFF_SYSCLK/DIF_SYSCLK_B. The selected clock must meet the clock specifications for USB. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 73
3.7.7 Other input clocks
A description of the overall clocking of this device is available in the chip reference manual in the form of a clock subsystem block diagram. For information about the input clock requirements of functional modules sourced external of the chip, such as SerDes, Ethernet management, eSDHC, and IFC, see the specific interface section.
3.8 RESET initialization
This table provides the AC timing specifications for the RESET initialization timing. Table 24. RESET initialization timing specifications
- PORESET_B must be driven asserted before the core and platform power supplies are powered up.
- SYSCLK is the primary clock input for the chip.
- The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The
documented in the reference manual's "Power-on Reset Sequence" section.
- The system/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
- For HRESET_B the rise/fall time should not exceed 10 SYSCLKs. Rise time refers to signal transitions from 20% to 70% of
O1VDD. Fall time refers to transitions from 70% to 20% of O1VDD.
- For PORESET_B the rise/fall time should not exceed 1 SYSCLK. Rise time refers to signal transitions from 20% to 70% of
O1VDD. Fall time refers to transitions from 70% to 20% of O1VDD.
- For proper clock selection, terminate cfg_eng_use0 with a pull up or pull down of 4.7 kΩ to ensure that the signal has a
valid state as soon as the IO voltage reaches its operating condition. This table provides the phase-locked loop (PLL) lock times. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 25. PLL lock times
3.9 DDR3L and DDR4 SDRAM controller
3.9.1 DDR3L and DDR4 SDRAM interface DC electrical
controller when interfacing to DDR3L SDRAM. Table 26. DDR3L SDRAM interface DC electrical characteristics (G1V DD = 1.35 V)1, 8
- G1VDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
- Dn_MVREF is expected to be equal to 0.5 x G1VDD and to track G1VDD DC variations as measured at the receiver. Peak-
to-peak noise on Dn_MVREF may not exceed the Dn_MVREF DC level by more than ±1% of G1VDD (that is, ±13.5 mV).
- VTT is not applied directly to the device. It is the supply to which far-end signal termination is made, and it is expected to be
- The voltage regulator for Dn_MVREF must meet the specifications stated in Table 28.
- Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
- Output leakage is measured with all outputs disabled (0 V ≤ VOUT ≤ G1VDD).
- Refer to the IBIS model for the complete output IV curve characteristics.
- For recommended operating conditions, see Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 75
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR4 SDRAM. Table 27. DDR4 SDRAM interface DC electrical characteristics (G1V DD = 1.2 V)1, 5
- G1VDD is expected to be within 60 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
- Input capacitance load for MDQ, MDQS, and MDQS_B are available in the IBIS models.
- Output leakage is measured with all outputs disabled (0 V ≤ VOUT ≤ G1VDD).
- Refer to the IBIS model for the complete output IV curve characteristics.
- For recommended operating conditions, see Table 3.
- VTT and VREFCA are applied directly to the DRAM device. Both VTT and VREFCA voltages must track G1VDD/2.
- Internal Vref for data bus must be set to 0.7 x G1VDD.
This table provides the current draw characteristics for Dn_MVREF. Table 28. Current draw characteristics for D n_MVREF1
- For recommended operating conditions, see Table 3.
3.9.2 DDR3L and DDR4 SDRAM interface AC timing specifications
3.9.2.1 DDR3L and DDR4 SDRAM interface input AC timing specifications
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 29. DDR4 SDRAM interface input AC timing specifications (GV DD = 1.2 V ± 5%)4 interfacing to DDR3L and DDR4 SDRAM. Table 30. DDR3L and DDR4 SDRAM interface input AC timing specifications 3
1600 MT/s data rate -112 112 1
1333 MT/s data rate -125 125 1
1200 MT/s data rate -142 142 1, 3
1000 MT/s data rate -170 170 1, 3
1600 MT/s data rate -200 200 2
1333 MT/s data rate -250 250 2
1200 MT/s data rate -275 275 2, 3
1000 MT/s data rate -300 300 2, 3
- tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This must be subtracted from the total timing budget.
- The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
This figure shows the DDR3L and DDR4 SDRAM interface input timing diagram. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 77
MCK_B[n] MCK[n] MDQS[n] MDQ[x] tDISKEW tDISKEW tDISKEW D0 D1 Figure 11. DDR3L and DDR4 SDRAM interface input timing diagram
3.9.2.2 DDR3L and DDR4 SDRAM interface output AC timing
Table 31. DDR3L and DDR4 SDRAM interface output AC timing specifications 7
1600 MT/s data rate 495 — 3
1333 MT/s data rate 606 — 3
1200 MT/s data rate 675 — 3, 6
1000 MT/s data rate 744 — 3, 6
1000 MT/s data rate, ≤ 1600MT/s data rate -245 245 4, 7
Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 31. DDR3L and DDR4 SDRAM interface output AC timing specifications 7 (continued)
1600 MT/s data rate 400 — 5
1333 MT/s data rate 500 — 5
1200 MT/s data rate 550 — 5, 6
1000 MT/s data rate 600 — 5, 6
- The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state) (reference)(state) for
low (L) until data outputs (D) are invalid (X) or data output hold time.
- All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals. Note:
The range of operating frequency for MCK are part dependent, enter the range that applies to your part.
- ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.
- tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from
modifications enabled by the use of these bits.
- Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.
- It is required to program the start value of the DQS adjust for write leveling. Note: tDDKHMH is required to program the
is why the tDDKHMH numbers for 1200/1333/1600 consume a higher percentage of the timing budget. memory clocks by ½ applied cycle. to MDQS skew measurement (tDDKHMH). QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 79
MCK_B[n] MCK[n] MDQS MDQS tDDKHMH(max) tDDKHMH(min) Figure 12. tDDKHMH timing diagram This figure shows the DDR3L and DDR4 SDRAM output timing diagram. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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MCK_B MCK MDQS[n] MDQ[x] tDDKXDEYE D0 D1 tDDKHMH tDDKHME tDDKHMP ADDR/CMD Write A0 NOOP tDDKHAS tDDKHAX tDDKXDEYE Figure 13. DDR3L and DDR4 output timing diagram
3.10 DUART interface
This section describes the DC and AC electrical specifications for the DUART interface.
3.10.1 DUART DC electrical characteristics
Table 32. DUART DC electrical characteristics (3.3 V) 3 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 81
Table 32. DUART DC electrical characteristics (3.3 V) 3 (continued)
- The min VILand max VIH values are based on the respective min and max DVIN/D1VIN values found in Table 3.
- The symbol DVIN/D1VIN represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 33. DUART DC electrical characteristics (1.8 V) 3
- The min VILand max VIH values are based on the min and max DVIN/D1VIN respective values found in Table 3.
- The symbol DVIN/D1VIN represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.10.2 DUART AC timing specifications
This table provides the AC timing specifications for the DUART interface. Table 34. DUART AC timing specifications
- fPLAT refers to the internal platform clock.
- The actual attainable baud rate is limited by the latency of interrupt processing.
- The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each 16th sample. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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3.11 Ethernet interface, Ethernet management interface, IEEE
Std 1588™ This section describes the DC and AC electrical characteristics for the Ethernet controller, Ethernet management, and IEEE Std 1588 interfaces.
3.11.1 SGMII interface
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 14, where CTX is the external (on board) AC-coupled capacitor. Each SerDes transmitter differential pair features 100-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XGNDn. The reference circuit of the SerDes transmitter and receiver is shown in Figure 81.
3.11.1.1 SGMII clocking requirements for SD1_REF_CLK1_P and
SD1_REF_CLK1_N When operating in SGMII mode, the ECn_GTX_CLK125 clock is not required for this port. Instead, a SerDes reference clock is required on SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N pins. SerDes lanes may be used for SerDes SGMII configurations based on the RCW Configuration field SRDS_PRTCL. For more information on these specifications, see SerDes reference clocks.
3.11.1.2 SGMII DC electrical characteristics
This section describes the electrical characteristics for the SGMII interface.
3.11.1.2.1 SGMII transmit DC electrical characteristics
This table provides the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N), as shown in Figure 15. Table 35. SGMII DC transmitter electrical characteristics (X1V DD = 1.35 V)4 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 83
Table 35. SGMII DC transmitter electrical characteristics (X1V DD = 1.35 V)4 (continued)
- This does not align to DC-coupled SGMII.
- │VOD│ = │VSD_TXn_P - VSD_TXn_N│. │VOD│ is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 x │VOD│.
- The │VOD│ value shown in the Typ column is based on the condition of X1VDD-Typ = 1.35 V, no common mode offset
variation. SerDes transmitter is terminated with 100-Ω differential load between SDn _TXn_P and SDn_TXn_N.
- For recommended operating conditions, see Table 3.
- Example amplitude reduction setting for SGMII on SerDes1 lane E: SRDS1LN4TECR0[AMP_RED] = 0b000001 for an
output differential voltage of 459 mV typical. This figure shows an example of a 4-wire AC-coupled SGMII serial link connection. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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100 Ω 50 Ω 50 Ω Transmitter SGMII SerDes Interface SDn_TXn_P SDn_TXn_N SDn_RXn_N SDn_RXn_P CTX CTX Receiver 100 Ω 50 Ω 50 Ω Transmitter SDn_TXn_P SDn_TXn_NSDn_RXn_N SDn_RXn_P CTX CTX Receiver Figure 14. 4-wire AC-coupled SGMII serial link connection example This figure shows the SGMII transmitter DC measurement circuit. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 85
100 Ω 50 Ω 50 Ω Transmitter SGMII SerDes Interface SDn_TXn_P SDn_TXn_N VOD Figure 15. SGMII transmitter DC measurement circuit
3.11.1.2.2 SGMII receiver DC electrical characteristics
clocking is not supported. Clock is recovered from the data. Table 36. SGMII receiver DC electrical characteristics (S1V DD = 1.0V)4
- Input must be externally AC coupled.
- VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
- The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. For further
- For recommended operating conditions, see Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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3.11.1.3 SGMII AC timing specifications
This section describes the AC timing specifications for the SGMII interface.
3.11.1.3.1 SGMII transmit AC timing specifications
This table provides the SGMII transmit AC timing specifications. Source-synchronous clocking is not supported. The AC timing specifications do not include RefClk jitter. Table 37. SGMII transmit AC timing specifications 4
- See Figure 17 for single frequency sinusoidal jitter measurements.
- The external AC coupling capacitor of 100 nF is required. It is recommended to place it near the device transmitter outputs.
- For recommended operating conditions, see Table 3.
3.11.1.3.2 SGMII AC measurement details
SDn_RXn_N) respectively, as shown in this figure. Figure 16. SGMII AC test/measurement load QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 87
3.11.1.3.3 SGMII receiver AC timing specifications
This table provides the SGMII receiver AC timing specifications. Source-synchronous clocking is not supported. Clock is recovered from the data. These AC timing specifications do not include RefClk jitter. Table 38. SGMII Receive AC timing specifications 3
- Measured at the receiver.
- Total jitter tolerance is composed of three components: deterministic jitter, random jitter, and single-frequency sinusoidal
component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
- For recommended operating conditions, see Table 3.
the unshaded region of this figure. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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0.10 UI p-p
20 MHz
8.5 UI p-p
Figure 17. Single-frequency sinusoidal jitter limits
3.11.2 RGMII electrical specifications
This section describes the electrical characteristics for the RGMII interface.
3.11.2.1 RGMII DC electrical characteristics
Table 39. RGMII DC electrical characteristics (LV DD, L1VDD = 2.5 V)4
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
- The symbol LVIN, in this case, represents the LVIN and L1VIN symbol referenced in Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 89
- The symbol LVDD, in this case, represents the LVDD and L1VDD symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 40. RGMII DC electrical characteristics (LV DD, L1VDD = 1.8 V)4
- The min VILand max VIH values are based on the min and max LVIN values found in Table 3.
- The symbol LVIN, in this case, represents the LVIN and L1VIN symbol referenced in Table 3.
- The symbol LVDD, in this case, represents the LVDD and L1VDD symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.11.2.2 RGMII AC timing specifications
This table provides the RGMII AC timing specifications. Table 41. RGMII AC timing specifications (LV DD, L1VDD = 2.5 /1.8 V)8 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 41. RGMII AC timing specifications (LV DD, L1VDD = 2.5 /1.8 V)8 (continued)
- In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
- This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
additional PCB delay is probably not needed.
- For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
- Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
- Applies to inputs and outputs.
- The system/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
- The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than
- For recommended operating conditions, see Table 3.
This figure shows the RGMII AC timing and multiplexing diagrams. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 91
GTX_CLK tRGT tRGTH tSKRGT_TX TX_CTL TXD[8:5] TXD[7:4] TXD[9] TXERR TXD[4] TXEN TXD[3:0] (At MAC, output) TXD S[8:5][3:0] TXD[7:4][3:0] TX_CLK (At PHY, input) RX_CTL RXD[8:5] RXD[7:4] RXD[9] RXERR RXD[4] RXDV RXD[3:0] RX_CLK (At MAC, input) tSKRGT_RX tRGTH tRGT RX_CLK (At PHY, output) RXD[8:5][3:0] RXD[7:4][3:0] tSKRGT_RX PHY equivalent to t SKRGT_TX tSKRGT_TX PHY equivalent to t SKRGT_RXPHY equivalent to t SKRGT_RX (At MAC, output) (At MAC, output) (At PHY, output) (At PHY, output) PHY equivalent to t SKRGT_TX Figure 18. RGMII AC timing and multiplexing diagrams designers must ensure delays needed at the PHY or the MAC.
3.11.3 MII, RMII electrical specifications
This section describes the electrical characteristics for the MII and RMII interfaces.
3.11.3.1 MII, RMII DC electrical characteristics
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 42. MII and RMII DC electrical characteristics
- The min VIL and max VIH values are based on the respective min and max L1VIN values found in Table 3
- The symbol VIN, in this case, represents the L1VIN symbol referenced in Table 3
3.11.3.2 MII AC timing specifications
This table describes the MII transmit and receive AC timing specifications. Table 43. MII transmit AC timing specifications This figure shows the MII transmit AC timing diagram. Figure 19. MII transmit AC timing diagram This table provides the MII receive AC timing specifications. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 93
Table 44. MII receive AC timing specifications 1
- The frequency of RX_CLK (input) should not exceed the frequency of TX_CLK (input) by more than 300 ppm.
This figure shows the AC test load for the Ethernet controller. Figure 20. Ethernet controller AC test load This figure shows the MII receive AC timing diagram. Figure 21. MII receive AC timing diagram QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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3.11.4 RMII AC timing specifications
In RMII mode, the reference clock should be fed to TSECn_TX_CLK. This section describes the RMII transmit and receive AC timing specifications. This table provides the RMII transmit AC timing specifications. Table 45. RMII transmit AC timing specifications 1 This figure shows the RMII transmit AC timing diagram. Figure 22. RMII transmit AC timing diagram This table provides the RMII receive AC timing specifications. Table 46. RMII receive AC timing specifications 1 This figure shows the AC test load for Ethernet controller. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 95
Output Z0= 50 Ω RL = 50 Ω LVDD/2 Figure 23. Ethernet controller AC test load This figure shows the RMII receive AC timing diagram. Figure 24. RMII receive AC timing diagram
3.11.5 Ethernet management interface 1 (EMI1)
This section describes the electrical characteristics for the EMI1 interface. The EMI1 interface timing is compatible with IEEE Std 802.3™ clause 22.
3.11.5.1 EMI1 DC electrical characteristics
This table provides the EMI1 DC electrical characteristics when L1VDD = 3.3 V. Table 47. EMI1 DC electrical characteristics (L1V DD = 3.3 V) 2 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 47. EMI1 DC electrical characteristics (L1V DD = 3.3 V) 2 (continued)
- The min VILand max VIH values are based on the respective min and max L1VIN values found in Table 3.
- For recommended operating conditions, see Table 3.
This table provides the EMI1 DC electrical characteristics when L1VDD = 2.5 V. Table 48. EMI1 DC electrical characteristics (L1V DD = 2.5 V)2
- The min VILand max VIH values are based on the respective min and max L1VIN values found in Table 3.
- For recommended operating conditions, see Table 3.
This table provides the EMI1 DC electrical characteristics when L1VDD = 1.8 V. Table 49. EMI1 DC electrical characteristics (L1V DD = 1.8 V)2
- The min VILand max VIH values are based on the min and max L1VIN respective values found in Table 3.
- For recommended operating conditions, see Table 3.
3.11.5.2 EMI1 AC timing specifications
This table provides the EMI1 AC timing specifications. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 97
Table 50. EMI1 AC timing specifications 5
- The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
- This parameter is dependent on the Ethernet clock frequency. The eTSEC_MDIO_MIIMCFG[MgmtClk} field determines
the clock frequency of the MII management clock.
- This parameter is dependent on the Ethernet clock frequency (CCB clock)/2. The delay is equal to 3 Ethernet clock periods
± 3 ns. For example, with an Ethernet clock of 400 MHz, the min/max delay is 12.5 ns ± 3 ns.
- tenet_clk is the Ethernet clock period (Ethernet clock period x 2).
- For recommended operating conditions, see Table 3.
3.11.6 IEEE 1588 electrical specifications
3.11.6.1 IEEE 1588 DC electrical characteristics
Table 51. IEEE 1588 DC electrical characteristics(LV DD = 2.5 V)3
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
- The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 52. IEEE 1588 DC electrical characteristics(LV DD = 1.8 V)3
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
- The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.11.6.2 IEEE 1588 AC timing specifications
This table provides the IEEE 1588 AC timing specifications. Table 53. IEEE 1588 AC timing specifications 5
- TRX_CLK is the maximum clock period of the ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip
reference manual for a description of TMR_CTRL registers.
- This needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
- The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively.
- There are three input clock sources for 1588: TSEC_1588_CLK_IN, RTC, and MAC clock / 2. When using
TSEC_1588_CLK_IN, the minimum clock period is 2 x tT1588CLK. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 99
- For recommended operating conditions, see Table 3.
This figure shows the data and command output AC timing diagram. Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is counted starting at the falling edge. Figure 25. IEEE 1588 output AC timing This figure shows the data and command input AC timing diagram. Figure 26. IEEE 1588 input AC timing
3.12 QUICC engine specifications
3.12.1 HDLC interface
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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3.12.1.1 HDLC, transparent, and synchronous UART DC electrical
This table provides the DC electrical characteristics for the HDLC, transparent, and synchronous UART protocols when DVDD = 3.3 V. Table 54. HDLC, transparent, and synchronous UART DC electrical characteristics
- The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
- The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
synchronous UART protocols when DVDD = 1.8 V. Table 55. HDLC, transparent, and synchronous UART DC electrical characteristics
- The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
- The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.12.1.2 HDLC, transparent, and synchronous UART AC timing
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 101
Table 56. HDLC and transparent AC timing specifications 2
- Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
- For recommended operating conditions, see Table 3.
Table 57. Synchronous UART AC timing specifications 2
- Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
- For recommended operating conditions, see Table 3.
This figure shows the AC test load. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Serial CLK (output) Input Signals: (see Note) Output Signals: (see Note) Note: The clock edge is selectable. tHIIVKH tHIIXKH tHIKHOV tHIKHOX Figure 29. AC timing (internal clock) diagram
3.12.2 Time-division-multiplexed and serial interface (TDM/SI)
This section describes the DC and AC electrical specifications for the TDM/SI.
3.12.2.1 TDM/SI DC electrical characteristics
This table provides the TDM/SI DC electrical characteristics when DVDD = 3.3 V. Table 58. TDM/SI DC electrical characteristics (DV DD = 3.3 V)3
- The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
- The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
This table provides the TDM/SI DC electrical characteristics when DVDD = 1.8 V. Table 59. TDM/SI DC electrical characteristics (DV DD = 1.8 V)3 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 59. TDM/SI DC electrical characteristics (DV DD = 1.8 V)3 (continued)
- The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
- The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.12.2.2 TDM/SI AC timing specifications
This table provides the TDM/SI input and output AC timing specifications. Table 60. TDM/SI AC timing specifications 1
- Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
This figure shows the AC test load for the TDM/SI. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 105
Output Z0= 50 Ω RL = 50 Ω OVDD/2 Figure 30. TDM/SI AC test load also apply when the falling edge is the active edge. This figure shows the TDM/SI timing with an external clock. Note: The clock edge is selectable on TDM/SI. Figure 31. TDM/SI AC timing (external clock) diagram This section describes the AC and DC electrical specifications for the USB 2.0 interface. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 61. USB 2.0 DC electrical characteristics (3.3 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 62. USB 2.0 DC electrical characteristics (2.5 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN/L1VIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN/L1VIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 63. USB 2.0 DC electrical characteristics (1.8 V) 3 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 107
Table 63. USB 2.0 DC electrical characteristics (1.8 V) 3 (continued)
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 64. USB 2.0 general timing parameters (ULPI mode only) 1, 6, 7
- The symbols for timing specifications follow these patterns: t(First two letters of functional block)(signal)(state)(reference)(state) for inputs
timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold time.
- All timings are in reference to the USB 2.0 clock.
- All signals are measured from OVDD/2 of the rising edge of the USB 2.0 clock to 0.4 x OVDD of the signal in question for
- Input timings are measured at the pin.
- For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered
through the component pin is less than or equal to that of the leakage current specification. functionally looking at these signals on that cycle as per ULPI specifications.
- For recommended operating conditions, see Table 3.
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3.14 USB 3.0 interface This section describes the DC and AC electrical specifications for the USB 3.0 interface. 3.14.1 USB 3.0 PHY transceiver supply DC voltage This table provides the DC electrical characteristics for the USB 3.0 interface when operating at USB_HVDD = 3.3 V. Table 66. USB 3.0 PHY transceiver supply DC voltage (USB_HV DD = 3.3 V)2
- The min VILand max VIH values are based on the respective min and max USB_HVIN values found in Table 3.
- For recommended operating conditions, see Table 3.
This table provides the USB 3.0 transmitter DC electrical characteristics at package pins. Table 67. USB 3.0 transmitter DC electrical characteristics 1
- For recommended operating conditions, see Table 3.
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Table 68. USB 3.0 receiver DC electrical characteristics
25 K — — Ohm —
- Below the minimum is noise. Must wake up above the maximum.
This table provides the USB 3.0 transmitter AC timing specifications at package pins. Table 69. USB 3.0 transmitter AC timing specifications 1
- For recommended operating conditions, see Table 3.
- UI does not account for SSC-caused variations.
This table provides the USB 3.0 receiver AC timing specifications at Rx package pins. Table 70. USB 3.0 receiver AC timing specifications 1
- For recommended operating conditions, see Table 3.
- UI does not account for SSC-caused variations.
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3.14.4 USB 3.0 reference clock requirements This table summarizes the requirements of the reference clock provided to the USB 3.0 SSPHY. There are two options for the reference clock of USB PHY: SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B. The following table provides the additional requirements when SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B is used as USB REFCLK. This table can also be used for 100 MHz reference clock requirements. Table 71. Reference clock requirements
- 1.5 MHz to Nyquist frequency. For example, for 100 MHz reference clock, the Nyquist frequency is 50 MHz.
- The peak-to-peak Rj specification is calculated as 14.069 times the RMS Rj for 10-12 BER.
- DJ across all frequencies.
This table provides the key LFPS electrical specifications at the transmitter. Table 72. LFPS electrical specifications at the transmitter
- Measured at compliance TP1. See Figure 34 for details.
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Measurement Tool Reference Test Channel Reference Cable DUTSMP TP1 Figure 34. Tx normative setup
3.15 Integrated flash controller (IFC)
3.15.1 IFC DC electrical characteristics
Table 73. IFC DC electrical characteristics (3.3 V) 3
- The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
- The symbol VIN, in this case, represents the BVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 74. IFC DC electrical characteristics (1.8 V) 3 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 113
Table 74. IFC DC electrical characteristics (1.8 V) 3 (continued)
- The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
- The symbol VIN, in this case, represents the BVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.15.2 IFC AC timing specifications
This section describes the AC timing specifications for the IFC.
3.15.2.1 Test condition
This figure shows the AC test load for the IFC. Figure 35. IFC AC test load
3.15.2.2 IFC input AC timing specifications
Table 75. IFC input timing specifications for GPCM and GASIC mode (BV DD = 1.8/3.3 V) Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Figure 36. IFC-GPCM and IFC-GASIC input AC timings This table provides the input timing specifications of the IFC-NOR interface. Table 76. IFC input timing specifications for NOR mode (BV DD = 1.8/3.3 V)2
- tIP_CLK is the period of ip clock (not the IFC_CLK) on which IFC is running.
- For recommended operating conditions, see Table 3.
LS1021A QorIQ Advanced Multicore Processor Reference Manual for more information. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 115
OE_B AD (Data Phase, Read) (TRAD+1) x tIP_CLK tIBIVKH2 tIBIXKH2 Note: IP_CLK is the internal clock on which IFC is running. It is not available on interface pins. Figure 37. IFC-NOR interface input AC timings This table provides the input timing specifications of the IFC-NAND interface. Table 77. IFC input timing specifications for NAND mode (BV DD = 1.8/3.3 V)2
- tIP_CLK is the period of ip clock on which IFC is running.
- For recommended operating conditions, see Table 3.
LS1021A QorIQ Advanced Multicore Processor Reference Manual for more information. Note: tIP_CLK is the period of IP clock (not the IFC_CLK) on which IFC is running. Figure 38. IFC-NAND interface input AC timings QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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3.15.2.3 IFC output AC timing specifications
This table provides the output AC timing specifications of the IFC-GPCM and IFC- GASIC interface. Table 78. IFC-GPCM and IFC-GASIC interface output timing specifications (BV DD = 1.8/3.3
- Output hold is negative. This means that output transition happens earlier than the falling edge of IFC_CLK.
- For recommended operating conditions, see Table 3.
Figure 39. IFC-GPCM and IFC-GASIC signals This table provides the output AC timing specifications of the IFC-NOR interface. Table 79. IFC-NOR interface output timing specifications (BV DD = 1.8/3.3 V) QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 117
- This effectively means that a signal change may appear anywhere within ±tIBKLOV2 (max) duration, from the point where it
- For recommended operating conditions, see Table 3.
This figure shows the AC timing diagram for output signals of the IFC-NOR interface. Advanced Multicore Processor Reference Manual for more information. of the IFC-NOR interface, as well. Figure 40. IFC-NOR Interface output AC timings This table provides the output AC timing specifications of the IFC-NAND interface. Table 80. IFC-NAND interface output timing specifications (BV DD = 1.8/3.3 V)2
- This effectively means that a signal change may appear anywhere within tIBKLOV3 (min) to tIBKLOV3 (max) duration, from the
point where it is expected to change.
- For recommended operating conditions, see Table 3.
This figure shows the AC timing diagram for output signals of the IFC-NAND interface. Advanced Multicore Processor Reference Manual for more information. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Because of skew between the signals, CLE may change anywhere within the time window tIBKLOV3 (min) and tIBKLOV3 (max). This concept applies to other output signals of the IFC-NAND interface, as well. CS_B CLE TCCST tIBKLOV3 Figure 41. IFC-NAND interface output AC timings
3.15.3 IFC NAND Source Synchronous interface AC timing
Table 81. IFC-NAND Source Synchronous interface AC timing specifications (BV DD = 1.8/3.3 Absolute clock period tCK(abs) O tCK(avg)-0. Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 119
- tCK(avg) is the average clock period over any consecutive 200 cycle window.
- tCKH(abs) and tCKL(abs) include static off set and duty cycle jitter.
- tDQSL and tDQSH are relative to tCK when CLK is running . If CLK is stopped during data input, then tDQSL and tDQSH are
- For recommended operating conditions, see Table 3
- These AC parameters do not meet ONFI standard. The board designer needs to take into account trace length for these
signals to meet the timing requirement. These figures show the AC timing diagram for IFC-NAND source synchronous interface. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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CE# CLE ALE CLK W/R# DQS DQ[7:0] tCKL tCKH tCK tCAD tCALS tCALS tCALH tCALH tCH tDQSS tDSH tDSS tDSH tDQSHtDQSL tDQSH tDQSL tDQSH tDSS tDSH tDSS tDSH tDH tDS tDH D0 D1 tDS DN-2D3D2 DN-1 DN Figure 44. Write cycle Figure 45. Read cycle
3.16 LPUART interface
This section describes the DC and AC electrical specifications for the LPUART interface. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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3.16.1 LPUART DC electrical characteristics
This table provides the DC electrical characteristics for the LPUART interface when operating at DVDD = 3.3 V. Table 82. LPUART DC electrical characteristics (3.3 V) 2
- The min VILand max VIH values are based on the min and max DVDD respective values found in Table 3.
- For recommended operating conditions, see Table 3.
Table 83. LPUART DC electrical characteristics (1.8 V) 3
- The min VILand max VIH values are based on the min and max DVDD respective values found in Table 3.
- The symbol DVIN represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.16.2 LPUART AC timing specifications
This table provides the AC timing specifications for the LPUART interface. Table 84. LPUART AC timing specifications Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 123
- fPLAT refers to the internal platform clock.
- The actual attainable baud rate is limited by the latency of interrupt processing.
- Every bit can be over sampled with a sample clock rate of 8 and 64 times (software configurable) and each bit is the
majority of the values sampled at the sample rate divided by two, (sample rate/2)+1 and (sample rate/2)+2.
- The 1-to-0 transition during a data word can cause a resynchronization of the sample point.
3.17 Flextimer interface
interface. There are Flextimer pins on various power supplies in this device.
3.17.1 Flextimer DC electrical characteristics
Table 85. Flextimer DC electrical characteristics (3.3 V) 3
- The min VILand max VIH values are based on the respective min and max L/L1/D/BVIN values found in Table 3.
- The symbol VIN, in this case, represents the L/L1/D/BVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
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Table 86. Flextimer DC electrical characteristics (2.5 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN/L1VIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN/L1VIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 87. Flextimer DC electrical characteristics (1.8 V) 3
- The min VILand max VIH values are based on the respective min and max L/L1/D/BVIN values found in Table 3.
- The symbol VIN, in this case, represents the L/L1/D/BVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.17.2 Flextimer AC timing specifications
This table provides the Flextimer AC timing specifications. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 125
Table 88. Flextimer AC timing specifications 2
- Flextimer inputs and outputs are asynchronous to any visible clock. Flextimer outputs should be synchronized before use
by any external synchronous logic. Flextimer inputs are required to be valid for at least tPIWID to ensure proper operation.
- For recommended operating conditions, see Table 3.
This figure provides the AC test load for the Flextimer. Figure 46. Flextimer AC test load
3.18 FlexCAN interface
3.18.1 FlexCAN DC electrical characteristics
Table 89. FlexCAN DC electrical characteristics (3.3 V) 3 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 89. FlexCAN DC electrical characteristics (3.3 V) 3 (continued)
- The min VILand max VIH values are based on the respective min and max LVIN/L1VIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN/L1VIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 90. FlexCAN DC electrical characteristics (2.5 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN/L1VIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN/L1VIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 91. FlexCAN DC electrical characteristics (1.8 V) 3 QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 127
- The min VILand max VIH values are based on the respective min and max LVIN/L1VIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN/L1VIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.18.2 FlexCAN AC timing specifications
This table provides the FlexCAN AC timing specifications. Table 92. FlexCAN AC timing specifications 2 This figure provides the FlexCAN AC test load. Figure 47. FlexCAN AC test load
3.19 SAI/I2S interface
This section describes the DC and AC electrical characteristics for the SAI/I2S interface. There are SAI/I2S pins on various power supplies in this device.
3.19.1 SAI/I2S DC electrical characteristics
This table provides the SAI/I2S DC electrical characteristics when L1VDD/DVDD = 3.3 V. Table 93. SAI/I 2S DC electrical characteristics (L1VDD/DVDD = 3.3 V) 4 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 93. SAI/I 2S DC electrical characteristics (L1VDD/DVDD = 3.3 V) 4 (continued)
- The min VILand max VIH values are based on the respective min and max L1VIN/DVIN values found in Table 3.
- The symbol L1VIN, in this case, represents the L1VIN/DVIN symbol referenced in Table 3.
- The symbol L1VDD, in this case, represents the L1VDD/DVDD symbols referenced in Table 3.
- For recommended operating conditions, see Table 3.
This table provides the SAI/I2S DC electrical characteristics when L1VDD = 2.5 V. Table 94. SAI/I 2S DC electrical characteristics (L1VDD/DVDD = 2.5 V)4
- The min VILand max VIH values are based on the respective min and max L1VIN/DVDD values found in Table 3.
- The symbol VIN, in this case, represents the L1VIN/DVDD symbols referenced in Table 3.
- The symbol L1VDD, in this case, represents the L1VDD/DVDD symbols referenced in Table 3.
- For recommended operating conditions, see Table 3.
This table provides the SAI/I2S DC electrical characteristics when L1VDD/DVDD = 1.8 V. Table 95. SAI/I 2S DC electrical characteristics (L1VDD/DVDD = 1.8 V)4
- The min VILand max VIH values are based on the min and max L1VIN/DVDD respective values found in Table 3.
- The symbol L1VIN represents the L1VIN/DVDD symbols referenced in Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 129
- The symbol L1VDD, in this case, represents the L1VDD/DVDD symbols referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.19.2 SAI/I2S AC timing specifications
(clocks driven) and slave (clocks input) modes. This table provides the SAI timing in master mode. Table 96. Master mode SAI timing This figure shows the SAI timing in master modes. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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SAIn_Tx_BCLK SAIn_Tx_SYNC SAIn_Rx_SYNC SAIn_Tx_DATA SAIn_Rx_DATA tSAIMVKH tSAIMLOV tSAIMLOX Figure 48. SAI timing — master modes This table provides the SAI timing in slave mode. Table 97. Slave mode SAI timing This figure shows the SAI timing in slave modes. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 131
SAIn_Rx_BCLK SAIn_Tx_SYNC SAIn_Rx_SYNC SAIn_Tx_DATA SAIn_Rx_DATA tSAISFSLOV tSAISFSLOV tSAISXKH tSAISFSXKH tSAISLOX Figure 49. SAI timing — slave modes
3.20 SPDIF interface
Digital Interconnent Formal (SPDIF) interface.
3.20.1 SPDIF DC electrical characteristics
Table 98. SPDIF DC electrical characteristics (DV DD = 3.3 V)3
- The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
- The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
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Table 99. SPDIF DC electrical characteristics (DV DD = 1.8 V)3
- The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
- The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.20.2 SPDIF AC timing specifications
This table provides the AC timing specifications for the SPDIF interface. Table 100. SPDIF AC timing specifications This figure shows the timing for SPDIF_SRCLK. Figure 50. SPDIF_SRCLK timing QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 133
This figure shows the timing for SPDIF_EXTCLK. SPDIF_EXTCLK (Input) stclkpl stclkp stclkph VM VM Figure 51. SPDIF_EXTCLK timing
3.21 SPI interface
This section describes the DC and AC electrical characteristics for the SPI interface.
3.21.1 SPI DC electrical characteristics
Table 101. SPI DC electrical characteristics (3.3 V) 3
- The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
- The symbol VIN, in this case, represents the BVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
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Table 102. SPI DC electrical characteristics (1.8 V) 3
- The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
- The symbol VIN, in this case, represents the BVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.21.2 SPI AC timing specifications
This table provides the SPI timing specifications. Table 103. SPI AC timing specifications This figure shows the SPI timing master when CPHA = 0. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 135
(CPOL = 0) SCK Output (CPOL = 1) CSx tCSC tASC tSDC tSCK tSDC tNIIVKH tNIIXKH tNIKHOX tNIKHOV SIN SOUT First Data Data Last Data First Data Data Last Data Figure 52. SPI timing master, CPHA = 0 This figure shows the SPI timing master when CPHA = 1. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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(CPOL = 0) SCK Output (CPOL = 1) CSx tNIIVKH t NIKHOX tNIKHOV SIN SOUT First Data Data Last Data First Data Data Last Data tNIIXKH Figure 53. SPI timing master, CPHA = 1 This figure shows the SPI timing slave when CPHA = 0. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 137
(CPOL = 0) SCK Input (CPOL = 1) SS tCSC tASC tSDC tSCK tSDC tNEIVKH tNEIXKH t NEKHOX t NEKHOV SOUT SIN First Data Data Last Data First Data Data Last Data tA tDI Figure 54. SPI timing slave, CPHA = 0 This figure shows the SPI timing slave when CPHA = 1. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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(CPOL = 0) SCK Input (CPOL = 1) SS tNEIVKH t NEIXKHt NEKHOX tNEKHOV SOUT SIN First Data Data Last Data First Data Data Last Data tA t DI Figure 55. SPI timing slave, CPHA = 1
3.22 QuadSPI interface
This section describes the DC and AC electrical characteristics for the QuadSPI interface.
3.22.1 QuadSPI DC electrical characteristics
Table 104. QuadSPI DC electrical characteristics (3.3 V) 3 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 139
Table 104. QuadSPI DC electrical characteristics (3.3 V) 3 (continued)
- The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
- The symbol VIN, in this case, represents the BVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 105. QuadSPI DC electrical characteristics (1.8 V) 3
- The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
- The symbol VIN, in this case, represents the BVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.22.2 QuadSPI AC timing specifications
shown in the timing figures in this section.
3.22.2.1 QuadSPI timing SDR mode
This table provides the QuadSPI input and output timing in SDR mode. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 106. SDR mode QuadSPI input and output timing
- The input timing is relative to the sampling clock edge which is configurable. Please refer to register QuadSPI_SMPR from
LS102xA Reference Manual for more information. This figure shows the QuadSPI AC timing in SDR mode. Figure 56. QuadSPI AC timing — SDR mode
3.23 Enhanced secure digital host controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface. Note: This section is preliminary and is subject to further change. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 141
3.23.1 eSDHC DC electrical characteristics This table provides the DC electrical characteristics for the eSDHC interface operating at D/EVDD = 3.3 V. Table 107. eSDHC interface DC electrical characteristics 3
- The min VIL and max VIH values are based on the respective min and max EVIN values found in Table 3.
- Open-drain mode is for MMC cards only.
- The eSDHC interface is powered by DVDD and EVDD.
Table 108. eSDHC interface DC electrical characteristics (dual-voltage cards) 1, 4
- The eSDHC interface is powered by DVDD and EVDD.
- The min VIL and VIH values are based on the respective min and max D/EVIN values found in Table 3.
- Open-drain mode is for MMC cards only.
- For recommended operating conditions, see Table 3.
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3.23.2 eSDHC AC timing specifications This section provides the AC timing specifications. This table provides the eSDHC AC timing specifications as defined in Figure 57 and Figure 58 (EVDD/DVDD = 1.8 V or 3.3 V). Table 109. eSDHC AC timing specifications (high speed/ full speed) 6
- The symbols used for timing specifications follow these patterns: t(first three letters of functional block)(signal)(state) (reference)(state) for
clock of a particular function. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
- In full-speed mode, the clock frequency value can be 0-25 MHz for an SD/SDIO card and 0-20 MHz for an MMC card. In
high-speed mode, the clock frequency value can be 0-50 MHz for an SD/SDIO card and 0-52 MHz for an MMC card.
- Without voltage translator and SDHC_CLK_SYNC_IN and SDHC_CLK_SYNC_OUT, to satisfy setup timing, one-way
for input setup time and 0.5 ns skew for output delay time are considered in the table.
- CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF.
- The parameter values apply to both full-speed and high-speed modes.
- For recommended operating conditions, see Table 3.
This figure shows the eSDHC clock input timing diagram. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 143
VM = Midpoint voltage (EV DD /2) Figure 57. eSDHC clock input timing diagram This figure shows the eSDHC input AC timing diagram for high-speed mode. Figure 58. eSDHC high-speed mode input AC timing diagram This figure shows the eSDHC output AC timing diagram for high-speed mode. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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SDHC_CLK SDHC_CMD/SDHC_CMD_DIR SDHC_DAT/SDHC_DATn_DIR outputs VM VM VM VM tSHKHOV tSHKHOX VM = Midpoint voltage (EVDD/2) Figure 59. eSDHC high-speed mode output AC timing diagram Table 110. eSDHC AC timing specifications (SDR50) 2
- CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 30 pF.
- For recommended operating conditions, see Table 3.
This figure shows the eSDHC clock input timing diagram for SDR50 mode. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 145
VM = Midpoint voltage (EV DD /2) Figure 60. eSDHC SDR50 mode clock input timing diagram This figure shows the eSDHC input AC timing diagram for SDR50 mode. Figure 61. eSDHC SDR50 mode input AC timing diagram This figure shows the eSDHC output AC timing diagram for SDR50 mode. Figure 62. eSDHC SDR50 mode output AC timing diagram QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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This table provides the eSDHC AC timing specifications for DDR50/eMMC DDR mode (EVDD/DVDD = 1.8 V for DDR50, EVDD/DVDD = 1.8 V or 3.3 V for eMMC DDR mode). Table 111. eSDHC AC timing specifications (DDR50/eMMC DDR) 3
- CL = CBUS + CHOST + CCARD ≤ 20 pF for MMC, 40 pF for SD.
- For recommended operating conditions, see Table 3.
This figure shows the eSDHC DDR50/eMMC DDR mode input AC timing diagram. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 147
SDHC_CLK_SYNC_IN SDHC_DAT input SDHC_CMD input TSHCK T SHCIVKH TSHCIXKH TSHDIVKH TSHDIXKH TSHDIVKH TSHDIXKH Figure 63. eSDHC DDR50/eMMC DDR mode input AC timing diagram This figure shows the DDR50/eMMC DDR mode output AC timing diagram. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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SDHC_CLK SDHC_DAT/ SDHC_DATn_DIR output SDHC_CMD/ SD_CMD_DIR output TSHCK TSHCKHOV TSHCKHOX TSHDKHOV TSHDKHOV TSHDKHOXTSHDKHOX Figure 64. eSDHC DDR50/eMMC DDR mode output AC timing diagram Table 112. eSDHC AC timing specifications (SDR104/eMMC HS200) 2
- CL = CBUS + CHOST + CCARD ≤ 10 pF.
- For recommended operating conditions, see Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 149
This figure shows the SDR104/HS200 mode AC timing diagram. SDHC_CLK SDHC_CMD/ SDHC_DAT input SDHC_CMD/SDHC_CMD_DIR SDHC_DAT/SDHC_DATn_DIR output DATA DATA DATA TNIKHOV TNIKHOX TCLK TIDV Figure 65. SDR104/eMMC HS200 mode AC timing diagram
3.24 JTAG controller
3.24.1 JTAG DC electrical characteristics
This table provides the JTAG DC electrical characteristics. Table 113. JTAG DC electrical characteristics (OV DD = 1.8V)3 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 113. JTAG DC electrical characteristics (OV DD = 1.8V)3 (continued)
- The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
- The symbol VIN, in this case, represents the OVIN symbol found in Table 3.
- For recommended operating conditions, see Table 3.
- TMI, TMS, and TRST_B have internal pull-ups per the IEEE Std 1149.1 specification.
3.24.2 JTAG AC timing specifications
67, Figure 68, and Figure 69. Table 114. JTAG AC timing specifications 4
- The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for
times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.
- All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
added for trace lengths, vias, and connectors in the system.
- For recommended operating conditions, see Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 151
This figure shows the AC test load for TDO and the boundary-scan outputs of the device. Output Z0= 50 Ω RL = 50 Ω OVDD/2 Figure 66. AC test load for the JTAG interface This figure shows the JTAG clock input timing diagram. Figure 67. JTAG clock input timing diagram This figure shows the TRST_B timing diagram. Figure 68. TRST_B timing diagram This figure shows the boundary-scan timing diagram. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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VM = Midpoint Voltage (OVDD/2) tJTKLDV tJTKLDX tJTDVKH tJTDXKH Figure 69. Boundary-scan timing diagram
3.25 I2C interface
This section describes the DC and AC electrical characteristics for the I2C interfaces.
3.25.1 I2C DC electrical characteristics
Table 115. I 2C DC electrical characteristics (DVDD, D1VDD = 3.3 V)4
- The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
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- See the chip reference manual for information about the digital filter used.
- I/O pins obstruct the SDA and SCL lines if DVDD is switched off.
- For recommended operating conditions, see Table 3.
Table 116. I 2C DC electrical characteristics (DVDD, D1VDD = 1.8 V)4
- The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
- See the chip reference manual for information about the digital filter used.
- I/O pins obstruct the SDA and SCL lines if DVDD is switched off.
- For recommended operating conditions, see Table 3.
3.25.2 I2C AC timing specifications
This table provides the AC timing specifications for the I2C interfaces. Table 117. I 2C AC timing specifications5 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 117. I 2C AC timing specifications5 (continued)
- The symbols used for timing specifications herein follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state)
to the tI2C clock reference (K) going to the high (H) state or setup time.
- The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for
- As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
chip as transmitter, see Determining the I2C Frequency Divider Ratio for SCL (AN2919).
- The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
- For recommended operating conditions, see Table 3.
This figure shows the AC test load for the I2C. Figure 70. I2C AC test load This figure shows the AC timing diagram for the I2C bus. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 155
tI2DXKL , t I2OVKL tI2CL tI2SXKL Figure 71. I2C bus AC timing diagram
3.26 GPIO interface
This section describes the DC and AC electrical characteristics for the GPIO interface. LVDD stands for any power supply that the GPIO is running off.
3.26.1 GPIO DC electrical characteristics
Table 118. GPIO DC electrical characteristics (3.3 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
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Table 119. GPIO DC electrical characteristics (2.5 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN/L1VIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN/L1VIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 120. GPIO DC electrical characteristics (1.8 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.26.2 GPIO AC timing specifications
This table provides the GPIO input and output AC timing specifications. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 157
Table 121. GPIO input AC timing specifications
- GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
- For recommended operating conditions, see Table 3.
- Entry and exit from deep sleep respectively require a minimum pulse width tPIWID of 35 SYSCLK. See the Reference
Manual for details on Entry and Exit from deep sleep. This figure shows the AC test load for the GPIO. Figure 72. GPIO AC test load
3.27 GIC interface
This section describes the DC and AC electrical characteristics for the GIC interface.
3.27.1 GIC DC electrical characteristics
Table 122. GIC DC electrical characteristics (3.3 V) 3 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 122. GIC DC electrical characteristics (3.3 V) 3 (continued)
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 123. GIC DC electrical characteristics (2.5 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN/L1VIN values found in Table 3.
- The symbol VIN, in this case, represents the LVIN/L1VIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 124. GIC DC electrical characteristics (1.8 V) 3
- The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 159
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
3.27.2 GIC AC timing specifications
This table provides the GIC input and output AC timing specifications. Table 125. GIC Input AC timing specifications 2
- GIC inputs and outputs are asynchronous to any visible clock. GIC outputs must be synchronized before use by any
- For recommended operating conditions, see Table 3.
- Entry and exit from deep sleep respectively require a minimum pulse width tPIWID of 25 SYSCLK. See the applicable device
reference manual for details on Entry and Exit from deep sleep.
3.28 Display controller unit (2D-ACE)
This section describes the 2D-ACE DC and AC electrical characteristics. This table provides the 2D-ACE DC electrical characteristics operating at DVDD = 3.3 V. Table 126. 2D-ACE DC electrical characteristics (3.3 V) 3 QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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- The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
- The symbol VIN, in this case, represents the DVIN symbol referenced in Table 3.
- For recommended operating conditions, see Table 3.
Table 127. 2D-ACE DC electrical characteristics (1.8 V) 3
- The min VILand max VIH values are based on the min and max DVDD respective values found in Table 3.
- The symbol DVIN represents the input voltage of the supply referenced in Table 3.
- For recommended operating conditions, see Table 3.
This table provides the output AC timing specifications for the 2D-ACE interface. Table 128. 2D-ACE interface timing parameters 1 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 161
Table 128. 2D-ACE interface timing parameters 1 (continued)
- Display pixel clock frequency must be less than or equal to 1/4 of the platform clock.
This figure shows the AC timing diagram for the 2D-ACE interface. Figure 73. 2D-ACE interface AC timing diagram
3.29 High-speed serial interfaces (HSSI)
SGMII, and serial ATA (SATA) data transfers. transmitter (Tx) and receiver (Rx) reference circuits are also described.
3.29.1 Signal terms definitions
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This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This figure shows the waveform for either a transmitter output (SD_TXn_P and SD_TXn_N) or a receiver input (SD_RXn_P and SD_RXn_N). Each signal swings between A volts and B volts where A > B. A Volts B Volts SD_TXn_P or SD_RXn_P SD_TXn_N or SD_RXn_N Vcm= (A + B)/2 Differential swing, VID orVOD = A - B Differential peak voltage, VDIFFp = |A - B| Differential peak-to-peak voltage, VDIFFpp =2 x VDIFFp (not shown) Figure 74. Differential voltage definitions for transmitter or receiver also referred to as each signal wire's single-ended swing. VOD value can be either positive or negative. value can be either positive or negative. input signal is defined as the differential peak voltage, VDIFFp = |A - B| volts. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 163
example, the output differential peak-to-peak voltage can also be calculated as VTX- DIFFp-p = 2 x |VOD|. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SD_TXn_N, for example) from the non-inverting signal (SD_TXn_P, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. See Figure 79 as an example for differential waveform. Common Mode Voltage, Vcm The common mode voltage is equal to half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSD_TXn_P + VSD_TXn_N) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complementary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component's output to the other's input. It may be different between the receiver input and driver output circuits within the same component. It is also referred to as the DC offset on some occasions. To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the differential signaling environment is fully symmetrical in this example, the transmitter output's differential swing (VOD) has the same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV. In other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
3.29.2 SerDes reference clocks
The SerDes reference clock inputs are applied to an internal phase-locked loop (PLL) whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N. SerDes may be used for various combinations of the following IP blocks based on the RCW Configuration field SRDS_PRTCLn:
- SGMII (1.25 Gbps)
- PCIe (2.5 and 5 Gbps)
- SATA (1.5, 3.0, and 6.0 Gbps)
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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The following sections describe the SerDes reference clock requirements and provide application information.
3.29.2.1 SerDes spread-spectrum clock source recommendations
SD1_REF_CLKn_P and SD1_REF_CLKn_N are designed to work with spread-spectrum clocking for the PCI Express protocol only with the spreading specification defined in Table 129. When using spread-spectrum clocking for PCI Express, both ends of the link significant unintended modulation must be used. using spread-spectrum clocking. the SerDes lane usage mapping option, spread-spectrum clocking cannot be used at all. This table provides the source recommendations for SerDes spread-spectrum clocking. Table 129. SerDes spread-spectrum clock source recommendations 1
- At recommended operating conditions. See Table 3.
- Only down-spreading is allowed.
3.29.2.2 SerDes reference clock receiver characteristics
This figure shows a receiver reference diagram of the SerDes reference clocks. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 165
50 Ω 50 Ω SD1_REF_CLKn_P SD1_REF_CLKn_N Figure 75. Receiver of SerDes reference clocks
- The SerDes transceiver's core power supply voltage requirements (SVDDn) are as specified in Table 3.
- The SerDes reference clock receiver reference circuit structure is as follows:
- The SD1_REF_CLKn_P and SD1_REF_CLKn_N are internally AC-coupled differential inputs as shown in Figure 75. Each differential clock input (SD1_REF_CLKn_P or SD1_REF_CLKn_N) has on-chip 50-Ω termination to SGNDn followed by on-chip AC-coupling.
- The external reference clock driver must be able to drive this termination.
- The SerDes reference clock input can be either differential or single-ended. See the differential mode and single-ended mode descriptions in Signal terms definitions for detailed requirements.
- The maximum average current requirement also determines the common mode voltage range.
- When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input is AC-coupled on-chip.
- This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0-0.8 V), such that each phase of the differential input has a single- ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
- If the device driving the SD1_REF_CLKn_P and SD1_REF_CLKn_N inputs cannot drive 50 Ω to SGNDn DC or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip.
- The input amplitude requirement is described in detail in the following sections.
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3.29.2.3 DC-level requirements for SerDes reference clocks
The DC-level requirements for the SerDes reference clock inputs are different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below:
- Differential Mode
- The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-to-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection.
- For an external DC-coupled connection, as described in Figure 75, the maximum average current requirements set the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV.
- This figure shows the SerDes reference clock input requirement for a DC- coupled connection scheme. SD1_REF_CLKn_P SD1_REF_CLKn_N 200 mV < Input amplitude or differential peak < 800 mV Vmax < 800mV 100 mV < Vcm < 400 mV Vmin > 0 V
Figure 76. Differential reference clock input DC requirements (external DC-coupled)
- For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different common mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGNDn. Each signal wire of the differential inputs is allowed to swing below and above the common mode voltage (SGNDn).
- This figure shows the SerDes reference clock input requirement for an AC- coupled connection scheme.
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SD1_REF_CLKn_P SD1_REF_CLKn_N 200 mV < Input amplitude or differential peak < 800 mV Vmax < Vcm + 400 mV Vmin > Vcm - 400 mV Vcm Figure 77. Differential reference clock input DC requirements (external AC-coupled)
- Single-ended mode
- The reference clock can also be single-ended. The SD1_REF_CLKn_P input amplitude (single-ended swing) must be between 400 mV and 800 mV peak-to- peak (from VMIN to VMAX) with SD1_REF_CLKn_N either left unconnected or tied to ground.
- To meet the input amplitude requirement, the reference clock inputs may need to be externally DC- or AC-coupled. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase (SD1_REF_CLKn_N) through the same source impedance as the clock input (SD1_REF_CLKn_P) in use.
- The SD1_REF_CLKn_P input average voltage must be between 200 and 400 mV.
- This figure shows the SerDes reference clock input requirement for single-ended signaling mode. 400 mV < SD1_REF_CLKn input amplitude < 800 mV SD1_REF_CLKn_P SD1_REF_CLKn_N 0 V
Figure 78. Single-ended reference clock input DC requirements
3.29.2.4 AC requirements for SerDes reference clocks
running at data rates up to 5 Gb/s. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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This includes PCI Express (2.5 and 5 GT/s), SGMII (1.25 Gbps), and SATA (1.5, 3.0, and 6.0 Gbps). SerDes reference clocks need to be verified by the customer's application design. Table 130. SD1_REF_CLK n_P and SD1_REF_CLKn_N input clock requirements
1.5 MHz RMS jitter
- For recommended operating conditions, see Table 3.
- Caution: Only 100 and 125 have been tested. In-between values do not work correctly with the rest of the system.
- For PCI Express (2.5 and 5 GT/s).
- Measurement taken from differential waveform.
- Limits from PCI Express CEM Rev 2.0.
- For PCI Express 5 GT/s, per PCI Express base specification Rev 3.0.
- Measured from -200 mV to +200 mV on the differential waveform (derived from SD1_REF_CLKn_P minus
measurement window is centered on the differential zero crossing. See Figure 79.
- Measurement taken from single-ended waveform.
- Matching applies to rising edge for SD1_REF_CLKn_P and falling edge rate for SD1_REF_CLKn_N. It is measured using
a 200 mV window centered on the median cross point where SD1_REF_CLKn_P rising meets SD1_REF_CLKn_N falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. allowed difference should not exceed 20% of the slowest edge rate. See Figure 80. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 169
This figure shows the differential measurement points for rise and fall time. Rise-edge rate Fall-edge rate VIH = + 200 mV 0.0 V VIL = - 200 mV SD1_REF_CLKn_P SD1_REF_CLKn_N Figure 79. Differential measurement points for rise and fall time This figure shows the single-ended measurement points for rise and fall time matching. Figure 80. Single-ended measurement points for rise and fall time matching
3.29.3 SerDes transmitter and receiver reference circuits
This figure shows the reference circuits for SerDes data lane's transmitter and receiver. Figure 81. SerDes transmitter and receiver reference circuits QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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The DC and AC specifications of the SerDes data lanes are defined in each interface protocol section below based on the application usage:
- PCI Express
- Serial ATA (SATA) interface
- SGMII interface Note that an external AC-coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in the specification of each protocol section.
3.29.4 PCI Express
This section describes the clocking dependencies, as well as the DC and AC electrical specifications for the PCI Express bus.
3.29.4.1 Clocking dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 ppm of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
3.29.4.2 PCI Express DC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this chip.
3.29.4.2.1 PCI Express DC physical layer transmitter specifications
This section describes the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s. This table provides the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 131. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 171
- For recommended operating conditions, see Table 3.
- VTX-DIFFp-p = 2 x | VTX-D+ - VTX-D- |
- Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a
- Transmitter DC differential mode low impedance.
- Required transmitter D+, as well as D- DC impedance during all states.
output at all transmitters. The parameters are specified at the component pins. Table 132. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications
- For recommended operating conditions, see Table 3.
- VTX-DIFFp-p = 2 x | VTX-D+ - VTX-D- |
- Ration of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a
- Transmitter DC differential mode low impedance.
- Required transmitter D+, as well as D- DC impedance during all states.
3.29.4.3 PCI Express DC physical layer receiver specifications
input at all receivers. The parameters are specified at the component pins. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 133. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (S1V DD =
- Measured at the package pins with a test load of 50Ω to GND on each pin.
- VRX-DIFFp-p = 2 x | VRX-D+ - VRX-D- |
- Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
- Required receiver D+ as well as D- DC impedance (50 ± 20% tolerance).
- The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
be measured at 300 mV above the receiver ground.
- Required receiver D+ as well as D- DC impedance when the receiver terminations do not have power.
- VRX-IDLE-DET-DIFFp-p = 2 x | VRX-D+ - VRX-D- |
- Measured at the package pins of the receiver.
input at all receivers. The parameters are specified at the component pins. Table 134. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (S1V DD =
- Measured at the package pins with a test load of 50Ω to GND on each pin.
- VRX-DIFFp-p = 2 x | VRX-D+ - VRX-D- |
- Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
- Required receiver D+ as well as D- DC impedance (50 ± 20% tolerance).
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- The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
be measured at 300 mV above the receiver ground.
- Required receiver D+ as well as D- DC impedance when the receiver terminations do not have power.
- VRX-IDLE-DET-DIFFp-p = 2 x | VRX-D+ - VRX-D- |
- Measured at the package pins of the receiver.
3.29.4.4 PCI Express AC physical layer specifications
3.29.4.4.1 PCI Express AC physical layer transmitter specifications
timing specifications do not include RefClk jitter. Table 135. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications
- Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
- Specified at the measurement point into a timing and voltage test load as shown in Figure 82 and measured over any 250
consecutive transmitter UIs.
- The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 - TTX-EYE = 0.25 UI. Does not include spread-spectrum
or RefCLK jitter. Includes device random jitter at 10-12.
- A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
approximately equal as opposed to the averaged time value. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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- Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered
measured using all edges of the 250 consecutive UI in the center of the 3,500 UI used for calculating the transmitter UI.
- The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor of 100 nF is required.
- All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting
timing specifications do not include RefClk jitter. Table 136. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications
- Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
- Specified at the measurement point into a timing and voltage test load as shown in Figure 82 and measured over any 250
consecutive transmitter UIs.
- The maximum transmitter jitter can be derived as: TTX-MAX-JITTER = 1 - TTX-EYE = 0.25 UI.
- Reference input clock RMS jitter (< 1.5 MHz) at pin < 1ps.
- The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor of 100 nF is required.
- All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting
3.29.4.4.2 PCI Express AC physical layer receiver specifications
specifications do not include RefClk jitter. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 175
Table 137. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications
- Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
- The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAX-
JITTER = 1 - TRX-EYE = 0.6 UI.
- Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 82 must be used
reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
- A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
- It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a
- Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered
measured using all edges of the 250 consecutive UI in the center of the 3,500 UI used for calculating the transmitter UI. specifications do not include RefClk jitter. Table 138. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications 4
- Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
- The maximum inherent total timing error for common and separated RefClk receiver architecture.
- The maximum inherent deterministic timing error for common and separated RefClk receiver architecture.
- If spread spectrum clocking is desired, common clock must be used.
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3.29.4.5 Test and measurement load
The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in the following figure. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/ board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and D- package pins. Transmitter silicon + package D + package pin D - package pin C = CTX C = CTX R = 50 Ω R = 50 Ω Figure 82. Test and measurement load
3.29.5 Serial ATA (SATA) interface
This section describes the DC and AC electrical specifications for the SATA interface.
3.29.5.1 SATA DC electrical characteristics
This section describes the DC electrical characteristics for SATA.
3.29.5.1.1 SATA DC transmitter output characteristics
interface at Gen1i/1m or 1.5 Gbits/s transmission. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 177
Table 139. Gen1i/1m 1.5 G transmitter DC specifications (X1V DD = 1.35 V)3
- For recommended operating conditions, see Table 3.
interface at Gen2i/2m or 3.0 Gbits/s transmission. Table 140. Gen 2i/2m 3 G transmitter DC specifications (X1V DD = 1.35 V)2
- For recommended operating conditions, see Table 3.
interface at Gen 3i transmission. Table 141. Gen 3i transmitter DC specifications (X1V DD = 1.35 V)2
- For recommended operating conditions, see Table 3.
3.29.5.1.2 SATA DC receiver input characteristics
characteristics for the SATA interface. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 142. Gen1i/1m 1.5 G receiver input DC specifications (S1V DD = 1.0 V)3
- Voltage relative to common of either signal comprising a differential pair.
- For recommended operating conditions, see Table 3.
characteristics for the SATA interface. Table 143. Gen2i/2m 3 G receiver input DC specifications (S1V DD = 1.0 V)3
- Voltage relative to common of either signal comprising a differential pair.
- For recommended operating conditions, see Table 3.
Table 144. Gen 3i receiver input DC specifications (S1V DD = 1.0 V)3
- Voltage relative to common of either signal comprising a differential pair.
- For recommended operating conditions, see Table 3.
3.29.5.2 SATA AC timing specifications
This section describes the SATA AC timing specifications. QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 179
3.29.5.2.1 AC requirements for SATA REF_CLK
This table provides the AC requirements for the SATA reference clock. These requirements must be guaranteed by the customer's application design. Table 145. SATA reference clock input requirements 6
- Caution: Only 100 and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.
- In a frequency band from 150 kHz to 15 MHz at BER of 10-12.
- Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.
- Measurement taken from differential waveform.
- For recommended operating conditions, see Table 3.
3.29.5.3 AC transmitter output characteristics
Table 146. Gen 1i/1m 1.5 G transmitter AC specifications 2
- Measured at transmitter output pins peak-to-peak phase variation; random data pattern.
- For recommended operating conditions, see Table 3.
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This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not include RefClk jitter. Table 147. Gen 2i/2m 3 G transmitter AC specifications 2
- Measured at transmitter output pins peak-to-peak phase variation; random data pattern.
- For recommended operating conditions, see Table 3.
Table 148. Gen 3i transmitter AC specifications (S1V DD = 1.0 V)
3.29.5.4 AC differential receiver input characteristics
Table 149. Gen 1i/1m 1.5 G receiver AC specifications 2 Table continues on the next page... QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 181
Table 149. Gen 1i/1m 1.5 G receiver AC specifications 2 (continued)
- Measured at the receiver.
- For recommended operating conditions, see Table 3.
Table 150. Gen 2i/2m 3 G receiver AC specifications 2
- Measured at the receiver.
- For recommended operating conditions, see Table 3.
Table 151. Gen 3i receiver AC specifications 2
- Measured at the receiver.
- The AC specifications do not include RefClk jitter.
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4 Hardware design considerations
4.1 Power supply design
4.1.1 Core and platform supply voltage filtering
The VDD, VDDC supply is normally derived from a linear regulator or switching power supply that can regulate its output voltage very accurately despite changes in current demand from the chip within the regulator's relatively low bandwidth. Several bulk decoupling capacitors must be distributed around the PCB to supply transient current demand above the bandwidth of the voltage regulator. These bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure a quick response time. They should also be connected to the power and ground planes through two vias to minimize inductance. Customers should work directly with their power regulator vendor for best values and types of bulk capacitors. As a guideline for customers and their power regulator vendors, NXP recommends that these bulk capacitors be chosen to maintain the positive transient power surges to less than + 50 mV (negative transient undershoot should comply with specification of -30 mV) for current steps of up to 2A with a slew rate of 1.5A/μs. These bulk decoupling capacitors will ideally supply a stable voltage for current transients into the megahertz range. Above that, see Decoupling recommendations for further decoupling recommendations.
4.1.2 PLL power supply filtering
Each of the PLLs is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CGA1, AVDD_D1 and AVDD_SD1_PLLn). AVDD_PLAT, AVDD_CGA1, and AVDD_D1 voltages must be derived directly from a 1.8 V voltage source through a low frequency filter scheme. AVDD_SD1_PLLn voltages must be derived directly from the X1VDD source through a low frequency filter scheme. The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in Figure 83, one for each of the AVDD pins. By providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLL's resonant frequency range from a 500 kHz to 10 MHz range. Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 183
without the inductance of vias. This figure shows the PLL power supply filter circuit.
- R = 5 Ω ± 5%
- C1 = 10 μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH
- C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 NH 1 .8 V source R C1 C2 GND Low-ESL surface-mount capacitors AV DD _PLAT, AV DD _CGA1, AV DD _D1
Figure 83. PLL power supply filter circuit
- A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH).
- Voltage for AV DD is defined at the input of the PLL supply filter and not the pin of AVDD. The AVDD_SD1_PLLn signals provide power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 84. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SD1_PLLn balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SD1_PLLn balls. The 0.003-µF capacitors should be closest to the balls, followed by a 4.7-µF and 47-µF capacitor, and finally the 0.33 Ω resistor to the board supply plane. The capacitors are connected from AVDD_SD1_PLLn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide, and direct. This figure shows the PLL power supply filter circuit for the SerDes. Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Figure 84. SerDes PLL power supply filter circuit
- AVDD_SD1_PLLn should be a filtered version of X1VDD.
- Signals on the SerDes interface are fed from the X1V DD power plane.
- Voltage for AV DD_SD1_PLLn is defined at the PLL supply filter and not the pin of AVDD_SD1_PLLn.
- The 47-µF 0805 XR5 or XR7, 4.7-µF 0603, and 0.003-µF 0402 capacitors are recommended. The size and material type are important. A 0.33-Ω ± 1% resistor is recommended.
- There needs to be dedicated analog ground, AGND_SD1_PLLn for each AVDD_SD1_PLLn pin up to the physical locale of the filters themselves.
4.1.3 S1VDD power supply filtering
design in both options to allow flexibility to address system noise dependencies. based on the system or environment noise.
- C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
- C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
- F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)
- Bulk and decoupling capacitors are added, as needed, per power supply design. Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 185
Figure 85. S1VDD power supply filter circuit
- For maximum S1V DD power-up ramp rate, see Table 12.
- There needs to be enough output capacitance or a soft start feature to ensure the ramp rate requirement is met.
- The ferrite beads should be placed in parallel to reduce voltage droop.
- Besides a linear regulator, a low-noise, dedicated switching regulator can also be used. The goal is 10 mVp-p, 50 kHz - 500 MHz.
4.1.4 X1VDD power supply filtering
may design in both options to allow flexibility to address system noise dependencies. based on the system or environment noise.
- C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
- C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
- F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)
- Bulk and decoupling capacitors are added, as needed, per power supply design. Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Figure 86. X1VDD power supply filter circuit
- For maximum X1V DD power-up ramp rate, see Table 12.
- There needs to be enough output capacitance or a soft-start feature to ensure the ramp rate requirement is met.
- The ferrite beads should be placed in parallel to reduce voltage droop.
- Besides a linear regulator, a low-noise, dedicated switching regulator can be used. 10 mVp-p, 50 kHz - 500 MHz is the noise goal.
4.1.5 USB_HVDD power supply filtering
USB_HVDD must be sourced by a filtered 3.3 V voltage source using a star connection. values may need adjustment based on the system or environment noise.
- C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
- C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
- F1 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)
- Bulk and decoupling capacitors are added, as needed, per power supply design. USB_HV DD 3.3-V source C1 C2 C3 GND Bulk and decoupling capacitors
Figure 87. USB_HVDD power supply filter circuit
4.1.6 USB_SnVDD power supply filtering (SDVDD, SPVDD, SXVDD)
USB_SnVDD must be sourced by a filtered VDD using a star connection. adjustment based on the system or environment noise.
- C1 = 2.2 μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)
- F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
- Bulk and decoupling capacitors are added, as needed, per power supply design. USB_SnV DD V DD GND Bulk and decoupling capacitors V DD GND Bulk and decoupling capacitors
Figure 88. USB_SnVDD power supply filter circuit
4.2 Decoupling recommendations
under the device using a standard escape pattern. Others may surround the part.
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As presented in Core and platform supply voltage filtering, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, VDDC and other planes (for example, VDD, DVDD, EVDD, LVDD, and G1VDD), to enable quick recharging of the smaller chip capacitors.
4.3 SerDes block power supply decoupling recommendations
The SerDes block requires a clean, tightly regulated source of power (S1VDD and X1VDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below: 1. The board should have at least 1 x 0.1-uF SMT ceramic chip capacitor placed as close as possible to each supply ball of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. 2. Between the device and any SerDes voltage regulator, there should be a lower bulk capacitor. For example, a 10-uF, low ESR SMT tantalum or ceramic capacitor. There should also be a higher bulk capacitor. For example, a 100uF - 300-uF low ESR SMT tantalum or ceramic capacitor. NOTE Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
4.4 Connection recommendations
The following is a list of connection recommendations:
- To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unless otherwise noted in this document, all unused active low inputs should be tied to VDD, VDDC, TA_BB_VDD, O1VDD, and OVDD, BVDD, D1VDD, DVDD, EVDD, L1VDD, LVDD, and G1VDD, as required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, VDDC, TA_BB_VDD, O1VDD, OVDD, BVDD, D1VDD, DVDD, EVDD, L1VDD, LVDD, G1VDD , and GND pins of the device.
- The TEST_SEL_B pin must be pulled to OV DD through a 100-ohm to 1k-ohm resistor. Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 189
4.4.1 JTAG configuration signals
asynchronous behavior and spurious assertion will give unpredictable results. the JTAG port of the processor, with some additional status monitoring signals. connector typically has pin 7 removed as a connector key.
4.4.1.1 Termination of unused signals
is required for TDI, TMS, or TDO. This figure shows the Arm Cortex 10-pin header physical pinout. Figure 89. Arm Cortex 10-pin header physical pinout This figure shows the JTAG interface connection.
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1 . GNDDetect is an optional board feature. Check with 3rd-party tool vendor.
- This switch is included as a precaution for IEEE 1149.1 testing. The switch should be open (in position B)
debug testing, ensure this switch is closed (in position A). Figure 90. JTAG interface connection
4.4.2 Guidelines for high-speed interface termination
4.4.2.1 SerDes interface entirely unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. Note that S1VDD, X1VDD , AVDD_SD1_PLL1, and AVDD_SD1_PLL2 must remain powered. AVDD_SD1_PLL1 must be connected to X1VDD through a 0-Ω resistor (instead of through a filter circuit, as shown in Figure 84). The following pins must be left unconnected:
- SD1_TX[3:0]_P
- SD1_TX[3:0]_N
- SD1_IMP_CAL_RX
- SD1_IMP_CAL_TX The following pins must be connected to S1GND: It is recommended for the following pins to be connected to S1GND:
- SD1_RX[3:0]_P
- SD1_RX[3:0]_N It is possible to disable the SerDes module by disabling all PLLs associated with it. Use the following method to disable the SerDes module:
- SRDS_PLL_PD_S1 = 2’b11 (Both PLLs are configured as powered down; all data lanes selected by the protocols defined in SRDS_PRTCL_S1 associated to the PLLs are powered down, as well.)
- SRDS_PLL_REF_CLK_SEL_S1 = 2’b00
- SRDS_PRTCL_S1 = 2 (No other values are permitted when both PLLs are powered down.)
4.4.2.2 SerDes interface partly unused
If only part of the high-speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. Note that both S1VDD and X1VDD must remain powered. Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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If any of the PLLs are unused, the corresponding AVDD_SD1_PLL1 and AVDD_SD1_PLL2 must be connected to X1VDD through a 0-Ω resistor (instead of through a filter circuit, as shown in Figure 84). The following unused pins must be left unconnected:
- SD1_TX0_P
- SD1_TX0_N The following unused pins must be connected to S1GND:
- SD1_REF_CLKn_P, SD1_REF_CLKn_N (If the entire SerDes is unused.) It is recommended for the following unused pins to be connected to S1GND:
- SD1_RX0_P
- SD1_RX0_N In the RCW configuration field SRDS_PLL_PD_S1, the respective bits for each unused PLL must be set to power it down. A module is disabled when both its PLLs are turned off. Unused lanes must be powered down through the SRDSx Lane m General Control 0 (SRDSxLNmGCR0) register as follows:
- SRDSxLNmGCR0[RRST] = 0
- SRDSxLNmGCR0[TRST] = 0
- SRDSxLNmGCR0[RX_PD] = 1
- SRDSxLNmGCR0[TX_PD] = 1 Note that in the case where the SerDes pins are connected to slots, it is acceptable to have these pins unterminated when unused.
4.4.3 USB1 PHY connections
This section describes the hardware connections required for the USB PHY. This figure shows the VBUS interface for the chip. Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 193
Figure 91. USB1 PHY VBUS interface
4.5 Thermal
Table 152. Package thermal characteristics 5
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
- Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6 with the board (JESD51-9)
- Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
- Junction-to-case top at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature
is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
- For additional details, see Thermal management information.
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4.6 Recommended thermal model
Information about Flotherm models of the package or thermal data not available in this document can be obtained from your local NXP sales office.
4.7 Temperature diode
The chip has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461A). These devices feature series resistance cancellation using three current measurements, where up to 1.5 KΩ of resistance can be automatically cancelled from the temperature result, allowing noise filtering and a more accurate reading. The following are the specifications of the chip's on-board temperature diode:
- Operating range: 10 - 230 μA
- Ideality factor over 13.5 - 220 μA
- Temperature range: 80°C - 105°C: n = 1.004 ± 0.008
4.8 Thermal management information
This section describes the thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design — the heat sink, airflow, and thermal interface material. The recommended attachment method to the heat sink is illustrated in the following figure. The heat sink should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45 Newton). Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 195
Figure 92. Package exploded, cross-sectional view-FC-PBGA (no lid) attachment method, assembly, and cost. Flip Chip Ball Grid Array Packages".
4.8.1 Internal package conduction resistance
- The die junction-to-case thermal resistance
- The die junction-to-board thermal resistance This figure shows the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Hardware design considerations QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Figure 93. Package with heat sink mounted to a printed-circuit board resistance are the dominant terms.
4.8.2 Thermal interface materials
The system board designer can choose among several types of commercially available thermal interface materials.
5 Package information
5.1 Mechanical dimensions of the FC-PBGA
This figure shows the mechanical dimensions and bottom surface nomenclature of the chip.
Package information
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Figure 94. Mechanical dimensions of the FC-PBGA QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 199
Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured parallel to datum C. 4. Datum C, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
6 Security fuse processor
This chip implements the QorIQ platform's Trust Architecture, supporting capabilities such as secure boot. Use of the Trust Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP can be found in the chip reference manual. To program SFP fuses, the user is required to supply 1.8 V to the TA_PROG_SFP pin per Power sequencing. TA_PROG_SFP should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles. All other times, TA_PROG_SFP should be connected to GND. The sequencing requirements for raising and lowering TA_PROG_SFP are shown in Power sequencing. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature range per Table 3. NOTE Users not implementing the QorIQ platform's Trust Architecture features should connect TA_PROG_SFP to GND.
7 Ordering information
7.1 Part numbering nomenclature
This table provides the NXP QorIQ platform part numbering nomenclature. Security fuse processor QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
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Table 153. Part numbering nomenclature
7.2 Orderable part numbers addressed by this document
Table 154. Orderable part numbers addressed by this document
1 A =
Ordering information
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017 NXP Semiconductors 201
7.2.1 Part marking
Parts are marked as in the example shown in this figure. Figure 95. Part marking for FC-BGA chip (LS1021A)
8 Revision history
This table summarizes revisions to this document.
Revision history
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Table 155. Revision history
- updated signal description for signals TD1_ANODE and TD1_CATHODE.
- updated note reference for signals SPARE1 and SPARE2.
- updated note 19.
- added 4.7 kΩ in note 22.
- Replaced ARM with Arm throughout the document as per updated Arm brand guidelines
- In Table 2, removed note 11.
- In Table 3, added note 8.
- Added Table 11.
- In Table 23, removed slew rate.
- Updated Table 24 and added note 7.
- In Table 53, added note 6 and updated note reference for parameter TSEC_1588_CLK_IN clock period.
- In Table 35, added note 5 and updated notes for parameter Output differential voltage (XVDD-Typ at 1.35 V).
- In Table 113, added note 4 and updated max value and note reference for parameter Input current (OVIN = 0 V or OVIN = OVDD).
- Added new section, Temperature diode. 4 11/2016 • In Table 8, added a new row for supporting 1200 MHz frequency.
- In Table 9, added a new column for 1.2 GHz frequency.
- In Table 27, updated maximum value for input low voltage.
- In Table 89, updated input high voltage minimum value and input low voltage maximum value for nVDD.
- In Table 90, updated input high and low voltage minimum and maximum values to be formula based.
- In Table 91, updated input high and low voltage minimum and maximum values to be formula based.
- In Table 116, updated maximum value for output low voltage.
- In the GIC DC electrical characteristics section, updated "LVDD/ L1VDD = 2.5 V" to "L/L1/D/D1/O/O1/E/BVDD = 2.5 V".
- In the GPIO DC electrical characteristics section, updated "LVDD/ L1VDD = 2.5 V" to "L/L1/D/D1/O/O1/E/BVDD = 2.5 V".
- In the Thermal section, removed "prelimimary" from introductory paragraph.
- In Table 154, added part numbers for 1200 MHz. 3 05/2016 • Throughout document:
- Changed company references from Freescale to NXP within the body of the document content.
- Renamed description for power supply TA_BB_VDD from "Low Powered Security Monitor supply" to Battery Backed Security Monitor supply."
- Removed reference to signal TA_BB_RTC.
- In Pinout list,
- Changed name of "Trust" section to "Battery Backed Trust."
- For signal TA_BB_RTC:
- Changed signal description to "Reserved"
- Applied note #15, "These pins must be pulled to ground (GND)."
- For TA_BB_TMP_DETECT_B, changed signal description from "Low Power Tamper Detect" to "Battery Backed Tamper Detect"
- For CKSTP_OUT_B, changed signal description to "Reserved"
- For power supply TA_BB_VDD, changed description from "Low Power Security Monitor Supply" to "Battery Backed Security Monitor Supply"
- Added footnote 21, "Must be pulled down during power-on reset." to alternate signal listing QSPI_CS_A0.
- In Power sequencing, updated stable value from 75ms to 400ms and added step three to secure boot fuse programming sequence. Table continues on the next page...
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Table 155. Revision history (continued)
- In Differential system clock DC electrical characteristics table, added note 3, "Input differential voltage swing (Vid) specified is equal to |VDIFF_SYSCLK_P - VDIFF_SYSCLK_N|."
- In Differential system clock AC timing specifications table, added note 3," The 100 MHz reference frequency is needed if USB is used. The reference clock to USB PHY is selectable between SYSCLK or DIFF_SYSCLK/DIF_SYSCLK_B. The selected clock must meet the clock specifications for USB." 2 02/2016 • In Features listing, removed "supports 1000Base KX" from SerDes feature list.
- In Pinout list, added new note, "Permissible voltage range" to the USB1_VBUS pin.
- In Recommended operating conditions, updated table and added the following sentence to table note #7, "This also applies to DVDD and D1VDD."
- In Output driver capability table, added D1VDD to DVDD.
- In Real-time clock recommendations table, added a "Typical value" column and updated min and max values.
- In the table for Differential system clock DC electrical characteristics, updated min, max, and typical values for input capacitance and added note#2, "The die capacitance may cause reflection of the clock signal through the package back to the pin. This should not affect the signal quality seen by internal PLL. Recommend verifying signal quality using IBIS simulations."
- RESET initialization timing specifications table, added new notes #5 & #6.
- In EMI1 DC electrical characteristics, updated all tables:
- Removed table note #2, "The symbol L1VIN, in this case, represents the L1VIN symbol referenced in Table 3."
- Removed table note #3, " The symbol L1VDD, in this case, represents the L1VDD symbols referenced in Table 3."
- Updated LVDD to L1VDD
- In USB 3.0 reference clock requirements :
- Added a paragraph concerning the two options for USB PHY reference clock.
- Removed rows pertaining to Common mode input level, Differential input swing, Single- ended input logic low, Single-ended input logic high, Input edge rate, and Reference clock skew from the Reference clock requirements table
- In QuadSPI timing SDR mode, updated figure QuadSPI AC timing — SDR mode.
- In eSDHC AC timing specifications, updated the following figures:
- eSDHC DDR50/eMMC DDR mode input AC timing diagram
- eSDHC DDR50/eMMC DDR mode output AC timing diagram
- In SATA DC transmitter output characteristics, updated title of table from Gen 3i transmitter DC specifications (S1VDD = 1.0 V)2 to Gen 3i transmitter DC specifications (X1VDD = 1.35 V)2
- In Termination of unused signals, updated note #2 of figure, "JTAG interface connection," to read: "This switch is included as a precaution for IEEE 1149.1 testing." 1 11/2015 • In Introduction updated block diagram.
- In DDR3L and DDR4 SDRAM interface AC timing specifications, added entries for 1000 MT/s data rate.
- In DDR3L and DDR4 SDRAM interface output AC timing specifications, added entries for 1000 MT/s data rate.
- In Part numbering nomenclature, changed the unit of measure for DDR data rate (column d) from MHz to MT/s.
- In Orderable part numbers addressed by this document, changed the unit of measure for DDR data rate (column d) from MHz to MT/s. 0 10/2015 Initial public release
QorIQ LS1021A Data Sheet, Rev. 5, 09/2017
204 NXP Semiconductors
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