LPV521_16 TI1 | Alldatasheet
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SUPPLY VOLTAGE (V) SUPPLY CURRENT (nA) 800 700 600 500 400 300 200 100 1 2 3 4 5 6 125° C 85° C 25° C -40° C VCM = VS /cb1 0.3V Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LPV521 SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014 LPV521NanoPower,1.8-V,RRIO,CMOSInput,OperationalAmplifier
1 Features 3 Description
The LPV521 is a single nanopower 552-nW amplifier 1• For VS = 5 V, Typical Unless Otherwise Noted designed for ultra long life battery applications. The– Supply Current at VCM = 0.3 V 400 nA (Max) operating voltage range of 1.6 V to 5.5 V coupled – Operating Voltage Range 1.6 V to 5.5 V with typically 351 nA of supply current make it well suited for RFID readers and remote sensor– Low TCVOS 3.5 µV/°C (Max) nanopower applications. The device has input– VOS 1 mV (Max) common mode voltage 0.1 V over the rails, – Input Bias Current 40 fA guaranteed TCVOS and voltage swing to the rail output performance. The LPV521 has a carefully– PSRR 109 dB designed CMOS input stage that outperforms– CMRR 102 dB competitors with typically 40 fA IBIAS currents. This – Open-Loop Gain 132 dB low input current significantly reduces IBIAS and IOS errors introduced in megohm resistance, high– Gain Bandwidth Product 6.2 kHz impedance photodiode, and charge sense situations.– Slew Rate 2.4 V/ms The LPV521 is a member of the PowerWise™ family– Input Voltage Noise at f = 100 Hz 255 nV/√Hz and has an exceptional power-to-performance ratio. – Temperature Range −40°C to 125°C The wide input common mode voltage range, guaranteed 1 mV VOS and 3.5 µV/°C TCVOS enables2 Applications accurate and stable measurement for both high-side and low-side current sensing.• Wireless Remote Sensors
- Powerline Monitoring EMI protection was designed into the device to reduce sensitivity to unwanted RF signals from cell• Power Meters phones or other RFID readers.• Battery Powered Industrial Sensors The LPV521 is offered in the 5-pin SC70 package.• Micropower Oxygen sensor and Gas Sensor
- Active RFID Readers Device Information(1)
- Zigbee Based Sensors for HVAC Control PART NUMBER PACKAGE BODY SIZE (NOM)
- Sensor Network Powered by Energy Scavenging LPV521 SC70 (5) 2.00 mm x 1.25 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Nanopower Supply Current An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (Feburary 2013) to Revision D Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
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+ - OUT IN+ IN- LPV521 www.ti.com SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
5 Pin Configuration and Functions
NO. NAME
1 OUT O Output
2 V- P Negative Power Supply
3 IN+ I Noninverting Input
4 IN- I Inverting Input
5 V+ P Positive Power Supply
6 Specifications
6.1 Absolute Maximum Ratings(1)
Any pin relative to V- −0.3 6 V IN+, IN-, OUT Pins V– – 0.3 V V+ + 0.3 V V V+, V-, OUT Pins 40 mA Differential Input Voltage (VIN+ - VIN-) –300 300 mV Junction Temperature(2) –40 150 °C Mounting Temperature Infrared or Convection (30 sec.) 260 °C Wave Soldering Lead Temp. (4 sec.) 260 °C Storage temperature, Tstg −65 150 °C (1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. (2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22- ±1000V(ESD) Electrostatic discharge VC101(2) Machine Model ±200 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LPV521
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6.3 Recommended Operating Conditions(1)
Temperature Range(2) −40 125 °C Supply Voltage (VS = V+ - V−) 1.6 5.5 V (1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see Electrical Characteristics. (2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.4 Thermal Information
THERMAL METRIC(1) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance (2) 456 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. 6.5 1.8-V DC Electrical Characteristics Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOS Input Offset Voltage VCM = 0.3 V –1 0.1 1 Temperature extremes –1.23 1.23 mV VCM = 1.5 V –1 0.1 1 Temperature extremes –1.23 1.23 TCVOS Input Offset Voltage Drift(2) ±0.4 μV/°C Temperature extremes –3 3 IBIAS Input Bias Current –1 0.01 1 pA Temperature extremes –50 50 IOS Input Offset Current 10 fA CMRR Common Mode Rejection Ratio 0 V ≤ VCM ≤ 1.8 V 66 92 Temperature extremes 60 0 V ≤ VCM ≤ 0.7 V 75 101 dB Temperature extremes 74 1.2 V ≤ VCM ≤ 1.8 V 75 120 Temperature extremes 53 PSRR Power Supply Rejection Ratio 1.6 V ≤ V+ ≤ 5.5 V dB VCM = 0.3 V 85 109 Temperature extremes 76 CMRR ≥ 67 dB 0 V CMRR ≥ 60 dB 0 1.8CMVR Common Mode Voltage Range Temperature extremes 1.8 VO = 0.5 V to 1.3 V 125 dB74RL = 100 kΩ to V+/2AVOL Large Signal Voltage Gain Temperature extremes 73 (1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
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www.ti.com SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014 1.8-V DC Electrical Characteristics (continued) Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output Swing High RL = 100 kΩ to V+/2 2 50 VIN(diff) = 100 mV Temperature extremes 50 mV from either railOutput Swing Low RL = 100 kΩ to V+/2 2 50VIN(diff) = −100 mV Temperature extremes 50 IO Sourcing, VO to V– 31VIN(diff) = 100 mV Temperature extremes 0.5 Output Current(3) mA Sinking, VO to V+ 31VIN(diff) = −100 mV Temperature extremes 0.5 IS Supply Current VCM = 0.3 V 345 400 Temperature extremes 580 nA VCM = 1.5 V 472 600 Temperature extremes 850 (3) The short circuit test is a momentary open-loop test. 6.6 1.8-V AC Electrical Characteristics Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GBW Gain-Bandwidth Product CL = 20 pF, RL = 100 kΩ 6.1 kHz SR Slew Rate AV = +1, Falling Edge 2.9 V/msVIN = 0V to 1.8V Rising Edge 2.3 θ m Phase Margin CL = 20 pF, RL = 100 kΩ 72 deg Gm Gain Margin CL = 20 pF, RL = 100 kΩ 19 dB en Input-Referred Voltage Noise Density f = 100 Hz 265 nV/√Hz Input-Referred Voltage Noise 0.1 Hz to 10 Hz 24 μVPP In Input-Referred Current Noise f = 100 Hz 100 fA/√Hz (1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014 www.ti.com 6.7 3.3-V DC Electrical Characteristics Unless otherwise specified, all limits for TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOS Input Offset Voltage VCM = 0.3 V –1 0.1 1 Temperature extremes –1.23 1.23 mV VCM = 3 V –1 0.1 1 Temperature extremes –1.23 1.23 TCVOS Input Offset Voltage Drift(2) ±0.4 μV/°C Temperature extremes –3 3 IBIAS Input Bias Current –1 0.01 1 pA Temperature extremes –50 50 IOS Input Offset Current 20 fA CMRR Common Mode Rejection Ratio 0 V ≤ VCM ≤ 3.3 V 72 97 Temperature extremes 70 0 V ≤ VCM ≤ 2.2 V 78 106 dB Temperature extremes 75 2.7 V ≤ VCM ≤ 3.3 V 77 121 Temperature extremes 76 PSRR Power Supply Rejection Ratio 1.6 V ≤ V+ ≤ 5.5 V 10985VCM = 0.3 V dB Temperature extremes 76 CMRR ≥ 72 dB −0.1 3.4CMRR ≥ 70 dBCMVR Common Mode Voltage Range V Temperature extremes 0 3.3 VO = 0.5 V to 2.8 V 12082RL = 100 kΩ to V+/2AVOL Large Signal Voltage Gain dB Temperature extremes 76 VO Output Swing High RL = 100 kΩ to V+/2 3 50 VIN(diff) = 100 mV mVTemperature extremes 50 from either Output Swing Low RL = 100 kΩ to V+/2 2 rail50VIN(diff) = −100 mV Temperature extremes 50 IO Output Current(3) Sourcing, VO to V– 115VIN(diff) = 100 mV Temperature extremes 4 mA Sinking, VO to V+ 125VIN(diff) = −100 mV Temperature extremes 4 IS Supply Current VCM = 0.3 V 346 400 Temperature extremes 600 nA VCM = 3 V 471 600 Temperature extremes 860 (1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. (3) The short circuit test is a momentary open-loop test.
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www.ti.com SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014 6.8 3.3-V AC Electrical Characteristics Unless otherwise is specified, all limits for TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GBW Gain-Bandwidth Product CL = 20 pF, RL = 100 kΩ 6.2 kHz SR Slew Rate AV = +1, Falling Edge 2.9 V/msVIN = 0V to 3.3V Rising Edge 2.5 θ m Phase Margin CL = 20 pF, RL = 10 kΩ 73 deg Gm Gain Margin CL = 20 pF, RL = 10 kΩ 19 dB en Input-Referred Voltage Noise Density f = 100 Hz 259 nV/√Hz Input-Referred Voltage Noise 0.1 Hz to 10 Hz 22 μVPP In Input-Referred Current Noise f = 100 Hz 100 fA/√Hz (1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. 6.9 5-V DC Electrical Characteristics Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOS Input Offset Voltage VCM = 0.3 V 0.1 ±1 Temperature extremes –1.23 1.23 mV VCM = 4.7 V 0.1 ±1 Temperature extremes –1.23 1.23 TCVOS Input Offset Voltage Drift(2) ±0.4 μV/°C Temperature extremes –3.5 3.5 IBIAS Input Bias Current 0.04 ±1 pA Temperature extremes –50 50 IOS Input Offset Current 60 fA CMRR Common Mode Rejection Ratio 0 V ≤ VCM ≤ 5.0 V 75 102 Temperature extremes 74 0 V ≤ VCM ≤ 3.9 V 84 108 dB Temperature extremes 80 77 115 Temperature extremes 76 PSRR Power Supply Rejection Ratio 1.6 V ≤ V+ ≤ 5.5 V 85 109 VCM = 0.3 V dB Temperature extremes 76 CMVR Common Mode Voltage Range CMRR ≥ 75 dB −0.1 5.1 CMRR ≥ 74 dB V Temperature extremes 0 5 AVOL Large Signal Voltage Gain VO = 0.5 V to 4.5 V 84 132 dB RL = 100 kΩ to V+/2 Temperature extremes 76 (1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014 www.ti.com Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output Swing High RL = 100 kΩ to V+/2 3 50 VIN(diff) = 100 mV Temperature extremes 50 mV from either railOutput Swing Low RL = 100 kΩ to V+/2 3 50 VIN (diff) = −100 mV Temperature extremes 50 IO Output Current Sourcing, VO to V− 15 23 VIN(diff) = 100 mV Temperature extremes 8 mA Sinking, VO to V+ 15 22 VIN(diff) = −100 mV Temperature extremes 8 IS Supply Current VCM = 0.3 V 351 400 Temperature extremes 620 nA VCM = 4.7 V 475 600 Temperature extremes 870 6.10 5-V AC Electrical Characteristics(1) Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) (3) (2) GBW Gain-Bandwidth Product CL = 20 pF, RL = 100 kΩ 6.2 kHz SR Slew Rate AV = +1, Falling Edge 1.1 2.7 VIN = 0 V to 5 V Temperature 1.2 extremes V/ms Rising Edge 1.1 2.4 Temperature 1.2 extremes θ m Phase Margin CL = 20 pF, RL = 100 kΩ 73 deg Gm Gain Margin CL = 20 pF, RL = 100 kΩ 20 dB en Input-Referred Voltage Noise Density f = 100 Hz 255 nV/√Hz Input-Referred Voltage Noise 0.1 Hz to 10 Hz 22 μVPP In Input-Referred Current Noise f = 100 Hz 100 fA/√Hz EMIRR EMI Rejection Ratio, IN+ and IN−(4) VRF_PEAK = 100 mVP (−20 dBP), 121 f = 400 MHz VRF_PEAK = 100 mVP (−20 dBP), 121 f = 900 MHz dB VRF_PEAK = 100 mVP (−20 dBP), 124 f = 1800 MHz VRF_PEAK = 100 mVP (−20 dBP), 142 f = 2400 MHz (1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) All limits are guaranteed by testing, statistical analysis or design. (3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. (4) The EMI Rejection Ratio is defined as EMIRR = 20log (VRF_PEAK/ΔVOS).
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6.11 Typical Characteristics
At TJ = 25°C, unless otherwise specified. Figure 1. Supply Current vs. Supply Voltage Figure 2. Supply Current vs. Supply Voltage Figure 3. Offset Voltage Distribution Figure 4. TcvOS Distribution Figure 5. Offset Voltage Distribution Figure 6. TcvOS Distribution
At TJ = 25°C, unless otherwise specified. Figure 7. Offset Voltage Distribution Figure 8. TcvOS Distribution Figure 9. Input Offset Voltage vs. Input Common Mode Figure 10. Input Offset Voltage vs. Input Common Mode Figure 11. Input Offset Voltage vs. Input Common Mode Figure 12. Input Offset Voltage vs. Supply Voltage
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At TJ = 25°C, unless otherwise specified. Figure 19. Input Offset Voltage vs. Sourcing Current Figure 20. Input Offset Voltage vs. Sinking Current Figure 21. Input Offset Voltage vs. Sinking Current Figure 22. Input Offset Voltage vs. Sinking Current Figure 23. Sourcing Current vs. Output Voltage Figure 24. Sinking Current vs. Output Voltage
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At TJ = 25°C, unless otherwise specified. Figure 31. Output Swing High vs. Supply Voltage Figure 32. Output Swing Low vs. Supply Voltage Figure 33. Input Bias Current vs. Common Mode Voltage Figure 34. Input Bias Current vs. Common Mode Voltage Figure 35. Input Bias Current vs. Common Mode Voltage Figure 36. Input Bias Current vs. Common Mode Voltage
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At TJ = 25°C, unless otherwise specified. Figure 43. Frequency Response vs. Temperature Figure 44. Frequency Response vs. RL Figure 45. Frequency Response vs. RL Figure 46. Frequency Response vs. RL Figure 47. Frequency Response vs. CL Figure 48. Frequency Response vs. CL
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At TJ = 25°C, unless otherwise specified. Figure 55. Small Signal Pulse Response Figure 56. Small Signal Pulse Response Figure 57. Large Signal Pulse Response Figure 58. Large Signal Pulse Response Figure 59. Overload Recovery Waveform Figure 60. EMIRR vs. Frequency
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7 Detailed Description
7.1 Overview
dramatically improves the performance of Texas Instruments' low-power and low-voltage operational amplifiers.
7.2 Functional Block Diagram
Figure 61. Block Diagram
7.3 Feature Description
where AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10uV per Volt).
7.4 Device Functional Modes
7.4.1 Input Stage
within the entire common mode voltage range.
7.4.2 Output Stage
dynamic range at the output. This is particularly important when operating on low supply voltages. load. The LPV521 output swings 50 mV from the rail at 5-V supply with an output load of 100 kΩ.
8 Applications and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
temperature are presented in the Typical Characteristics section.
8.1.1 Driving Capacitive Load
The LPV521 is internally compensated for stable unity gain operation, with a 6.2-kHz, typical gain bandwidth. Figure 62. Resistive Isolation of Capacitive Load reduced output current drive. response. For capacitive loads of 20 pF and below no isolation resistor is needed.
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10 M/c3a
10 M/c3a10 M/c3a
225 mAh = 5 circuits @ 9.5 yrs.
60 Hz Twin T Notch Filter
Figure 63. Step Response
8.1.2 EMI Suppression
DC offset of the op amp. Also some common RF modulation schemes can induce down-converted components. supply pins; thereby preserving the integrity of the precision signal path.
8.2 Typical Applications
Figure 64. 60-Hz Notch Filter
8.2.1.1 Design Requirements
of 2 V. With an operating voltage from 1.6 V to 5.5 V the LPV521 can function over this voltage range.
8.2.1.2 Detailed Design Procedure
eliminating 50-Hz noise, which is common in European systems, use R = 11.8 MΩ and C = 270 pF. path through the resistors R - R and another separate high frequency path through the capacitors C - C. signals will tend to cancel at the amplifier’s input. for the filter components that connect to ground. capacitance which effects can be reduced by cutting out the ground plane below components of concern. circuit's noise is below ½ LSB of a 10 bit system with a 2-V reference, which is 1 mV.
8.2.1.3 Application Curve
Figure 65. 60-Hz Notch Filter Waveform
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100 M/c3a
1 M/c3a
8.2.2 Portable Gas Detection Sensor
Figure 66. Precision Oxygen Sensor
8.2.2.1 Design Requirements
of load resistors to choose from. which detect traces of oxygen in ppm.
8.2.2.2 Detailed Design Procedure
known current through the load resistor. This value changes with the amount of oxygen present in the air sample. LPV521 a great choice for this application.
8.2.2.3 Application Curve
Figure 67. Calculated Oxygen Sensor Circuit Output (Single 5V Supply)
8.2.3 High-Side Battery Current Sensing
Figure 68. High-Side Current Sensing
8.2.3.1 Design Requirements
resistor RSENSE is connected in series with the battery.
8.2.3.2 Detailed Design Procedure
amplifier, with the same value as R1 to minimize offset voltage.
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the measuring circuit supply current and extend battery life. 1.5 µA and measure 100 µA to 1 mA.
8.2.3.3 Application Curve
Figure 69. Calculated High-Side Current Sense Circuit Output
9 Power Supply Recommendations
temperature are presented in the Typical Characteristics. Supply voltages larger than 6 V can permanently damage the device. kHz range noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
- Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
- Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
- Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to Circuit Board Layout Techniques, SLOA089.
- In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
- Place the external components as close to the device as possible. As shown in Layout Example, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
- Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
- Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 70. Noninverting Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LPV521 PSPICE Model, SNOM024 TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti TI Filterpro Software, http://www.ti.com/tool/filterpro DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm Evaluation board for 5-pin, north-facing amplifiers in the SC70 package, SNOA487. Manual for LMH730268 Evaluation board 551012922-001
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
- Feedback Plots Define Op Amp AC Performance, SBOA015 (AB-028)
- Circuit Board Layout Techniques, SLOA089
- Op Amps for Everyone, SLOD006
- AN-1698 A Specification for EMI Hardened Operational Amplifiers, SNOA497
- EMI Rejection Ratio of Operational Amplifiers, SBOA128
- Capacitive Load Drive Solution using an Isolation Resistor, TIPD128
- Handbook of Operational Amplifier Applications, SBOA092
11.3 Trademarks
PowerWise is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LPV521
www.ti.com 3-Oct-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LPV521MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AHA LPV521MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AHA LPV521MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AHA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
www.ti.com 3-Oct-2014 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2016 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LPV521MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LPV521MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0 LPV521MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2016 Pack Materials-Page 2
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