LPV521 NSC | Alldatasheet
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Technical content
Features
(For VS = 5V, Typical unless otherwise noted) ■ Supply current at VCM = 0.3V 400 nA (max) ■ Operating voltage range 1.6V to 5.5V ■ Low TCVOS 3.5 µV/°C (max) ■ VOS 1 mV (max) ■ Input bias current 40 fA ■ PSRR 109 dB ■ CMRR 102 dB ■ Open loop gain 132 dB ■ Gain bandwidth product 6.2 kHz ■ Slew rate 2.4 V/ms ■ Input voltage noise at f = 100 Hz 255 nV/√Hz ■ Temperature range −40°C to 125°C
Applications
■ Wireless remote sensors ■ Powerline monitoring ■ Power meters ■ Battery powered industrial sensors ■ Micropower oxygen sensor and gas sensor ■ Active RFID readers ■ Zigbee based sensors for HVAC control ■ Sensor network powered by energy scavenging Typical Application 30054578 30054577 © 2009 National Semiconductor Corporation 300545 www.national.com LPV521 Nanopower, 1.8V, RRIO, CMOS Input, Operational Amplifier
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model 2000V Machine Model 200V Charge-Device Model 1000V Any pin relative to V- 6V, −0.3V IN+, IN-, OUT Pins V+ + 0.3V, V– – 0.3V V+, V-, OUT Pins 40mA Differential Input Voltage (VIN+ - VIN-) ±300 mV Storage Temperature Range −65°C to 150°C Junction Temperature (Note 3) 150°C Mounting Temperature Infrared or Convection (30 sec.) 260°C Wave Soldering Lead Temp. (4 sec.) 260°C Operating Ratings (Note 1) Temperature Range (Note 3) −40°C to 125°C Supply Voltage (VS = V+ - V−) 1.6V to 5.5V Package Thermal Resistance (θJA) (Note 3) 5-Pin SC-70 456 °C/W 1.8V DC Electrical Characteristics (Note 4) Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 1.8V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units VOS Input Offset Voltage VCM = 0.3V 0.1 ±1.0 ±1.23 TCVOS Input Offset Voltage Drift (Note 9) ±0.4 ±3 μV/°C IBIAS Input Bias Current 0.01 ±1 ±50 pA IOS Input Offset Current 10 fA CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 1.8V 66 dB0V ≤ VCM ≤ 0.7V 75 101 1.2V ≤ VCM ≤ 1.8V 75 120 PSRR Power Supply Rejection Ratio 1.6V ≤ V+ ≤ 5.5V VCM = 0.3V 109 dB CMVR Common Mode Voltage Range CMRR ≥ 67 dB CMRR ≥ 60 dB 1.8 1.8 V AVOL Large Signal Voltage Gain VO = 0.5V to 1.3V RL = 100 kΩ to V+/2 125 dB VO Output Swing High RL = 100 kΩ to V+/2 VIN(diff) = 100 mV 2 50 50 mV from either railOutput Swing Low RL = 100 kΩ to V+/2 VIN(diff) = −100 mV 2 50 IO Output Current (Note 7) Sourcing, VO to V– VIN(diff) = 100 mV 0.5 mASinking, VO to V+ VIN(diff) = −100 mV 0.5 IS Supply Current VCM = 0.3V 345 400 580 nAVCM = 1.5V 472 600 850 www.national.com 2 LPV521
1.8V AC Electrical Characteristics (Note 4) Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 1.8V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units GBW Gain-Bandwidth Product CL = 20 pF, RL = 100 kΩ 6.1 kHz SR Slew Rate AV = +1, VIN = 0V to 1.8V Falling Edge 2.9 V/msRising Edge 2.3 θ m Phase Margin CL = 20 pF, RL = 100 kΩ 72 deg Gm Gain Margin CL = 20 pF, RL = 100 kΩ 19 dB en Input-Referred Voltage Noise Density f = 100 Hz 265 nV/ Input-Referred Voltage Noise 0.1 Hz to 10 Hz 24 μVPP in Input-Referred Current Noise f = 100 Hz 100 fA/ 3.3V DC Electrical Characteristics (Note 4) Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units VOS Input Offset Voltage VCM = 0.3V 0.1 ±1.0 ±1.23 mVVCM = 3V 0.1 ±1.0 ±1.23 TCVOS Input Offset Voltage Drift (Note 9) ±0.4 ±3 μV/°C IBIAS Input Bias Current 0.01 ±1 ±50 pA IOS Input Offset Current 20 fA CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 3.3V 72 dB0V ≤ VCM ≤ 2.2V 78 106 2.7V ≤ VCM ≤ 3.3V 77 121 PSRR Power Supply Rejection Ratio 1.6V ≤ V+ ≤ 5.5V VCM = 0.3V 109 dB CMVR Common Mode Voltage Range CMRR ≥ 72 dB CMRR ≥ 70 dB −0.1 3.4 3.3 V AVOL Large Signal Voltage Gain VO = 0.5V to 2.8V RL = 100 kΩ to V+/2 120 dB VO Output Swing High RL = 100 kΩ to V+/2 VIN(diff) = 100 mV 3 50 50 mV from either railOutput Swing Low RL = 100 kΩ to V+/2 VIN(diff) = −100 mV 2 50 IO Output Current (Note 7) Sourcing, VO to V– VIN(diff) = 100 mV mASinking, VO to V+ VIN(diff) = −100 mV 3 www.national.com LPV521
Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units IS Supply Current VCM = 0.3V 346 400 600 nAVCM = 3V 471 600 860 3.3V AC Electrical Characteristics (Note 4) Unless otherwise is specified, all limits guaranteed for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ. Bold- face limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units GBW Gain-Bandwidth Product CL = 20 pF, RL = 100 kΩ 6.2 kHz SR Slew Rate AV = +1, VIN = 0V to 3.3V Falling Edge 2.9 V/msRising Edge 2.5 θ m Phase Margin CL = 20 pF, RL = 10 kΩ 73 deg Gm Gain Margin CL = 20 pF, RL = 10 kΩ 19 dB en Input-Referred Voltage Noise Density f = 100 Hz 259 nV/ Input-Referred Voltage Noise 0.1 Hz to 10 Hz 22 μVPP in Input-Referred Current Noise f = 100 Hz 100 fA/ Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units VOS Input Offset Voltage VCM = 0.3V 0.1 ±1.0 ±1.23 TCVOS Input Offset Voltage Drift (Note 9) ±0.4 ±3.5 μV/°C IBIAS Input Bias Current 0.04 ±1 ±50 pA IOS Input Offset Current 60 fA CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 5.0V 75 102 dB0V ≤ VCM ≤ 3.9V 84 108 4.4V ≤ VCM ≤ 5.0V 77 115 PSRR Power Supply Rejection Ratio 1.6V ≤ V+ ≤ 5.5V VCM = 0.3V 109 dB CMVR Common Mode Voltage Range CMRR ≥ 75 dB CMRR ≥ 74 dB −0.1 5.1 5 V AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V RL = 100 kΩ to V+/2 132 dB VO Output Swing High RL = 100 kΩ to V+/2 VIN(diff) = 100 mV 3 50 50 mV from either railOutput Swing Low RL = 100 kΩ to V+/2 VIN (diff) = −100 mV 3 50 www.national.com 4 LPV521
Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units IO Output Current (Note 7) Sourcing, VO to V− VIN(diff) = 100 mV mASinking, VO to V+ VIN(diff) = −100 mV IS Supply Current VCM = 0.3V 351 400 620 nAVCM = 4.7V 475 600 870 Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units GBW Gain-Bandwidth Product CL = 20 pF, RL = 100 kΩ 6.2 kHz SR Slew Rate AV = +1, VIN = 0V to 5V Falling Edge 1.1 1.2 2.7 V/msRising Edge 1.1 1.2 2.4 θ m Phase Margin CL = 20 pF, RL = 100 kΩ 73 deg Gm Gain Margin CL = 20 pF, RL = 100 kΩ 20 dB en Input-Referred Voltage Noise Density f = 100 Hz 255 nV/ Input-Referred Voltage Noise 0.1 Hz to 10 Hz 22 μVPP in Input-Referred Current Noise f = 100 Hz 100 fA/ EMIRR EMI Rejection Ratio, IN+ and IN− (Note 8) VRF_PEAK = 100 mVP (−20 dBP), f = 400 MHz 121 dB VRF_PEAK = 100 mVP (−20 dBP), f = 900 MHz 121 VRF_PEAK = 100 mVP (−20 dBP), f = 1800 MHz 124 VRF_PEAK = 100 mVP (−20 dBP), f = 2400 MHz 142 Note 1: Absolute Maximum Ratings indicate limits beyond which damage may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Note 5: Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: All limits are guaranteed by testing, statistical analysis or design. Note 7: The short circuit test is a momentary open loop test. Note 8: The EMI Rejection Ratio is defined as EMIRR = 20log (VRF_PEAK/ΔVOS). Note 9: The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. 5 www.national.com LPV521
Ordering Information
Package Part Number Package Marking Transport Media NSC Drawing 5-Pin SC-70 LPV521MG AHA 1k Units Tape and Reel MAA05ALPV521MGE 250 Units Tape and Reel LPV521MGX 3k Units Tape and Reel www.national.com 6 LPV521
Typical Performance Characteristics At TJ = 25°C, unless otherwise specified. Supply Current vs. Supply Voltage 30054504 Supply Current vs. Supply Voltage 30054535 Offset Voltage Distribution 30054573 TCVOS Distribution 30054574 Offset Voltage Distribution 30054575 TCVOS Distribution 30054567 7 www.national.com LPV521
Offset Voltage Distribution 30054568 TCVOS Distribution 30054569 Input Offset Voltage vs. Input Common Mode 30054506 Input Offset Voltage vs. Input Common Mode 30054505 Input Offset Voltage vs. Input Common Mode 30054507 Input Offset Voltage vs. Supply Voltage 30054537 www.national.com 8 LPV521
Input Offset Voltage vs. Supply Voltage 30054538 Input Offset Voltage vs. Output Voltage 30054539 Input Offset Voltage vs. Output Voltage 30054540 Input Offset Voltage vs. Output Voltage 30054541 Input Offset Voltage vs. Sourcing Current 30054542 Input Offset Voltage vs. Sourcing Current 30054543 9 www.national.com LPV521
Input Offset Voltage vs. Sourcing Current 30054544 Input Offset Voltage vs. Sinking Current 30054545 Input Offset Voltage vs. Sinking Current 30054546 Input Offset Voltage vs. Sinking Current 30054547 Sourcing Current vs. Output Voltage 30054508 Sinking Current vs. Output Voltage 30054509 www.national.com 10 LPV521
Sourcing Current vs. Output Voltage 30054510 Sinking Current vs. Output Voltage 30054511 Sourcing Current vs. Output Voltage 30054552 Sinking Current vs. Output Voltage 30054553 Sourcing Current vs. Supply Voltage 30054548 Sinking Current vs. Supply Voltage 30054549 11 www.national.com LPV521
Output Swing High vs. Supply Voltage 30054550 Output Swing Low vs. Supply Voltage 30054551 Input Bias Current vs. Common Mode Voltage 30054514 Input Bias Current vs. Common Mode Voltage 30054515 Input Bias Current vs. Common Mode Voltage 30054516 Input Bias Current vs. Common Mode Voltage 30054564 www.national.com 12 LPV521
Input Bias Current vs. Common Mode Voltage 30054565 Input Bias Current vs. Common Mode Voltage 30054566 PSRR vs. Frequency 30054527 CMRR vs. Frequency 30054560 Frequency Response vs. Temperature 30054523 Frequency Response vs. Temperature 30054524 13 www.national.com LPV521
Frequency Response vs. Temperature 30054522 Frequency Response vs. RL 30054520 Frequency Response vs. RL 30054521 Frequency Response vs. RL 30054519 Frequency Response vs. CL 30054517 Frequency Response vs. CL 30054518 www.national.com 14 LPV521
Frequency Response vs. CL 30054513 Slew Rate vs. Supply Voltage 30054536 Voltage Noise vs. Frequency 30054526 0.1 to 10 Hz Time Domain Voltage Noise 30054561 0.1 to 10 Hz Time Domain Voltage Noise 30054562 0.1 to 10 Hz Time Domain Voltage Noise 30054563 15 www.national.com LPV521
Small Signal Pulse Response 30054531 Small Signal Pulse Response 30054530 Large Signal Pulse Response 30054532 Large Signal Pulse Response 30054533 Overload Recovery Waveform 30054534 EMIRR vs. Frequency 30054572 www.national.com 16 LPV521
Application Information
The LPV521 is fabricated with National Semiconductor's state-of-the-art VIP50 process. This proprietary process dra- matically improves the performance of National Semiconductor's low-power and low-voltage operational am- plifiers. The following sections showcase the advantages of the VIP50 process and highlight circuits which enable ultra- low power consumption.
60 HZ TWIN T NOTCH FILTER
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60 Hz interfer- ence from AC power lines. The circuit of Figure 1 notches out the 60 Hz and provides a gain A V = 2 for the sensor signal represented by a 1 kHz sine wave. Similar stages may be cascaded to remove 2nd and 3rd harmonics of 60 Hz. Thanks to the nA power consumption of the LPV521, even 5 such circuits can run for 9.5 years from a small CR2032 lithium cell. These batteries have a nominal voltage of 3V and an end of life voltage of 2V. With an operating voltage from 1.6V to 5.5V the LPV521 can function over this voltage range. The notch frequency is set by F0 = 1/2πRC. To achieve a 60 Hz notch use R = 10 MΩ and C = 270 pF. If eliminating 50 Hz noise, which is common in European systems, use R = 11.8 MΩ and C = 270 pF. The Twin T Notch Filter works by having two separate paths from VIN to the amplifier’s input. A low frequency path through the resistors R - R and another separate high frequency path through the capacitors C - C. However, at frequencies around the notch frequency, the two paths have opposing phase an- gles and the two signals will tend to cancel at the amplifier’s input. To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter needs to be as balanced as possible. To obtain circuit balance, while over- coming limitations of available standard resistor and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements for the filter components that connect to ground. To make sure passive component values stay as expected clean board with alcohol, rinse with deionized water, and air dry. Make sure board remains in a relatively low humidity en- vironment to minimize moisture which may increase the con- ductivity of board components. Also large resistors come with considerable parasitic stray capacitance which effects can be reduced by cutting out the ground plane below components of concern. Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors, resistor thermal noise, op amp current noise, as well as op amp volt- age noise, must be considered in the noise analysis of the circuit. The noise analysis for the circuit in Figure 1 can be done over a bandwidth of 5 kHz, which takes the conservative approach of overestimating the bandwidth (LPV521 typical GBW/AV is lower). The total noise at the output is approxi- mately 800 µVpp, which is excellent considering the total consumption of the circuit is only 540 nA. The dominant noise terms are op amp voltage noise (550 µVpp), current noise through the feedback network (430 µVpp), and current noise through the notch filter network (280 µVpp). Thus the total circuit's noise is below 1/2 LSB of a 10 bit system with a 2 V reference, which is 1 mV. 30054576 FIGURE 1. 60 Hz Notch Filter FIGURE 2. 60 Hz Notch Filter Waveform
the op amp might start oscillating. swing and reduced output current drive. FIGURE 5. Resistive Isolation of Capacitive Load below no isolation resistor is needed. FIGURE 6. Step Response important design consideration for precision signal paths. rejection provide immunity against low frequency noise (i.e.
60 Hz or 50 Hz mains) but are ineffective against RF interfer-
mation on EMIRR, please refer to AN-1698. 0.1 μF ceramic capacitor placed close to the V+ and V− pins. components close to the op amps' pins.
Physical Dimensions inches (millimeters) unless otherwise noted 5-Pin SC-70 www.national.com 20 LPV521
21 www.national.com LPV521
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