LPC844M201JHI33

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 97

Technical content

1. General description The LPC84x are an Arm Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and 16 KB of SRAM. The peripheral complement of the LPC84x includes a CRC engine, four I2C-bus interfaces, up to five USARTs, up to two SPI interfaces, Capacitive Touch Interface, one multi-rate timer, self-wake-up timer, SCTimer/PWM, one general purpose 32-bit counter/timer, a DMA, one 12-bit ADC, two 10-bit DACs, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 54 general-purpose I/O pins. For additional documentation related to the LPC84x parts, see Section 18 2. Features and benefits  System:  Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port.  Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  System tick timer.  AHB multilayer matrix.  Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported.  Micro Trace Buffer (MTB).  Memory:  Up to 64 KB on-chip flash programming memory with 64 Byte page write and erase.  Fast Initialization Memory (FAIM) allowing the user to configure chip behavior on power-up.  Code Read Protection (CRP)  Up to 16 KB SRAM consisting of two 8 KB contiguous SRAM banks. One 8 KB of SRAM can be used for MTB.  Bit-band addressing supported to permit atomic operations to modify a single bit.  ROM API support:  Boot loader.  Supports Flash In-Application Programming (IAP). LPC84x 32-bit Arm® Cortex®-M0+ microcontroller; up to 64 KB flash and 16 KB SRAM; FAIM memory; 12-bit ADC; 10-bit DACs; Comparator; Capacitive Touch Interface Rev. 1.7 — 27 February 2018 Product data sheet

Product data sheet Rev. 1.7 — 27 February 2018 2 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller  Supports In-System Programming (ISP) through USART, SPI, and I2C.  FAIM API.  FRO API.  On-chip ROM APIs for integer divide.  Digital peripherals:  High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and digital filter. GPIO direction control supports independent set/clear/toggle of individual bits.  High-current source output driver (20 mA) on four pins.  High-current sink driver (20 mA) on two true open-drain pins.  GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs.  Switch matrix for flexible configuration of each I/O pin function.  CRC engine.  DMA with 25 channels and 13 trigger inputs.  Capacitive Touch Interface.  Timers:  One SCTimer/PWM with five input and seven output functions (including capture and match) for timing and PWM applications. Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 8 match/captures, 8 events, and 8 states.  One 32-bit general purpose counter/timer, with four match outputs and three capture inputs. Supports PWM mode, external count, and DMA.  Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.  Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a low-power, low-frequency internal oscillator, or an external clock input in the always-on power domain.  Windowed Watchdog timer (WWDT).  Analog peripherals:  One 12-bit ADC with up to 12 input channels with multiple internal and external trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports two independent conversion sequences.  Comparator with five input pins and external or internal reference voltage.  Two 10-bit DACs.  Serial peripherals:  Five USART interfaces with pin functions assigned through the switch matrix and two fractional baud rate generators.  Two SPI controllers with pin functions assigned through the switch matrix.  Four I 2C-bus interfaces. One I2C supports Fast-mode Plus with 1 Mbit/s data rates on two true open-drain pins and listen mode. Three I2Cs support data rates up to 400 kbit/s on standard digital pins.  Clock generation:

Product data sheet Rev. 1.7 — 27 February 2018 3 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller  Free Running Oscillator (FRO). This oscillator provides a selectable 18 MHz, 24 MHz, and 30 MHz outputs that can be used as a system clock. Also, these outputs can be divided down to 1.125 MHz, 1.5 MHz, 1.875 MHz, 9 MHz, 12 MHz, and 15 MHz for system clock. The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range of 0 C to 70 C.  Low power boot at 1.5 MHz using FAIM memory.  External clock input for clock frequencies of up to 25 MHz.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Low power oscillator can be used as a clock source to the watchdog timer.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input, or the internal FRO.  Clock output function with divider that can reflect all internal clock sources.  Power control:  Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode.  Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and I2C peripherals.  Timer-controlled self wake-up from deep power-down mode.  Power-On Reset (POR).  Brownout detect (BOD).  Unique device serial number for identification.  Single power supply (1.8 V to 3.6 V).  Operating temperature range -40 °C to +105 °C.  Available in LQFP64, LQFP48, HVQFN48, and HVQFN33 packages. 3. Applications  Sensor gateways  Simple motor control  Industrial  Portables and wearables  Gaming controllers  Lighting  8/16-bit applications  Motor control  Consumer  Fire and security applications  Climate control

4.1 Ordering options

Table 1. Ordering information Table 2. Ordering options

• First line: LPC84xMy01 – y: 3 or 2
• Second line: xxxxxx
• Third line: xxxyywwx[R]x – yyww: Date code with yy = year and ww = week. – xR = Boot code version and device revision. The LPC84x HVQFN48 and HVQFN33 packages have the following top-side marking:
• First line: LPC84xMy01 – y: 3 or 2
• Second line: xxxxxx
• Third line: xxxyywwx[R]x – yyww: Date code with yy = year and ww = week. – xR = Boot code version and device revision. Fig 1. HVQFN48, HVQFN33 package marking Fig 2. LQFP64, LQFP48 package marking aaa-014382 Terminal 1 index area NXP n Terminal 1 index area aaa-011231

Table 3. Device revision table

Product data sheet Rev. 1.7 — 27 February 2018 6 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller 6. Block diagram Gray-shaded blocks show peripherals that can provide hardware triggers or fixed DMA requests for DMA transfers. Fig 3. LPC84x block diagram aaa-022793 CLKOUT Vdd CLKIN XTALIN XTALOUTSWD Port JTAG Test and Boundary Scan interface RESET Clock Generation, Power Control, and other System Functions Voltage Regulator DEBUG INTERFACE IOP bus GPIOs GPIOs AND GPOINT Flash interface Flash 64 kB General Purpose DMA controller MTB slave interface DMA registers CRC Multilayer AHB Matrix AHB to APB bridge FAIM 256-bit T0 Match/ Capture M1M0 I2C2,3 COMP Inputs ADC Inputs and Triggers DAC1 outputs DAC0 outputs PIOs UART0,1,2, 3,4 CAPT SPI0,1 I2C0,1 APB slave group Watchdog Osc Windowed WDT Note: SCT Timer/ PWM ARM Cortex M0+ System control IOCON Registers Flash Registers (NVMC) CTIMER32 I2Cs 2 and 3 UARTs 0-4 CapTouch SPIs 0 and 1 I2Cs 0 and 1 Periph Input Mux Selects Comparator PMU Registers 12-bit ADC 10-bit DAC1 10-bit DAC0 FAIM Registers Switch Matrix Wakeup Timer Multi-Rate Timer Boot ROM 16 kB SRAM/MTB 8 kB SRAM 8 kB Yellow shaded blocks support general purpose DMA

Product data sheet Rev. 1.7 — 27 February 2018 7 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller 7. Pinning information

7.1 Pinning

Fig 4. Pin configuration LQFP64 package PIO1_8/CAPT_YL PIO0_0/ACMP_ I1/TDO PIO0_13/ADC_10 PIO1_7/CAPT_X8 PIO1_9/CAPT_YH PIO0_6/ADC_1/ACMPVREF PIO0_12 PIO0_7/ADC_0 PIO0_5/RESET PIO1_19 PIO0_4/ADC_11/TRST/WAKEUP PIO1_18 VDD VREFP VSS VREFN PIO1_12 VSS VDDPIO0_28/WKTCLKIN PIO1_6/CAPT_X7PIO1_13 PIO1_17SWCLK/PIO0_3/TCK PIO1_16PIO0_31/CAPT_X0 PIO1_5/CAPT_6 PIO1_0/CAPT_X1 PIO0_8/XTALIN PIO0_11/I2C0_SDA PIO0_9/XTALOUT PIO0_10/I2C0_SCL PIO1_10 PIO1_1/CAPT_X2 PIO0_17/ADC_9/DACOUT_0 PIO0_16 PIO1_11 PIO1_2/CAPT_X3 PIO0_18/ADC_8 PIO0_27 PIO0_19/ADC_7 PIO1_14 PIO1_21 PIO0_26 PIO0_20/ADC_6 PIO1_15 PIO0_21/ADC_5 VSS PIO1_20 VDD PIO0_22/ADC_4 PIO0_25 PIO0_30/ACMP_I5 PIO0_24 VSSA PIO1_3/CAPT_X4 VDDA PIO0_15 PIO0_23/ADC_3/ACMP_I4 PIO1_4/CAPT_X5 PIO0_29/DACOUT_1 PIO0_1/ACMP_I2/CLKIN/TDI PIO0_14/ACMP_I3/ADC_2 aaa-026593 SWDIO/PIO0_2/TMS

Product data sheet Rev. 1.7 — 27 February 2018 8 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 5. Pin configuration LQFP48 package PIO1_8/CAPT_YL PIO0_0/ACMP_I1/TDO PIO0_13/ADC_10 PIO1_7/CAPT_X8 PIO1_9/CAPT_YH PIO0_6/ADC_1/ACMPV REF PIO0_12 PIO0_7/ADC_0 VREFP PIO0_4/ADC_11/TRST/WAKEUP VREFN PIO0_28/WKTCLKIN V SS SWDCLK/PIO0_3/TCK V DD PIO0_31/CAPT_X0 PIO1_6/CAPT_X7 SWDIO/PIO0_2/TMS PIO1_5/CAPT_X6 PIO1_0/CAPT_X1 PIO0_8/XTALIN PIO0_11/I2C0_SDA PIO0_9/XTALOUT PIO0_10/I2C0_SCL PIO0_17/ADC_9/DACOUT_0 PIO1_1/CAPT_X2 PIO0_18/ADC_8 PIO0_16 PIO0_19/ADC_7 PIO1_2/CAPT_X3 PIO0_20/ADC_6 PIO0_27 PIO0_21/ADC_5 PIO0_26 PIO0_22/ADC_4 PIO0_25 PIO0_30/ACMP_I5 PIO0_24 VSSA PIO1_3/CAPT_X4 VDDA PIO0_15 PIO0_23/ADC_3/ACMP_I4 PIO1_4/CAPT_X5 PIO0_1/ACMP_I2/CLKIN/TDI PIO0_29/DACOUT_1 PIO0_14/ACMP_I3/ADC_2 aaa-026594 3724 PIO0_5/RESET

Product data sheet Rev. 1.7 — 27 February 2018 9 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 6. Pin configuration HVQFN48 package aaa-026596 PIO0_9/XTALOUT PIO1_0/CAPT_X1 PIO0_11/I2C0_SDA PIO0_8/XTALIN SWDIO/PIO0_2/TMS PIO1_5/CAPT_X6 PIO0_31/CAPT_X0 PIO1_6/CAPT_X7 SWDCLK/PIO0_3/TCK VDD PIO0_28/WKTCLKIN VSS PIO0_4/ADC_11/TRST/WAKEUP VREFN PIO0_5/RESET VREFP PIO0_12 PIO0_7/ADC_0 PIO1_9/CAPT_YH PIO0_6/ADC_1/ACMPV REF PIO0_13/ADC_10 PIO1_7/CAPT_X8 PIO1_8/CAPT_YL PIO0_0/ACMPIN_I1/TDO PIO0_10/I2C0_SCL PIO1_01/CAPT_X2 PIO0_16 PIO1_2/CAPT_X3 PIO0_27 PIO0_26 PIO0_25 PIO0_24 PIO1_3/CAPT_X4 PIO0_15 PIO1_4/CAPT_X5 PIO0_1/ACMP_I2/CLKIN/TDI PIO0_17/ADC_9/DACOUT_0 PIO0_18/ADC_8 PIO0_19/ADC_7 PIO0_20/ADC_6 PIO0_21/ADC_5 PIO0_22/ADC_4 PIO0_30/ACMP_I5 VSSA VDDA PIO0_23/ADC_3/ACMP_I4 PIO0_29/DACOUT_1 PIO0_14/ADC_2/ACMP_I3 Transparent top view 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 terminal 1 index area

Product data sheet Rev. 1.7 — 27 February 2018 10 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

7.2 Pin description

The pin description table shows the pin functions that are fixed to specific pins on each package. See Table 4. These fixed-pin functions are selectable through the switch matrix between GPIO and the comparator, ADC, SWD, RESET, and the XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only. Movable functions for the I 2C, USART, SPI, CTimer, SCT pins, and other peripherals can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions. The following exceptions apply: Do not assign more than one output to any pin. However, an output and/or one or more inputs can be assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is disabled. Pin PIO0_4 triggers a wake-up from deep power-down mode. If the part must wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. Fig 7. Pin configuration HVQFN33 package aaa-026595 Transparent top view PIO0_9/XTALOUT SWDIO/PIO0_2/TMS PIO0_11/I2C0_SDA PIO0_8/XTALIN SWCLK/PIO0_3/TCK VDD PIO0_28/WKTCLKIN VREFN PIO0_4/ADC_11/TRST/WAKEUP VREFP PIO0_5/RESET PIO0_7/ADC_0 PIO0_12 PIO0_6/ADC_1/ACMPV REF PIO0_13/ADC_10 PIO0_0/ACMP_I1/TDO PIO0_10/I2C0_SCL PIO0_16 PIO0_27 PIO0_26 PIO0_25 PIO0_24 PIO0_15 PIO0_1/ACMP_I2/CLKINTDI PIO0_17/ADC_9/DACOUT_0 PIO0_18/ADC_8 PIO0_19/ADC_7 PIO0_20/ADC_6 PIO0_21/ADC_5 PIO0_22/ADC_4 PIO0_23/ADC_3/ACMP_I4 PIO0_14/ACMP_I3/ADC_2 8 17 7 18 6 19 5 20 2 23 1 24 terminal 1 index area

33 VSS

PIO0_16 are high drive output pins. PIO0_4 by hardware when the part is in boundary scan mode. Table 4. Pin description 48 36 36 24 [2] I; PU IO PIO0_0 — General-purpose port 0 input/output 0. In boundary scan mode: TDO (Test Data Out). A ACMP_I1 — Analog comparator input 1. 32 24 24 16 [2] I; PU IO PIO0_1 — General-purpose port 0 input/output 1. In boundary scan mode: TDI (Test Data In). A ACMP_I2 — Analog comparator input 2. I CLKIN — External clock input. mode: TMS (Test Mode Select). I/O PIO0_2 — General-purpose port 0 input/output 2. In boundary scan mode: TCK (Test Clock). IO PIO0_3 — General-purpose port 0 input/output 3. 66 6 4 [3] I; PU IO PIO0_4 — General-purpose port 0 input/output 4. In boundary scan mode: TRST (Test Reset).

execution to begin at address 0. IO PIO0_5 — General-purpose port 0 input/output 5. 46 34 34 23 [10] I; PU IO PIO0_6 — General-purpose port 0 input/output 6. PIO0_7/ADC_0 45 33 33 22 [2] I; PU IO PIO0_7 — General-purpose port 0 input/output 7. PIO0_8/XTALIN 34 26 26 18 [8] I; PU IO PIO0_8 — General-purpose port 0 input/output 8. PIO0_9/XTALOUT 33 25 25 17 [8] I; PU IO PIO0_9 — General-purpose port 0 input/output 9. A XTALOUT — Output from the oscillator circuit. I2C0_SCL — Open-drain I2C-bus clock input/output. the I/O configuration register. I2C0_SDA — Open-drain I2C-bus data input/output. the I/O configuration register. PIO0_12 4 4 4 2 [4] I; PU IO PIO0_12 — General-purpose port 0 input/output 12. starts the ISP command handler. PIO0_13/ADC_10 2 2 2 1 [2] I; PU IO PIO0_13 — General-purpose port 0 input/output 13.

49 37 37 25 [2] I; PU IO PIO0_14 — General-purpose port 0 input/output 14. A ACMP_I3 — Analog comparator common input 3. PIO0_15 30 22 22 15 [5] I; PU IO PIO0_15 — General-purpose port 0 input/output 15. PIO0_16 19 15 15 10 [4] I; PU IO PIO0_16 — General-purpose port 0 input/output 16. 63 48 48 32 [2] I; PU IO PIO0_17 — General-purpose port 0 input/output 17. PIO0_18/ADC_8 61 47 47 31 [2] I; PU IO PIO0_18 — General-purpose port 0 input/output 18. PIO0_19/ADC_7 60 46 46 30 [2] I; PU IO PIO0_19 — General-purpose port 0 input/output 19. PIO0_20/ADC_6 58 45 45 29 [2] I; PU IO PIO0_20 — General-purpose port 0 input/output 20. PIO0_21/ADC_5 57 44 44 28 [2] I; PU IO PIO0_21 — General-purpose port 0 input/output 21. PIO0_22/ADC_4 55 43 43 27 [2] I; PU IO PIO0_22 — General-purpose port 0 input/output 22. 51 39 39 26 [2] I; PU IO PIO0_23 — General-purpose port 0 input/output 23. A ACMP_I4 — Analog comparator common input 4. PIO0_24 28 20 20 14 [5] I; PU IO PIO0_24 — General-purpose port 0 input/output 24. In ISP mode, this is the U0_RXD pin. PIO0_25 27 19 19 13 [5] I; PU IO PIO0_25 — General-purpose port 0 input/output 25. In ISP mode, this pin is the U0_TXD pin. PIO0_26 23 18 18 12 [5] I; PU IO PIO0_26 — General-purpose port 0 input/output 26. PIO0_27 21 17 17 11 [5] I; PU IO PIO0_27 — General-purpose port 0 input/output 27. 10 7 7 5 [3] I; PU IO PIO0_28 — General-purpose port 0 input/output 28. 50 38 38 - [5] I; PU IO PIO0_29 — General-purpose port 0 input/output 29. PIO0_30/ACMP_I5 54 42 42 - [5] I; PU IO PIO0_30 — General-purpose port 0 input/output 30. A ACMP_I5 — Analog comparator common input 5.

PIO0_31/CAPT_X0 13 9 9 - [5] I; PU IO PIO0_31 — General-purpose port 0 input/output 31. CAPT_X0 — Capacitive Touch X sensor 0. PIO1_0/CAPT_X1 15 11 11 - [5] I; PU IO PIO1_0 — General-purpose port 1 input/output 0. CAPT_X1 — Capacitive Touch X sensor 1. PIO1_1/CAPT_X2 18 14 14 - [5] I; PU IO PIO1_1 — General-purpose port 1 input/output 1. CAPT_X2 — Capacitive Touch X sensor 2. PIO1_2/CAPT_X3 20 16 16 - [5] I; PU IO PIO1_2 — General-purpose port 1 input/output 2. CAPT_X3 — Capacitive Touch X sensor 3. PIO1_3/CAPT_X4 29 21 21 - [5] I; PU IO PIO1_3 — General-purpose port 1 input/output 3. CAPT_X4 — Capacitive Touch X sensor 4. PIO1_4/CAPT_X5 31 23 23 - [5] I; PU IO PIO1_4 — General-purpose port 1 input/output 4. CAPT_X5 — Capacitive Touch X sensor 5. PIO1_5/CAPT_X6 35 27 27 - [5] I; PU IO PIO1_5 — General-purpose port 1 input/output 5. CAPT_X6 — Capacitive Touch X sensor 6. PIO1_6/CAPT_X7 38 28 28 - [5] I; PU IO PIO1_6 — General-purpose port 1 input/output 6. CAPT_X7 — Capacitive Touch X sensor 7. PIO1_7/CAPT_X8 47 35 35 - [5] I; PU IO PIO1_7 — General-purpose port 1 input/output 7. CAPT_X8 — Capacitive Touch X sensor 8. PIO1_8/CAPT_YL 1 1 1 - [5] I; PU IO PIO1_8 — General-purpose port 1 input/output 8. CAPT_YL — Capacitive Touch Y Low. PIO1_9/CAPT_YH 3 3 3 - [5] I; PU IO PIO1_9 — General-purpose port 1 input/output 9. CAPT_YH — Capacitive Touch Y High. PIO1_10 64 - - - [5] I; PU IO PIO1_10 — General-purpose port 1 input/output 10. PIO1_11 62 - - - [5] I; PU IO PIO1_11 — General-purpose port 1 input/output 11. PIO1_12 9 - - - [5] I; PU IO PIO1_12 — General-purpose port 1 input/output 12. PIO1_13 11 - - - [5] I; PU IO PIO1_13 — General-purpose port 1 input/output 13. PIO1_14 22 - - - [5] I; PU IO PIO1_14 — General-purpose port 1 input/output 14. PIO1_15 24 - - - [5] I; PU IO PIO1_15 — General-purpose port 1 input/output 15. PIO1_16 36 - - - [5] I; PU IO PIO1_16 — General-purpose port 1 input/output 16. PIO1_17 37 - - - [5] I; PU IO PIO1_17 — General-purpose port 1 input/output 17. PIO1_18 43 - - - [5] I; PU IO PIO1_18 — General-purpose port 1 input/output 18. PIO1_19 44 - - - [5] I; PU IO PIO1_19 — General-purpose port 1 input/output 19. PIO1_20 56 - - - [5] I; PU IO PIO1_20 — General-purpose port 1 input/output 20. PIO1_21 59 - - - [5] I; PU IO PIO1_21 — General-purpose port 1 input/output 21. VDDA 52 40 40 Analog supply voltage.

different power modes”. For termination on unused pins, see Section 14.5 “Termination of unused pins”. configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. WKTCLKIN pin” for the WKTCLKIN input. [5] 5 V tolerant pad providing digital I/O functions with conf igurable pull-up/pull-down resistors and configurable hysteresis. available in deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from deep power-down mode. oscillator. When configured for XTALIN and XTALOUT, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [9] The WKTCLKIN function is enabled in the DPDCTRL re gister in the PMU. See the LPC84x user manual. [11] Thermal pad for HVQFN33. VSSA 53 41 41 Analog ground. VREFN 41 31 31 20 - - ADC negative reference voltage. Table 5. Movable functions (assign to pins PIO 0_0 to PIO0_31, PIO1_0 to PIO1_21 through Ux_TXD O Transmitter output for USART0 to USART4. Ux_RXD I Receiver input fo r USART0 to USART4. Ux_RTS O Request To Send output for USART0 to USART4. Ux_CTS I Clear To Send input for USART0 to USART4. Ux_SCLK I/O Serial clock input/output for USART0 to USART4 in synchronous mode. SPIx_SCK I/O Serial clock for SPI0 and SPI1. SPIx_MISO I/O Master In Slave Out for SPI0 and SPI1.

SPIx_SSEL0 I/O Slave select 0 for SPI0 and SPI1. SPIx_SSEL1 I/O Slave select 1 for SPI0 and SPI1. SPIx_SSEL2 I/O Slave select 2 for SPI0 and SPI1. SPIx_SSEL3 I/O Slave select 3 for SPI0 and SPI1. SCT_PIN0 I Pin input 0 to the SCT input multiplexer. SCT_PIN1 I Pin input 1 to the SCT input multiplexer. SCT_PIN2 I Pin input 2 to the SCT input multiplexer. SCT_PIN3 I Pin input 3 to the SCT input multiplexer. 2C1, I2C2, and I2C3 bus data input/output. I2Cx_SCL I/O I 2C1, I2C2, and I2C3 bus clock input/output. ACMP_O O Analog comparator output. GPIO_INT_BMAT O Output of the pattern match engine. T0_MAT0 O Timer Match channel 0. T0_MAT1 O Timer Match channel 1. T0_MAT2 O Timer Match channel 2. T0_MAT3 O Timer Match channel 3. T0_CAP0 I Timer Capture channel 0. T0_CAP1 I Timer Capture channel 1. T0_CAP2 I Timer Capture channel 2.

Product data sheet Rev. 1.7 — 27 February 2018 17 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller 8. Functional description

8.1 Arm Cortex-M0+ core

The Arm Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a two-stage pipeline. The core revision is r0p1. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The Arm Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer.

8.2 On-chip flash program memory

The LPC84x contain up to 64 KB of on-chip flash program memory. The flash memory supports a 64 Byte page size with page write and erase.

8.3 On-chip SRAM

The LPC84x contain a total of 16KB on-chip static RAM data memory in two separate SRAM blocks with one combined clock for both SRAM blocks. One 8 KB of SRAM can be used for MTB. A bit-band module is added in series with the AHB matrix to allow atomic read-modify-write operations acting on a single bit.

8.4 FAIM memory

The LPC84x includes the FAIM memory and is used to configure the part at start-up. It is 128/256 bits in size and is used to configure the following:

• Clocks and PMU for low-power start-up.
• Low power boot at 1.5 MHz using FAIM memory.
• Pin configuration including direction and pull- up or pull-down.
• Specification of pins to use for ISP entry for each serial peripheral.
• Select whether SWCLK and SWDIO are enabled on reset. Remark: The FAIM programming voltage range is 3.0 V  Vdd  3.6 V.

8.5 On-chip ROM

The on-chip ROM contains the bootloader:

• Boot loader.
• Supports Flash In-Application Programming (IAP).
• Supports In-System Programming (ISP) through USART, SPI, and I2C.
• On-chip ROM APIs for integer divide.
• FAIM API.
• FRO API.

Product data sheet Rev. 1.7 — 27 February 2018 18 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.6 Memory map

The LPC84x incorporates several distinct memory regions. Figure 8 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The Arm private peripheral bus includes the Arm core registers for controlling the NVIC, the system tick timer (SysTick), and the reduced power modes. Fig 8. LPC84x AHB Memory mapping aaa-026589 FAIM memory MTB registers DMA controller SCTimer / PWM AHB perpherals CRC engine 0x5001 4000 0x5001 0000 0x5000 C000 0x5000 8000 0x5000 4000 0x5000 0000 (reserved) private peripheral bus (reserved) GPIO interrupts Memory space GPIO (reserved) (reserved) (reserved) (reserved) (reserved) active interrupt vectors Boot ROM RAM1 RAM0 AHB peripherals APB peripherals Flash memory (up to 64 KB) 0xFFFF FFFF 0xE010 0000 0xE000 0000 0xA000 8000 0xA000 4000 0xA000 0000 0x5001 4000 0x5000 0000 0x4008 0000 0x4000 0000 0x1000 4000 0x1000 2000 0x1000 0000 0x0F00 4000 0x0F00 0000 0x0001 0000 0x0000 0000 0x0000 00C0 0x0000 0000 (reserved) UART4 UART3 UART2 APB perpherals UART1 UART0 CapTouch SPI1 SPI0 I2C1 I2C0 (reserved) Syscon IOCON Flash controller (reserved) CTIMER 0 I2C3 I2C2 Input Multiplexing (reserved) Analog Comparator PMU ADC DAC1 DAC0 FAIM controller Switch Matrix Wake-up Timer Multi-Rate Timer Watchdog timer 31-30 0x4007 FFFF 0x4007 8000 0x4007 4000 0x4007 0000 0x4006 C000 0x4006 8000 0x4006 4000 0x4006 0000 0x4005 C000 0x4005 8000 0x4005 4000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000

Product data sheet Rev. 1.7 — 27 February 2018 19 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.7 Nested Vectored Inte rrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

8.7.1 Features

• Nested Vectored Interrupt Controller is a part of the Arm Cortex-M0+.
• Tightly coupled interrupt controller provides low interrupt latency.
• Controls system exceptions and peripheral interrupts.
• Supports 32 vectored interrupts.
• In the LPC84x, the NVIC supports vectored interrupts for each of the peripherals and the eight pin interrupts.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation using the Arm exceptions SVCall and PendSV.
• Supports NMI.

8.7.2 Interrupt sources

Each peripheral device has at least one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source.

8.8 System tick timer

The Arm Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).

8.9 I/O configuration

The IOCON block controls the configuration of the I/O pins. Each digital or mixed digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10 and PIO0_11) in Table 4 can be configured as follows:

• Enable or disable the weak internal pull-up and pull-down resistors.
• Select a pseudo open-drain mode. The input cannot be pulled up above VDD. The pins are not 5 V tolerant when VDD is grounded.
• Program the input glitch filter with different filter constants using one of the IOCON divided clock signals (IOCONCLKCDIV, see Figure 11 “LPC84x clock generation”). You can also bypass the glitch filter.
• Invert the input signal.
• Hysteresis can be enabled or disabled.
• For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard digital operation, for I2C standard and fast modes, or for I2C Fast mode+.
• The switch matrix setting enables the analog input mode on pins with analog and digital functions. Enabling the analog mode disconnects the digital functionality. Remark: The functionality of each I/O pin is flexible and is determined entirely through the switch matrix. See Section 8.10 for details.

Product data sheet Rev. 1.7 — 27 February 2018 20 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.9.1 Standard I/O pad configuration

Figure 9 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver with configurable open-drain output.
• Digital input: Weak pull-up resistor (PMOS device) enabled/disabled.
• Digital input: Weak pull-down resistor (NMOS device) enabled/disabled.
• Digital input: Repeater mode enabled/disabled.
• Digital input: Programmable input digital filter selectable on all pins.
• Analog input: Selected through the switch matrix. Fig 9. Standard I/O pad configuration PIN VDD VDD ESD VSS ESD strong pull-up strong pull-down VDD weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input analog input SWM PINENABLE for analog input pin configured as digital output driver pin configured as digital input pin configured as analog input PROGRAMMABLE DIGITAL FILTER aaa-014392

Product data sheet Rev. 1.7 — 27 February 2018 21 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.10 Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions, for example, the USART, SPI, SCTimer/PWM, CTimer, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in Table 5. Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. The fixed-pin functions are listed in Table 4. If a fixed-pin function is disabled, any other movable function can be assigned to this pin.

8.11 Fast General-Purpo se parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC84x use accelerated GPIO functions:

• GPIO registers are on the Arm Cortex-M0+ IO bus for fastest possible single-cycle I/O timing, allowing GPIO toggling with rates of up to 15 MHz.
• An entire port value can be written in one instruction.
• Mask, set, and clear operations are supported for the entire port. All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.

8.11.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in one write operation.
• Direction control of individual bits.
• All I/O default to GPIO inputs with internal pull-up resistors enabled after reset - except for the I2C-bus true open-drain pins PIO0_10 and PIO0_11.
• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the IOCON block for each GPIO pin (see Figure 9).
• Direction (input/output) can be set and cleared individually.
• Pin direction bits can be toggled.

8.12 Pin interrupt/pattern match engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. The pattern match engine can be used, with software, to create complex state machines based on pin inputs.

Product data sheet Rev. 1.7 — 27 February 2018 22 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Any digital pin, independently of the function selected through the switch matrix, can be configured through the SYSCON block as input to the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match engine are on the IO+ bus for fast single-cycle access.

8.12.1 Features

• Pin interrupts – Up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. – Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. – Level-sensitive interrupt pins can be HIGH- or LOW-active. – Pin interrupts can wake up the LPC84x from sleep mode, deep-sleep mode, and power-down mode.
• Pin interrupt pattern match engine – Up to eight pins can be selected from all digital pins to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins. – Each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. – Any occurrence of a pattern match can be also programmed to generate an RXEV notification to the Arm CPU. The RXEV signal can be connected to a pin. – The pattern match engine does not facilitate wake-up.

8.13 DMA controller

The DMA controller can access all memories and the USART, SPI, I2C, DAC, and Capacitive Touch. DMA transfers can also be triggered by internal events like the ADC interrupts, the pin interrupts (PININT0 and PININT1), the SCTimer DMA requests, CTimer, and the DMA trigger outputs.

8.13.1 Features

• Twenty five channels with each channel connected to peripheral request inputs.
• DMA operations can be triggered by on-chip events or by two pin interrupts. Each DMA channel can select one trigger input from13 sources.
• Priority is user selectable for each channel.
• Continuous priority arbitration.
• Address cache with two entries.
• Efficient use of data bus.
• Supports single transfers up to 1,024 words.
• Address increment options allow packing and/or unpacking data.

Product data sheet Rev. 1.7 — 27 February 2018 23 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.13.2 DMA trigger input MUX (TRIGMUX)

Each DMA trigger is connected to a programmable multiplexer which connects the trigger input to one of multiple trigger sources. Each multiplexer supports the same trigger sources: the ADC sequence interrupts, the SCT DMA request lines, and pin interrupts PININT0 and PININT1, and the outputs of the DMA triggers 0 and 1 for chaining DMA triggers.

8.14 USART0/1/2/3/4

All USART functions are movable functions and are assigned to pins through the switch matrix.

8.14.1 Features

• Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins except the open-drain pins.
• 7, 8, or 9 data bits and 1 or 2 stop bits
• Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option.
• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.)
• Parity generation and checking: odd, even, or none.
• One transmit and one receive data buffer.
• RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output.
• Received data and status can optionally be read from a single register
• Break generation and detection.
• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
• Built-in Baud Rate Generator.
• A fractional rate divider is shared among all UARTs.
• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected.
• Separate data and flow control loopback modes for testing.
• Baud rate clock can also be output in asynchronous mode.

8.15 SPI0/1

All SPI functions are movable functions and are assigned to pins through the switch matrix.

8.15.1 Features

• Maximum data rates of up to 30 Mbit/s in master mode and up to 18 Mbit/s in slave mode for SPI functions connected to all digital pins except the open-drain pins.

Product data sheet Rev. 1.7 — 27 February 2018 24 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data, which can be useful while setting up an SPI memory.
• Control information can optionally be written along with data, which allows very versatile operation, including “any length” frames.
• One Slave Select input/output with selectable polarity and flexible usage. Remark: Texas Instruments SSI and National Microwire modes are not supported.

8.16 I 2C-bus interface (I2C0/1/2/3)

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (for example, an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master. The I2C0-bus functions are fixed-pin functions. All other I2C-bus functions for I2C1/2/3 are movable functions and can be assigned through the switch matrix to any pin. However, only the true open-drain pins provide the electrical characteristics to support the full I2C-bus specification (see Ref. 3).

8.16.1 Features

• I2C0 supports Fast-mode Plus with data rates of up to 1 Mbit/s in addition to standard and fast modes on two true open-drain pins.
• True open-drain pins provide fail-safe operation: When the power to an I2C-bus device is switched off, the SDA and SCL pins connected to the I2C0-bus are floating and do not disturb the bus.
• I2C1/2/3 support standard and fast mode with data rates of up to 400 kbit/s.
• Independent Master, Slave, and Monitor functions.
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I2C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.

8.17 Capacitive Touch Interface

The Capacitive Touch interface is designed to handle up to nine capacitive buttons in different sensor configurations, such as slider, rotary, and button matrix. It operates in sleep, deep sleep, and power-down modes, allowing very low power performance.

Product data sheet Rev. 1.7 — 27 February 2018 25 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller The Capacitive Touch module measures the change in capacitance of an electrode plate when an earth-ground connected object (for example, finger) is brought within close proximity.

8.18 SCTimer/PWM

The SCTimer/PWM can perform basic 16-bit and 32-bit timer/counter functions with match outputs and external and internal capture inputs. In addition, the SCTimer/PWM can employ up to eight different programmable states, which can change under the control of events, to provide complex timing patterns. The inputs to the SCT are multiplexed between movable functions from the switch matrix and internal connections such as the ADC threshold compare interrupt, the comparator output, and the Arm core signals Arm_TXEV and DEBUG_HALTED. The signal on each SCT input is selected through the INPUT MUX. All outputs of the SCT are movable functions and are assigned to pins through the switch matrix. One SCT output can also be selected as one of the ADC conversion triggers.

8.18.1 Features

• Each SCTimer/PWM supports: – Eight match/capture registers. – Eight events. – Eight states. – Five inputs. The fifth input is hard-wired to a clock source. Each input is configurable through an input multiplexer to use one of four external pins (connected through the switch matrix) or one of four internal sources. The maximum input signal frequency is 25 MHz. – Six outputs. Connected to pins through the switch matrix.
• Counter/timer features: – Each SCTimer is configurable as two 16-bit counters or one 32-bit counter. – Counters can be clocked by the system clock or selected input. – Configurable as up counters or up-down counters. – Configurable number of match and capture registers. Up to eight match and capture registers total. – Upon match create the following events: interrupt; stop, limit, halt the timer or change counting direction; toggle outputs. – Counter value can be loaded into capture register triggered by a match or input/output toggle.
• PWM features: – Counters can be used with match registers to toggle outputs and create time-proportioned PWM signals. – Up to six single-edge or dual-edge PWM outputs with independent duty cycle and common PWM cycle length.
• Event creation features:

Product data sheet Rev. 1.7 — 27 February 2018 26 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller – The following conditions define an event: a counter match condition, an input (or output) condition such as a rising or falling edge or level, a combination of match and/or input/output condition. – Selected events can limit, halt, start, or stop a counter or change its direction. – Events trigger state changes, output toggles, interrupts, and DMA transactions. – Match register 0 can be used as an automatic limit. – In bidirectional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs.

• State control features: – A state is defined by events that can happen in the state while the counter is running. – A state changes into another state as a result of an event. – Each event can be assigned to one or more states. – State variable allows sequencing across multiple counter cycles.
• One SCTimer match output can be selected as ADC hardware trigger input.

8.18.2 SCTimer/PWM input MUX (INPUT MUX)

Each input of the SCTimer/PWM is connected to a programmable multiplexer which allows to connect one of multiple internal or external sources to the input. The available sources are the same for each SCTimer/PWM input and can be selected from four pins configured through the switch matrix, the ADC threshold compare interrupt, the comparator output, and the Arm core signals Arm_TXEV and DEBUG_HALTED.

8.19 CTIMER

8.19.1 General-purpose 32-bit timers/external event counter

The LPC84x has one general-purpose 32-bit timer/counter. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.

8.19.2 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Up to three 32-bit captures can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. The number of capture inputs for each timer that are actually available on device pins can vary by device.
• Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation.

Product data sheet Rev. 1.7 — 27 February 2018 27 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller – Reset timer on match with optional interrupt generation. – Shadow registers are added for glitch-free PWM output.

• For each timer, up to four external outputs corresponding to match registers with the following capabilities (the number of match outputs for each timer that are actually available on device pins can vary by device): – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
• The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge.
• Up to four match registers can be configured for PWM operation, allowing up to three single edged controlled PWM outputs. (The number of match outputs for each timer that are actually available on device pins can vary by device.)

8.20 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels.

8.20.1 Features

• 31-bit interrupt timer
• Four channels independently counting down from individually set values
• Bus stall, repeat and one-shot interrupt modes

8.21 Windowed Watc hDog Timer (WWDT)

The watchdog timer resets the controller if software fails to service the watchdog timer periodically within a programmable time window.

8.21.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out period.
• Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.

Product data sheet Rev. 1.7 — 27 February 2018 28 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

• Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4.
• The WatchDog Clock (WDCLK) is generated by the dedicated watchdog oscillator (WDOSC).

8.22 Self-Wake-up Timer (WKT)

The self-wake-up timer is a 32-bit, loadable down counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. When the counter is used as a wake-up timer, this write can occur prior to entering a reduced power mode.

8.22.1 Features

• 32-bit loadable down counter. Counter starts automatically when a count value is loaded. Time-out generates an interrupt/wake up request.
• The WKT resides in a separate, always-on power domain.
• The WKT supports three clock sources: an external clock on the WKTCLKIN pin, the low-power oscillator, and the FRO. The low-power oscillator is located in the always-on power domain, so it can be used as the clock source in deep power-down mode.
• The WKT can be used for waking up the part from any reduced power mode, including deep power-down mode, or for general-purpose timing.

8.23 Analog comparator (ACMP)

The analog comparator with selectable hysteresis can compare voltage levels on external pins and internal voltages. After power-up and after switching the input channels of the comparator, the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. Settling times are given in Table 29. The analog comparator output is a movable function and is assigned to a pin through the switch matrix. The comparator inputs and the voltage reference are enabled through the switch matrix.

Product data sheet Rev. 1.7 — 27 February 2018 29 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.23.1 Features

• Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input hysteresis.
• Two selectable external voltages (VDD or ACMPVREF ); fully configurable on either positive or negative input channel.
• Internal voltage reference from band gap selectable on either positive or negative input channel.
• 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel.
• Voltage ladder source voltage is selectable from an external pin or the main 3.3 V supply voltage rail.
• Voltage ladder can be separately powered down for applications only requiring the comparator function.
• Interrupt output is connected to NVIC.
• Comparator level output is connected to output pin ACMP_O.
• One comparator output is internally collected to the ADC trigger input multiplexer.

8.24 Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12 bit and fast conversion rates of up to 1.2 MSamples/s. Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible trigger sources are the pin triggers, the SCT output SCT_OUT3, the analog comparator output, and the Arm TXEV. Fig 10. Comparator block diagram ACMP_I[5:1] VDD ACMPVREF DACOUT_0 internal voltage reference edge detect sync comparator level ACMP_O, ADC triggercomparator edge NVIC COMPARATOR ANALOG BLOCK COMPARATOR DIGITAL BLOCK aaa-027485

Product data sheet Rev. 1.7 — 27 February 2018 30 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller The ADC includes a hardware threshold compare function with zero-crossing detection. Remark: For best performance, select VREFP and VREFN at the same voltage levels as VDD and VSS. When selecting VREFP and VREFN different from VDD and VSS, ensure that the voltage midpoints are the same: (VREFP-VREFN)/2 + VREFN = VDD/2

8.24.1 Features

• 12-bit successive approximation analog to digital converter.
• 12-bit conversion rate of up to 1.2 MSamples/s.
• Two configurable conversion sequences with independent triggers.
• Optional automatic high/low threshold comparison and zero-crossing detection.
• Power-down mode and low-power operating mode.
• Measurement range VREFN to VREFP (not to exceed VDD voltage level).
• Burst conversion mode for single or multiple inputs.
• Hardware calibration mode.

8.25 Digital-to-Ana log Converter (DAC)

The DAC supports a resolution of 10 bits. Conversions can be triggered by an external pin input or an internal timer. The DAC includes an optional automatic hardware shut-off feature which forces the DAC output voltage to zero while a HIGH level on the external DAC_SHUTOFF pin is detected.

8.25.1 Features

• 10-bit digital-to-analog converter.
• Supports DMA.
• Internal timer or pin external trigger for staged, jitter-free DAC conversion sequencing.
• Automatic hardware shut-off triggered by an external pin.

8.26 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers.

8.26.1 Features

• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
• Bit order reverse and 1’s complement programmable setting for input data and CRC sum.
• Programmable seed number setting.

Product data sheet Rev. 1.7 — 27 February 2018 31 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

• Supports CPU PIO or DMA back-to-back transfer.
• Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle).

8.27 Clocking and power control

8.27.1 Crystal and internal oscillators

The LPC84x include four independent oscillators: 1. The crystal oscillator (SysO sc) operating at frequencies between 1 MHz and 25 MHz. 2. Free Running Oscillator. 3. Watchdog Oscillator 4. Low Power Oscillator Each oscillator, except the low-frequency oscillator, can be used for more than one purpose as required in a particular application. Following reset, the LPC84x operates from the FRO until switched by software allowing the part to run without any external crystal and the bootloader code to operate at a known frequency. See Figure 11 for an overview of the LPC84x clock generation.

8.27.1.1 Free Running Oscillator (FRO)

The FRO oscillator provides the default clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage.

• This oscillator provides a selectable 18 MHz, 24 MHz, and 30 MHz outputs that can be used as a system clock. Also, these outputs can be divided down to 1.125 MHz, 1.5 MHz, 1.875 MHz, 9 MHz, 12 MHz, and 15 MHz for system clock.
• The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C to 70 C.
• By default, the fro_oscout is 24 MHz and is divided by 2 to provide a default system (CPU) clock frequency of 12 MHz.

8.27.1.2 Crystal Oscillator (SysOsc)

The crystal oscillator can be used as the clock source for the CPU, with or without using the PLL. The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.

8.27.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc)

The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process variations is  40%. The WDOsc is a dedicated oscillator for the windowed WWDT.

Product data sheet Rev. 1.7 — 27 February 2018 32 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller The internal low-power 10 kHz ( 40% accuracy) oscillator serves as the clock input to the WKT. This oscillator can be configured to run in all low-power modes.

8.27.2 Clock input

An external clock source can be supplied on the selected CLKIN pin directly to the PLL input. When selecting a clock signal for the CLKIN pin, follow the specifications for digital I/O pins in Table 13 “Static characteristics, supply pins” and Table 19 “Dynamic characteristics: I/O pins[1]”. An 1.8 V external clock source can be supplied on the XTALIN pins to the system oscillator limiting the voltage of this signal (see Section 14.2 “XTAL oscillator”). The maximum frequency for both clock signals is 25 MHz.

8.27.3 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is nominally 100 s.

8.27.4 Clock output

The LPC84x features a clock output function that routes the FRO, the SysOsc, the watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can be connected to any digital pin through the switch matrix.

Product data sheet Rev. 1.7 — 27 February 2018 33 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 11. LPC84x clock generation aaa-026590 sys_osc_clk fro external_clk wd_osc_clk fro_div External clock select EXTCLKSEL[0] Main clock select MAINCLKSEL[1:0] System PLL System PLL settings sys_pll0_clk clk_in (1)11 main_clk_pre_pll sys_pll0_clk “none” “none” Main clock PLL select MAINCLKPLLSEL IOCONCLKDIV(i) SYSAHBCLKDIV SYSAHBCLKCTRL (one bit per destination) (1)11 main_clk main_clk Divider to AHB peripherals, AHB matrix, memories, etc. to CPU fro external_clk wdt_osc_clk fro_div PLL clock select SYSPLLCLKSEL[1:0] (1)11 fro main_clk sys_pll0_clk “none” SCT clock select SCTCLKSEL[1:0] peripheral_clk Divider pin filter(i) SCTCLKDIV SYSAHBCLKCTRL0[SCT] SCT Clock Divider to SCT input 4 CLKOUTDIV CLKOUT Divider fro sys_pll0_clk “none” ADC clock select ADCCLKSEL[1:0] ADCCLKDIV ADC Clock Divider to ADC fro main_clk sys_pll0_clk fro_div CapTouch clock select CAPTCLKSEL[2:0] 000 001 010 011 wdt_osc_clk 100 “none” 111 SYSAHBCLKCTRL1[CAPT] to Cap Touch fro (1) : synchronized multiplexer, see register desriptions for details. main_clk sys_pll0_clk external_clk CLKOUT select CLKOUTSEL[2:0] 000 001 010 011 wdt_osc_clk 100 “none” 111 CLKOUT Range select and bypass SYSOSCCTRL[1:0] Crystal oscillator xtalin xtalout sys_osc_clk

Product data sheet Rev. 1.7 — 27 February 2018 34 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 12. LPC84x clock generation (continued) aaa-026591 fro main_clk sys_pll0_clk “none” FRG0 clock select FRG0CLKSEL[1:0] FRG1 clock select FRG1CLKSEL[1:0] FRG0DIV, FRG0MULT FRG1DIV, FRG1MULT fro 00 Fractional Rate Divider 0 (FRG0) Fractional Rate Divider 1 (FRG1) fro main_clk frg0clk frg1clk SPln clock select SPInCLKSEL[2:0] 000 001 010 011 fro_div 100 “none” 111 SYSAHBCLKCTRL0[SPln] One for each SPI (SPI0 through SPI1) to SPIn fro main_clk frg0clk frg1clk I2Cn clock select I2CnCLKSEL[2:0] 000 001 010 011 fro_div 100 “none” 111 SYSAHBCLKCTRL0[I2Cn] One for each l2C (I2C0 through I2C3) to I2Cn fro main_clk frg0clk frg1clk UARTn clock select UARTnCLKSEL[2:0] 000 001 010 011 fro_div 100 “none” 111 SYSAHBCLKCTRL0[UARTn] One for each UART (UART0 through UART4) to UARTn watchdog oscillator WWDT FRO oscillator WKT main_clk sys_pll0_clk “none”

8.27.5 Power control

Table 6. Clocking diagram si gnal name descriptions sys_osc_clk This is the internal clock that comes from external crystal oscillator through dedicated pins. “LPC84x clock generation (continued)”. fro The output of the currently selected on-chip FRO oscillator. See UM11029 User manual. fro_div The FRO output. This may be either 15 MH , 12 MHz, or 9 MHz. See UM11029 User manual. the PDRINCFG0 register. See UM11029 User manual. xtalin Input of the main oscillator. If used, this is connected to an external crystal and load capacitor. xtalout Output of the main oscillator. If used, this is connected to an external crystal and load capacitor. selecting it in the IOCON block. external_clk This is the internal clock that comes from the external crystal oscillator or the CLK_IN pin.

Product data sheet Rev. 1.7 — 27 February 2018 36 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.27.5.1 Sleep mode

When sleep mode is entered, the clock to the core is stopped. Resumption from the sleep mode does not need any special sequence but re-enabling the clock to the Arm core. In sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

8.27.5.2 Deep-sleep mode

In deep-sleep mode, the LPC84x core is in sleep mode and all peripheral clocks and all clock sources are off except for the FRO and watchdog oscillator or low-power oscillator if selected. The FRO output is disabled. In addition, all analog blocks are shut down and the flash is in standby mode. In deep-sleep mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC84x can wake up from deep-sleep mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from Capacitive Touch, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C blocks (in slave mode). Any interrupt used for waking up from deep-sleep mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Deep-sleep mode saves power and allows for short wake-up times.

8.27.5.3 Power-down mode

In power-down mode, the LPC84x is in sleep mode and all peripheral clocks and all clock sources are off except for watchdog oscillator or low-power oscillator if selected. In addition, all analog blocks and the flash are shut down. In power-down mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC84x can wake up from power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from Capacitive Touch, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C blocks (in slave mode). Any interrupt used for waking up from power-down mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times.

8.27.5.4 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin and the self-wake-up timer. The LPC84x can wake up from deep power-down mode via the WAKEUP pin, RESET pin, or without an external signal by using the time-out of the self-wake-up timer (see Section 8.22).

the watchdog timer or the BOD running at all times. before entering deep power-down mode. Table 7. Peripheral configuration in reduced power modes

8.27.6 Wake-up process

stabilize before they are used as a clock source. Table 8. Wake-up sources for reduced power modes Sleep Any interrupt Enable interrupt in NVIC. RESET pin PIO0_5 Enable the reset function in the PINENABLE0 register via switch matrix. Pin interrupts Enable pin interrupts in NVIC and STARTERP0 registers. BOD interrupt • Enable interrupt in NVIC and STARTERP1 registers.

• Enable interrupt in BODCTRL register.
• BOD powered in PDSLEEPCFG register. BOD reset • Enable reset in BODCTRL register.
• BOD powered in PDSLEEPCFG register. WWDT interrupt • Enable interrupt in NVIC and STARTERP1 registers.
• WWDT running. Enable WWDT in WWDT MOD register and feed.
• Enable interrupt in WWDT MOD register.
• WDOsc powered in PDSLEEPCFG register. WWDT reset • WWDT running.
• Enable reset in WWDT MOD register.
• WDOsc powered in PDSLEEPCFG register. Self-Wake-up Timer (WKT) time-out
• Enable interrupt in NVIC and STARTERP1 registers.
• Enable low-power oscillator in the DPDCTRL register in the PCON block.
• Select low-power clock for WKT clock in the WKT CTRL register.
• Start the WKT by writing a time-out value to the WKT COUNT register. Interrupt from USART/SPI/I2C peripheral
• Enable interrupt in NVIC and STARTERP1 registers.
• Enable USART/I2C/SPI interrupts.
• Provide an external clock signal to the peripheral.
• Configure the USART in synchronous slave mode and I2C and SPI in slave mode. RESET pin PIO0_5 Enable the reset function in the PINENABLE0 register via switch matrix. Interrupt from Capacitive Touch peripheral
• Enable interrupt in NVIC and STARTERP1 registers.
• Enable the Capacitive Touch interrupt.
• Switch FCLK clock source to the WDOsc.
• Set Capacitive Touch registers.
• Provide a touch event to the peripheral. Deep power-down WAKEUP pin PIO0_4 Enable the WAKEUP function in the DPDCTRL register in the PMU. RESET pin PIO0_5 Enable the reset function in th e DPDCTRL register in the PMU to allow wake-up in deep power-down mode. WKT time-out • Enable the low-power oscillator in the DPDCTRL register in the PMU.
• Enable the low-power oscillator to keep running in deep power-down mode in the DPDCTRL register in the PMU.
• Select low-power clock for WKT clock in the WKT CTRL register.
• Start WKT by writing a time-out value to the WKT COUNT register.

Product data sheet Rev. 1.7 — 27 February 2018 39 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.28 System control

8.28.1 Reset

Reset has four sources on the LPC84x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the FRO and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. In deep power-down mode, an external pull-up resistor is required on the RESET pin.

8.28.2 Brownout detection

The LPC84x includes up to four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Four threshold levels can be selected to cause a forced reset of the chip. Fig 14. Reset pad configuration 966 UHVHW DDD 9'' 9'' 9'' 5SX (6' (6' QV5& */,7&+),/7(5 3,1

Product data sheet Rev. 1.7 — 27 February 2018 40 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.28.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For details, see the LPC84x user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using the ISP entry pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can be disabled. For details, see the LPC84x user manual.

8.28.4 APB interface

The APB peripherals are located on one APB bus.

8.28.5 AHBLite

The AHBLite connects the CPU bus of the Arm Cortex-M0+ to the flash memory, the main static RAM, the CRC, the DMA, the ROM, and the APB peripherals. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.

Product data sheet Rev. 1.7 — 27 February 2018 41 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

8.29 Emulation and debugging

Debug functions are integrated into the Arm Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The Arm Cortex-M0+ is configured to support up to four breakpoints and two watch points. The Micro Trace Buffer is implemented on the LPC84x. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the Arm SWD debug (RESET = HIGH). The Arm SWD debug port is disabled while the LPC84x is in reset. The JTAG boundary scan pins are selected by hardware when the part is in boundary scan mode (see Table 4). To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes.

Table 9. Limiting values

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_10 and PIO0_11 and except the 3 V tolerant pin PIO0_6. [4] Including the voltage on outputs in 3-state mode. [5] V DD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [6] V DD present or not present. ADC inputs for a long time affects the reliability of the device and reduces its lifetime. VDD without affecting the hysteresis range of the comparator function. [9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] Dependent on package type. [11] Human body model: equivalent to dischar ging a 100 pF capacitor through a 1.5 k series resistor. [13] Single layer (4.5 in  3 in); still air. Table 9. Limiting values …continued

• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications.

Table 10. Thermal resistance

11.1 General operating conditions

[1] Typical ratings are not guaranteed. The va lues listed are for room temperature (25 C), nominal supply voltages. [2] Including bonding pad capacitance. Bas ed on simulation, not tested in production. mentioned above can be used. Table 11. General operating conditions Tamb = 40 C to +105 C, unless otherwise specified.

11.2 Power-up ramp conditions

[2] V DD to stay above V1 for the entire duration twd. [3] V DD to stay below V2 for the minimum duration of twd. Table 12. Power-up characteristics [1] t1: The time when there is no restriction on the ramp rate.

11.3 Power consumption

• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIO DIR register.
• Write 1 to the GPIO CLR register to drive the outputs LOW. [1] Typical ratings are not guaranteed. The va lues listed are for room temperature (25 C), VDD = 3.3 V. [2] Characterized through bench m easurements using typical samples.

Table 13. Static charac teristics, supply pins Tamb = 40 C to +105 C, unless otherwise specified.

Product data sheet Rev. 1.7 — 27 February 2018 48 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller [3] I DD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [4] FRO enabled; system oscillator disabled; system PLL disabled. [5] BOD disabled. [6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks disabled in system configuration block. [7] All oscillators and analog blocks turned off. [8] WAKEUP pin pulled HIGH externally. [9] Tested in production, VDD = 3.6 V. Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 16. Deep-sleep mode: Typical supply current I DD versus temperature for different supply voltages VDD DDD WHPSHUDWXUH '''','' 999 999 999 999 999

Product data sheet Rev. 1.7 — 27 February 2018 49 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 17. Power-down mode: Typical supply current I DD versus temperature for different supply voltages VDD WKT not running. Fig 18. Deep power-down mode: Typical supply current I DD versus temperature for different supply voltages VDD DDD WHPSHUDWXUH '''','' 999 999 999 DDD WHPSHUDWXUH ,'''','' 999 999 999 999

Product data sheet Rev. 1.7 — 27 February 2018 50 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller WKT running with internal 10 kHz low-power oscillator. Fig 19. Deep power-down mode: Typical supply current I DD versus temperature for different supply voltages VDD (internal clock) WKT running with external 10 kHz clock. Clock input waveform: square wave with rise time and fall time of 5 ns. Fig 20. Deep power-down mode: Typical supply current I DD versus temperature for different supply voltages VDD (external 10 kHz input clock) DDD WHPSHUDWXUH ,'''','' 999 999 999 999 DDD WHPSHUDWXUH '''','' 999 999 999 999

Product data sheet Rev. 1.7 — 27 February 2018 51 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller WKT running with external 32 kHz clock. Clock input waveform: square wave with rise time and fall time of 5 ns. Fig 21. Deep power-down mode: Typical supply current I DD versus temperature for different supply voltages VDD (external 32 kHz input clock) DDD WHPSHUDWXUH '''','' 999 999 999 999

11.4 Peripheral power consumption

The supply currents are shown for FRO clock frequencies of 12 MHz and 30 MHz. Table 14. Power consumption for indi vidual analog and digital blocks 24 MHz. FRO output disabled. BOD 42 - - Independent of main clock frequency. register. Not connected to pin.

ADC disabled in the PDRUNCFG register. register (ADC in low-power mode).

11.5 Pin characteristics

Table 15. Static characterist ics, pin characteristics Tamb = 40 C to +105 C, unless otherwise specified.

Table 15. Static characterist ics, pin characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified.

[1] Typical ratings are not guaranteed. The va lues listed are for room temperature (25 C), nominal supply voltages. [2] Based on characterization. Not tested in production. [3] Including voltage on outputs in 3-state mode. [4] 3-state outputs go into 3-state mode in deep power-down mode. [5] Allowed as long as the current limit does not exceed the maximum current allowed by the device. Tamb = 40 C to +105 C, unless otherwise specified.

Product data sheet Rev. 1.7 — 27 February 2018 57 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

11.5.1 Electrical pin characteristics

Conditions: VDD = 1.8 V; on pin PIO0_12. Conditions: V DD = 3.3 V; on pin PIO0_12. Fig 23. High-drive output: Typical HIGH-level output voltage V OH versus HIGH-level output current IOH DDD 92+2+92+ &&& &&& &&& DDD 92+2+92+ &&& &&& &&& Conditions: VDD = 1.8 V; on pins PIO0_10 and PIO0_11. Conditions: V DD = 3.3 V; on pins PIO0_10 and PIO0_11. Fig 24. I 2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL DDD ,2/2/,2/ &&& &&& &&& DDD ,2/2/,2/ &&& &&& &&&

Product data sheet Rev. 1.7 — 27 February 2018 58 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Conditions: VDD = 1.8 V; standard port pins and high-drive pin PIO0_12. Conditions: VDD = 3.3 V; standard port pins and high-drive pin PIO0_12. Fig 25. Typical LOW-level output current I OL versus LOW-level output voltage VOL DDD ,2/2/,2/ &&& &&& &&& DDD ,2/2/,2/ &&& &&& &&& Conditions: VDD = 1.8 V; standard port pins. Conditions: V DD = 3.3 V; standard port pins. Fig 26. Typical HIGH-level output voltage V OH versus HIGH-level output source current IOH DDD 92+2+92+ &&& &&& &&& DDD 92+2+92+ &&& &&& &&&

Product data sheet Rev. 1.7 — 27 February 2018 59 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Conditions: VDD = 1.8 V; standard port pins. Conditions: V DD = 3.3 V; standard port pins. Fig 27. Typical pull-up current I PU versus input voltage VI DDD ,SXSX,SX &&& &&& &&& DDD ,SXSX,SX &&& &&& &&& Conditions: VDD = 1.8 V; standard port pins. Conditions: V DD = 3.3 V; standard port pins. Fig 28. Typical pull-down current I PD versus input voltage VI DDD ,SGSG,SG &&& &&& &&& DDD ,SGSG,SG &&& &&& &&&

12.1 Flash memory

[1] Number of program/erase cycles. calls (see LPC84x user manual).

12.2 FRO

Table 16. Flash characteristics Table 17. Dynamic characteristic: FRO

[1] Typical ratings are not guaranteed. The va lues listed are at nominal supply voltages. [2] The typical frequency spread over processing and temperature (T amb = 40 C to +105 C) is 40 %. [3] See the LPC84x user manual.

12.3 I/O pins

[1] Applies to standard port pins and RESET pin.

12.4 WKTCLKIN pin (w ake-up clock input)

[1] Assuming a square-wave input clock.

12.5 SCTimer/PWM output timing

Table 18. Dynamic characterist ics: Watchdog oscillator Table 19. Dynamic characteristics: I/O pins [1] Table 20. Dynamic characte ristics: WKTCLKIN pin Table 21. SCTimer/PWM output dynamic characteristics level of the falling or rising edge; values guaranteed by design.

12.6 I 2C-bus

[1] See the I 2C-bus specification UM10204 for details. [2] Parameters are valid over operating temp erature range unless otherwise specified. VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] C b = total capacitance of one bus line in pF. SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. are used, designers should allow for this when considering bus timing. Table 22. Dynamic characteristic: I 2C-bus pins[1]

01 M H z

Product data sheet Rev. 1.7 — 27 February 2018 63 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller [8] The maximum t HD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] t SU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Fig 29. I 2C-bus pins clock timing DDD WI 6'$ WI W+' '$7 6&/ I6&/ W9' '$7 W+,*+ W/2: W68 '$7

12.7 SPI interfaces

all digital pins except the open-drain pins PIO0_10 and PIO0_11. Table 23. SPI dynamic characteristics external trace or external device are not considered.

Product data sheet Rev. 1.7 — 27 February 2018 65 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Tcy(clk) = CCLK/DIVVAL with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC84x User manual. Fig 30. SPI master timing SCK (CPOL = 0) MOSI (CPHA = 1) SSEL MISO (CPHA = 1) Tcy(clk) tDS tDH tv(Q) DATA VALID (LSB) DATA VALID tv(Q) SCK (CPOL = 1) DATA VALID (LSB) DATA VALID MOSI (CPHA = 0) MISO (CPHA = 0) tDS tDH DATA VALID (MSB) DATA VALID (MSB)DATA VALID DATA VALID (LSB) DATA VALID (LSB) tv(Q) DATA VALID (MSB) DATA VALID tv(Q) aaa-014969 DATA VALID (MSB) DATA VALID (MSB) DATA VALID (MSB) DATA VALID (MSB) IDLE IDLE IDLE IDLE DATA VALID (MSB)

Product data sheet Rev. 1.7 — 27 February 2018 66 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 31. SPI slave timing SCK (CPOL = 0) MISO (CPHA = 1) SSEL MOSI (CPHA = 1) Tcy(clk) tDS tDH tv(Q) DATA VALID (LSB) DATA VALID tv(Q) SCK (CPOL = 1) DATA VALID (LSB) DATA VALID MISO (CPHA = 0) MOSI (CPHA = 0) tDS tDH DATA VALID (MSB) DATA VALID (MSB)DATA VALID DATA VALID (LSB) DATA VALID (LSB) tv(Q) DATA VALID (MSB) DATA VALID tv(Q) aaa-014970 DATA VALID (MSB) DATA VALID (MSB) DATA VALID (MSB) DATA VALID (MSB) IDLE IDLE IDLE IDLE DATA VALID (MSB)

12.8 USART interface

slave synchronous mode is 10 Mbit/s. for all digital pins except the open-drain pins PIO0_10 and PIO0_11. Table 24. USART dynamic characteristics

12.9 Wake-up process

wake-up handler. ISR is located in SRAM. [3] FRO enabled, all peripherals off. PLL disabled. device up and when a GPIO output pin is set in the reset handler. Table 25. Dynamic characteristic: Typica l wake-up times from low power modes VDD = 3.3 V;Tamb =2 5 C; using FRO (12MHz) as the system clock. WKT disabled; using RESET pin.

1. Characteristics of analog peripherals

13.1 BOD

LPC84x user manual. Interrupt level 0 is reserved. Table 26. BOD static characteristics [1]

13.2 ADC

[1] The input resistance of ADC channel 0 is higher than for all other channels. See Figure 33. [2] In the ADC TRM register, set VRANGE = 0 (default). [3] In the ADC TRM register, set VRANGE = 1. [4] Based on characterization. Not tested in production. D) is the difference between the actual step width and the ideal step width. See Figure 34. appropriate adjustment of gain and offset errors. See Figure 34. offset error, and the straight line which fits the ideal transfer curve. See Figure 34. [9] T amb = 25 C; maximum sampling frequency fs = 1.2 Msamples/s and analog input capacitance Cia = 26 pF. capacity including Cia and Cio: Zi  1 / (fs  Ci). See Table 13 for Cio. Table 27. 12-bit ADC static characteristics Tamb = 40 C to +105 C unless noted otherwise; VDD = VDDA = 2.4 V to 3.6 V; VREFP = VDD = VDDA; VREFN = VSS.

Product data sheet Rev. 1.7 — 27 February 2018 71 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 33. 12-bit ADC characteristics aaa-016908 4095 4094 4093 4092 4091 (2) (1) 40964090 4091 4092 4093 4094 40957123456 4090 (5) (4) (3)

1 LSB

(ideal) code out VREFP - VREFN 4096 offset error EO gain error EG offset error EO VIA (LSBideal)

1 LSB =

Product data sheet Rev. 1.7 — 27 February 2018 72 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

13.2.1 ADC input impedance

Figure 34 shows the ADC input impedance. In this figure:

• ADCx represents ADC input channel 0.
• ADCy represents ADC input channels 1 to 11.
• R1 and Rsw are the switch-on resistance on the ADC input channel.
• If ADC input channel 0 is selected, the ADC input signal goes through R1 + Rsw to the sampling capacitor (Cia).
• If ADC input channels 1 to 11 are selected, the ADC input signal goes through Rsw to the sampling capacitor (Cia).
• Typical values, R1 = 2.5 k, Rsw = 25 
• See Table 11 for Cio.
• See Table 27 for Cia. Fig 34. ADC input impedance DAC ADC Rsw Cia ADCx ADCy Cio Cio aaa-017600

13.3 Comparator and internal voltage reference

Table 28. Internal voltage reference static and dynamic characteristics Tamb = 40 C to +105 C; VDD = 3.3 V; hysteresis disabled in the comparator CTRL register. VDD = 3.3 V; characterized through bench measurements on typical samples. Table 29. Comparator characteristics Tamb = 40 C to +105 C unless noted otherwise; VDD = 1.8 V to 3.6 V.

[2] Characterized on typical samp les, not tested in production. [3] Input hysteresis is relative to the referenc e input channel and is software programmable. [4] 100 mV overdrive corresponds to a square wave from 50 mV below the reference (V IC) to 50 mV above the reference. [1] Characterized on typical samples, not tested in production. Table 29. Comparator characteristics …continued Tamb = 40 C to +105 C unless noted otherwise; VDD = 1.8 V to 3.6 V. Table 30. Comparator voltage ladder dynamic characteristics

[1] Characterized though limited samples. Not tested in production. [2] All peripherals except comparator, temperature sensor, and FRO turned off.

13.4 DAC

[2] Characterized through bench measurements, not tested in production. [3] DAC output voltage depends on the voltage divider ratio of the R OUT and external load resistance. Table 31. Comparator voltage ladder reference static characteristics VDD = 1.8 V to 3.6 V. Tamb = -40 C to + 105C; external or internal reference. Table 32. 10-bit DAC electr ical characteristics

14.1 Start-up behavior

Table 33. Typical start-up timing parameters

Product data sheet Rev. 1.7 — 27 February 2018 77 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

14.2 XTAL oscillator

In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2 need to be connected externally on XTALIN and XTALOUT. See Figure 37. For best results, it is very critical to select a matching crystal for the on-chip oscillator. Load capacitance (CL), series resistance (RS), and drive level (DL) are important parameters to consider while choosing the crystal. After selecting the proper crystal, the external load capacitor CX1 and CX2 values can also be generally determined by the following expression: CX1 = CX2 = 2CL  (CPad + CParasitic) Where: CL - Crystal load capacitance CPad - Pad capacitance of the XTALIN and XTALOUT pins (~3 pF). CParasitic – Parasitic or stray capacitance of external circuit. Although CParasitic can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. Therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency. For fine tuning, measure the clock on the XTALOUT pin and optimize the values of external load capacitors for minimum frequency deviation. Fig 37. XTAL oscillator components aaa-025725 LPCxxxx XTALIN XTALOUT CX2CX1 XTAL = CL CP RS L

Product data sheet Rev. 1.7 — 27 February 2018 78 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller

14.2.1 XTAL Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of the chip.
• The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines.
• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal usage, have a common ground plane.
• Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the parasitics as small as possible.
• Lay out the ground (GND) pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.

14.2.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.95 V. If the oscillator is driven by a clock in slave mode, it is recommended to couple the input through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. In slave mode the input clock signal should be coupled with a capacitor of 100 pF (Figure 38), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected.

14.3 Connecting power, clo cks, and debug functions

Figure 39 shows the basic board connections used to power the LPC84x, connect the external crystal, and provide debug capabilities via the serial wire port. Fig 38. Slave mode operation of the on-chip oscillator /3& ;7$/,1 DDD

Product data sheet Rev. 1.7 — 27 February 2018 79 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller (1) See Section 14.2 “XTAL oscillator” for the values of C1 and C2. (2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the VDD pin. Add one set of decoupling capacitors to each VDD pin. (3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and VDD pins. The 10 μF bypass capacitor filters the power line. Tie VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used. (4) Uses the Arm 10-pin interface for SWD. (5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see Ref. 4. (6) External pull-up resistors on SWDIO and SWCLK pins are opt ional because these pins have an internal pull-up enabled by default. Fig 39. Power, clock, and debug connections PIO0_12 ADC_0 PIO0_8/XTALIN PIO0_9/XTALOUT VDD VREFP PIO0_6/ADC_1/ACMPVREF VREFN LPC84x 3.3 V DGND Note 5 Note 5 (ADC_1), Note 3 (ACMPVREF) Note 1 DGND DGND Note 2 Note 3 0.01 μF0.1 μF 3.3 V AGNDAGND AGND 10 μF0.1 μF0.1 μF ISP select pin aaa-026592 SWDIO/PIO0_2 SWCLK/PIO0_3 RESETN/PIO0_5 VSS 3.3 V DGND DGND n.c. n.c. n.c. SWD connector (6) (4) (6) 3.3 V ~10 kΩ - 100 kΩ ~10 kΩ - 100 kΩ 3.3 V

14.4 I/O power consumption

I/O pins are contributing to the overall dynamic and static power consumption of the part. external loads connected to the pin. external capacitive loads connected to the pin in addition to powering the I/O circuitry.

14.5 Termination of unused pins

minimize the overall power consumption of the part. to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register. smaller packages as outputs driven LOW with their internal pull-up disabled. [1] I = Input, O = Output, IA = Inactive (no pull- up/pull-down enabled), F = floating, PU = Pull-Up. Table 34. Termination of unused pins

• Deep power-down used: Connect an external pull-up resistor and keep pin in default state (input, pull-up enabled) during all other power modes.
• Deep power-down not used and no external pull-up connected: can be left unconnected if internal pull-up is disabled and pin is driven LOW and configured as output by software. all PIOn_m (not open-drain) I; PU Can be left unconnected if driven LOW and configured as GPIO output with pull-up disabled by software. PIOn_m (I2C open-drain) IA Can be left unconnected if driven LOW and configured as GPIO output by software. VREFP - Tie to VDD. VREFN - Tie to VSS.

14.6 Pin states in di fferent power modes

[1] Default and programmed pin states are retained in sleep, deep-sleep, and power-down modes. Table 35. Pin states in different power modes As configured in the IOCON[1]. Floating.

Product data sheet Rev. 1.7 — 27 February 2018 82 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller 15. Package outline Fig 40. Package outline SOT313-2 (LQFP48) UNIT A max. A1 A2 A3 bp cE (1) eH E LL p Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 o o0.12 0.10.21 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT313-2 MS-026 136E05 00-01-19 03-02-25 D(1) (1)(1) 7.1 6.9 HD 9.15 8.85 EZ 0.95 0.55 D bp e E B DH bp EH v M B D ZD A ZE e v M A 36 25 θ A Lp detail X L (A )3 X y c w M w M 0 2.5 5 mm scale pin 1 index LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Product data sheet Rev. 1.7 — 27 February 2018 83 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 41. Package outline SOT314-2 (LQFP64) UNIT A max. A1 A2 A3 bp cE (1) eH E LL p Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 o o0.12 0.11 0.2 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT314-2 MS-026 136E10 00-01-19 03-02-25 D(1) (1)(1) 10.1 9.9 HD 12.15 11.85 EZ 1.45 1.05 D bp e θ E A Lp detail X L (A )3 B c DH bp EH A2 v M B D ZD A ZE e v M A X 48 33 y pin 1 index w M w M 0 2.5 5 mm scale LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2

Product data sheet Rev. 1.7 — 27 February 2018 84 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 42. Package outline HVQFN33 (5 x 5 x 0.85 mm) ReferencesOutline version European projection Issue date IEC JEDEC JEITA MO-220 hvqfn33f_po 11-10-11 11-10-17 Unit(1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm bc 0.30 0.18 D(1)A(1) Dh E(1) Eh ee 1 e2 L 3.5 vw 0.1 0.1 y 0.05 0.5 0.3 0.05 0 2.5 5 mm scale 1/2 e AC Bv Cw terminal 1 index area A c detail X yy1 Ce L Eh Dh e b 91 6 32 25 178 X D E C B A terminal 1 index area 1/2 e

Product data sheet Rev. 1.7 — 27 February 2018 85 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 43. Package outline HVQFN48 7 x 7x 0.85 mm (SOT619-1) ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT619-1 MO-220 sot619-1_po 02-10-18 12-11-22 Unit(1) mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 5.25 5.10 4.95 5.25 5.10 4.95 7.1 7.0 6.9 0.5 0.4 0.3 0.5 5.5 0.1 A Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm SOT619-1 A1 b 0.30 0.21 0.18 CD D h EE h ee 1 e2 5.5 Lv 0.1 w 0.05 y 0.05 0 2.5 5 mm scale A A1 c detail X L Eh Dh b 13 24 48 37 2512 D E terminal 1 index area terminal 1 index area 1/2 e AC Bv wC B C A y 1/2 e Cy1e X e

Product data sheet Rev. 1.7 — 27 February 2018 86 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller 16. Soldering Fig 44. Reflow soldering for the LQFP48 package SOT313-2 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP48 package Ax Bx Gx GyHy Hx AyBy D2 (8×) D1 (0.125) Ax Ay Bx By D1 D2 Gx Gy Hx Hy 10.350 0.560 10.350 7.350 7.350 0.500 0.280 C solder land C Generic footprint pattern Refer to the package outline drawing for actual layout

Product data sheet Rev. 1.7 — 27 February 2018 87 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 45. Reflow soldering for the LQFP64 package SOT314-2 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP64 package Ax Bx Gx GyHy Hx AyBy P1P2 D2 (8×) D1 (0.125) Ax Ay Bx By D1 D2 Gx Gy Hx Hy 13.300 13.300 10.300 10.300 0.500 0.560 0.280 C solder land C Generic footprint pattern Refer to the package outline drawing for actual layout

Product data sheet Rev. 1.7 — 27 February 2018 88 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 46. Reflow soldering of the HVQFN48 package (7x7) 1 of 3

Product data sheet Rev. 1.7 — 27 February 2018 89 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 47. Reflow soldering of the HVQFN48 package (7x7) 2 of 3

Product data sheet Rev. 1.7 — 27 February 2018 90 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 48. Reflow soldering of the HVQFN48 package (7x7) 3 of 3

Product data sheet Rev. 1.7 — 27 February 2018 91 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Fig 49. Reflow soldering of the HVQFN48 package (7x7) SOT619-1Footprint information for reflow soldering of HVQFN48 package Dimensions in mm Ax Ay Bx By D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hx Hy 8.000 8.000 6.200 6.200 P 0.500 0.290 C nSPx nSPy sot619-1_fr occupied area Ax Bx SLx Gx GyHy Hx AyBySLy P 0.025 0.025D (0.105) SPx tot SPy t o t nSPx nSPy SPx SPy solder land plus solder paste solder land solder paste deposit C Generic footprint pattern Refer to the package outline drawing for actual layout Issue date 07-05-07 09-06-15

[3] I2C-bus specification UM10204. Table 36. Abbreviations

Table 37. Revision history

• Updated reflow soldering of the HVQFN48 package to add three figures: Figure 46 “Reflow soldering of the HVQFN48 package (7x7) 1 of 3”, Figure 47 “Reflow soldering of the HVQFN48 package (7x7) 2 of 3” and Figure 48 “Reflow soldering of the HVQFN48 package (7x7) 3 of 3”. LPC84X v.1.5 20171214 Product data sheet - LPC84X v.1.4 Modifications:
• Updated Table 25 “Dynamic characteristic: Typical wake-up times from low power modes”.
• Removed remark from Section 8.17 “Capacitive Touch Interface”: Remark: Evaluation kits and software packages for Capacitive Touch will be available in late Q3-2017. LPC84X v.1.4 20171128 Product data sheet - LPC84X v.1.3 Modifications:
• Updated Table 17 “Dynamic characteristic: FRO”. Added conditions20 C  Tamb  70 C and 40 C  Tamb  105 C.
• Updated Figure 8 “LPC84x AHB Memory mapping”.
• Updated table notes: Table 15 “Static characteristics, pin characteristics”.
• Updated Table 14 “Power consumption for individual analog and digital blocks”: FRO Typical supply current in μA is 89. LPC84X v.1.3 20170809 Product data sheet - LPC84X v.1.2 Modifications:
• Updated Table 9 “Limiting values”: Added max values for supply and ground pins for LQFP48, HVQFN48, and HVQFN33 packages.
• Updated Table 1 “Ordering information”: Description of part number LPC844M201JHI48 and package name, HVQFN48. LPC84X v.1.2 20170801 Product data sheet - LPC84X v.1.1 Modifications:
• Updated Table 7 “Peripheral configuration in reduced power modes” and Table 8 “Wake-up sources for reduced power modes”: Cap Touch interrupt can wake up from power down mode.
• Updated Table 2 “Ordering options”. LPC845M301JHI33 does not have Capacitive Touch. LPC84X v.1.1 20170623 Product data sheet - LPC84X v.1 Modifications:
• Updated Table 27 “12-bit ADC static characteristics”.
• Added a remark to Section 8.17 “Capacitive Touch Interface”: Evaluation kits and software packages for Capacitive Touch will be available in late Q3-2017. LPC84X v.1 20170619 Product data sheet - -

Product data sheet Rev. 1.7 — 27 February 2018 94 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller 20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

20.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

20.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This docu ment contains the product specification.

Product data sheet Rev. 1.7 — 27 February 2018 95 of 97 NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 1.7 — 27 February 2018 96 of 97 continued >> NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller 22. Contents 8.7 Nested Vectored Interrupt Controller (NVIC) . 19 8.11 Fast General-Purpose parallel I/O (GPIO) . . . 21 8.16 I

8.19.1 General-purpose 32- bit timers/external event

8.27.1.3 Internal Low-power Oscillator and Watchdog

8.28.3 Code security (Code Read Protection - CRP) 40

32-bit Arm Cortex-M0+ microcontroller © NXP Semiconductors N.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 February 2018 Document identifier: LPC84x Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 13.3 Comparator and internal voltage reference . . 73

14.2.1 XTAL Printed Circuit Board (PCB) design

14.3 Connecting power, clocks, and debug