LP8900TLE-AAEC/NOPB

LP8900 TI1 | Alldatasheet

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Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP8900 SNVS542E –MAY 2008–REVISED JUNE 2016 LP8900200-mAUltra-Low-NoiseDualLDO ForRFandAnalogCircuits

1 Features

1• Input Voltage Operation: 1.8 V to 5.5 V

• Output Voltage: 1.2 V to 3.6 V
• Accuracy Over Temperature: 1%
• Output Voltage Noise: 6 µVRMS
• PSRR: 75 dB at 1 kHz
• Dropout: 110 mV at 200 mA Load
• Quiescent Current: 48 µA per Regulator
• Start-Up Time: 80 µs
• Stable With Ceramic Capacitors as Small as 0402
• Thermal-Overload and Short-Circuit Protection

2 Applications

• Battery-Operated Devices
• Hand-Held Information Appliances
• Noise Sensitive RF Applications
• DC-DC Convertor Post Regulation and Filter

3 Description

The LP8900 is a dual LDO capable of supplying 200- mA output current per regulator. Designed to meet the requirements of RF and analog circuits, the LP8900 provides low device noise, high PSRR, low quiescent current, and superior line transient response figures. Using new innovative design techniques, the LP8900 offers class-leading device noise performance without a noise bypass capacitor. The LP8900 is designed to be stable with space saving ceramic capacitors as small as 0402 case size, enabling a solution size < 4 mm2. Performance is specified for a –40°C to +125°C junction temperature range. Output voltage options from 1.2 V to 3.6 V are available; for availability, contact your local TI sales office. Device Information(1) PART NUMBER PACKAGE BODY SIZE (MAX) LP8900 DSBGA (6) 1.49 mm × 1.09 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space space space space Typical Application Circuit

SNVS542E –MAY 2008–REVISED JUNE 2016 www.ti.com Product Folder Links: LP8900 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Table of Contents

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (August 2015) to Revision E Page Changes from Revision C (July 2013) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section; add updated Thermal Information values; delete lead

www.ti.com SNVS542E –MAY 2008–REVISED JUNE 2016 Product Folder Links: LP8900 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated

5 Default Device Options

ORDERABLE NUMBER OUT1 OUT2 LP8900TLE-3333 2.8 V 2.8 V LP8900TLE-AAAH 2.7 V 2.7 V LP8900TLE-AAEB 2.8 V 2.7 V LP8900TLE-AAEC 2.8 V 1.2 V

6 Pin Configuration and Functions

Enable input; enables the regulator when ≥ 1.2 V. Enable Input has an internal 3-MΩ pulldown resistor to GND. Disables the regulator when ≤ 0.4 V. A2 OUT1 O Voltage output. A low ESR ceramic capacitor must be connected from this pin to GND. (See Application and Implementation.) Connect this output to the load circuit. B1 GND G Common ground. B2 IN I Voltage supply input. A 1-µF capacitor must be connected from this pin to GND. C1 EN2 I Enable input; enables the regulator when ≥ 1.2 V. Enable input has an internal 3-MΩ pulldown resistor to GND. Disables the regulator when ≤ 0.4 V. C2 OUT2 O Voltage output. A low ESR ceramic capacitor must be connected from this pin to GND. (See Application and Implementation.) Connect this output to the load circuit.

SNVS542E –MAY 2008–REVISED JUNE 2016 www.ti.com Product Folder Links: LP8900 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the potential at the GND pin. (3) Internal thermal shutdown circuitry protects the device from permanent damage.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT IN, OUT pins: Voltage to GND –0.3 6.5 V EN pin: Voltage to GND –0.3 to (VIN + 0.3V) 6.5 °C Continuous power dissipation(3) Internally limited Junction temperature 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±200 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The maximum ambient temperature (TA(MAX)) is dependant on the maximum operating junction temperature (TJ(MAX-OP) = 125°C), the maximum power dissipation of the device in the application (PD(MAX)), and the junction to ambient thermal resistance of the part / package in the application (RθJA), as given by: TA(MAX) = TJ(MAX-OP) – (RθJA × PD(MAX)).

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT Input voltage 1.8 5.5 V Recommended load current per channel 200 mA Junction temperature, TJ –40 125 °C Ambient temperature, TA (2) –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) LP8900 UNITYZR (DSBGA)

6 PINS

RθJA Junction-to-ambient thermal resistance 140.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 1.0 °C/W RθJB Junction-to-board thermal resistance 26.0 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 26.0 °C/W

www.ti.com SNVS542E –MAY 2008–REVISED JUNE 2016 Product Folder Links: LP8900 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated (1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production at TJ = 25°C or correlated using Statistical Quality Control methods. Operation over the temperature specification is ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) The minimum input voltage = VOUT(NOM) + 0.5 V or 1.8 V, whichever is greater. (3) Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value. This parameter is only specified for output voltages above 1.8 V. (4) The device maintains the regulated output voltage without a load. (5) Short circuit current is measured with VOUT pulled to 0 V. (6) This electrical specification is ensured by design. (7) EN Pin has an internal 3-MΩ typical, resistor connected to GND.

7.5 Electrical Characteristics

Unless otherwise noted, VEN = 1.2 V, VIN = VOUT + 0.5 V, or 1.8 V, whichever is higher (where VOUT is the higher of VOUT1 and VOUT2), CIN = COUT = 1 µF, and IOUT = 1 mA. Typical values apply for TA = 25°C; minimum and maximum values apply over the full junction temperature range for operation, −40 to +125°C, unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage TA = 25°C, see(2) 1.8 5.5 V ΔVOUT Output voltage tolerance VIN = VOUT(NOM) + 0.5 V to 5.5 V ILOAD = 1 mA 1% 1% VIN = 1.8 V to 5.5 V ILOAD = 1 mA, VOUT = 1.2 V –2.25% 2.25% Line regulation error VIN = VOUT(NOM) + 0.5 V to 5.5 V IOUT = 1 mA 0.05 %/V Load regulation error IOUT = 1 mA to 200 mA 4 9 mV VDO Dropout voltage(3) IOUT = 200 mA VOUT = 3.6 V 55 82 mVVOUT = 2.8 V 110 164 VOUT = 1.8 V 185 260 ILOAD Load current TA = 25°C, see(4) 0 mA See(4) 200 IQ Quiescent current VEN1 = 1.2 V, VEN2 = 0 V, IOUT = 0 mA 48 120 µA VEN1 = 1.2 V, VEN2 = 1.2 V, IOUT = 0 mA 85 200 VEN1 = 1.2 V, VEN2 = 1.2 V, IOUT = 200 mA 210 VEN ≤ 0.4 V 0.003 1 ISC Short-circuit current limit VIN = 3.6 V(5) 600 900 mA PSRR Power supply rejection ratio(6) ƒ = 1 kHz, IOUT = 200 mA 75 dB ƒ = 10 kHz, IOUT = 200 mA 65 ƒ = 100 kHz, IOUT = 200 mA 45 ƒ = 1 MHz, IOUT = 200 mA 30 en Output noise voltage(6) BW = 10 Hz to 100 kHz, VIN = 4.2 V, COUT = 1 µF IOUT = 0 mA 6 µVRMSIOUT = 1 mA 10 IOUT = 200 mA 6 TSHUTDOWN Thermal shutdown Temperature 155 Hysteresis 15 ENABLE CONTROL CHARACTERISTICS IEN Maximum input current at EN input(7) VEN = 0 V, VIN = 5.5 V 0.003 µA VEN = VIN = 5.5 V 4 VIL Low input threshold VIN = 1.8 V to 5.5 V 0.4 V VIH High input threshold VIN = 1.8 V to 5.5 V 1.2 V

SNVS542E –MAY 2008–REVISED JUNE 2016 www.ti.com Product Folder Links: LP8900 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise noted, VEN = 1.2 V, VIN = VOUT + 0.5 V, or 1.8 V, whichever is higher (where VOUT is the higher of VOUT1 and VOUT2), CIN = COUT = 1 µF, and IOUT = 1 mA. Typical values apply for TA = 25°C; minimum and maximum values apply over the full junction temperature range for operation, −40 to +125°C, unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TRANSIENT CHARACTERISTICS Line transient response |δVOUT| Trise = Tfall = 30 µs δVIN = 600 mV 1 mV (pk - pk) Transient response Load transient response |δVOUT| Trise = Tfall = 1 µs IOUT = 1 mA to 200 mA 80 mV IOUT = 200 mA to 1 mA 70 Overshoot on start-up 0% 1%

7.6 Timing Requirements

Nominal values apply for TA = 25°C; minimim and maximum values apply over the full junction temperature range for operation, −40 to +125°C, unless otherwise specified. MIN NOM MAX UNIT TON Turnon time to 95% level, VOUT(NOM) 80 200 µs TOFF Turnoff Time, 5% of VOUT(NOM), IOUT = 0 mA 0.4 1 ms

7.7 Typical Characteristics

VOUT(NOM) = 2.85 V, and the EN pin is tied to VIN. Figure 1. Power Supply Rejection Ratio Figure 2. Power Supply Rejection Ratio Figure 3. Noise Density Figure 4. Output Voltage Change vs Temperature Figure 5. Ground Current vs Load Current Figure 6. Ground Current vs Load Current

3M Ÿ 3M Ÿ LP8900 www.ti.com SNVS542E –MAY 2008–REVISED JUNE 2016 Product Folder Links: LP8900 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The LP8900 is a dual linear regulator capable of supplying 200 mA output current per regulator. Designed to meet the requirements of RF and analog circuits, the LP8900 provides low device noise, high PSRR, low quiescent current, and superior line transient response figures. Using new innovative design techniques the LP8900 offers class-leading device noise performance without a noise bypass capacitor. The LP8900 is designed to perform with a single 1-µF input capacitor and a single 1-µF ceramic output capacitor.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Enable Control

The LP8900 may be switched ON or OFF by a logic input at the EN pin. A high voltage at this pin turns the device on. When the enable pin is low, the regulator output is off and the device typically consumes 3 nA. However if the application does not require the shutdown feature, the EN pin can be tied to VIN to keep the regulator permanently on. To ensure fast start-up is achieved, EN must be driven separately. A 3-MΩ pulldown resister ties the EN input to ground, this ensures that the device remains off when the enable pin is left open circuit. To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turnon or turnoff voltage thresholds listed in Electrical Characteristics under VIL and VIH.

SNVS542E –MAY 2008–REVISED JUNE 2016 www.ti.com Product Folder Links: LP8900 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated

8.4 Device Functional Modes

8.4.1 Enable (EN)

The LP8900 EN pin is internally held low by a 3-MΩ resistor to GND. The Enable pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin is pulled low, the output is off and the device typically consumes 3 nA.

8.4.2 Minimum Operating Input Voltage (VIN)

The LP8900 does not include any dedicated UVLO circuitry. The LP8900 internal circuitry is not fully functional until VIN is at least 1.8 V. The output voltage is not regulated until VIN has reached at least the greater of 1.8 V or (VOUT + VDO).

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

performance without a noise bypass capacitor and is stable with input and output capacitors with a value of 1 µF. specified with an operating junction temperature (TJ) of –40°C to +125°C.

9.2 Typical Application

Figure 11. LP8900 Typical Application

9.2.1 Design Requirements

Table 1. Design Parameters +125°C, unless otherwise specified. Table 2. Recommended Capacitor Specifications

9.2.2 Detailed Design Procedure

9.2.2.1 External Capacitors

capacitors must be correctly selected for good performance.

9.2.2.2 Input Capacitor

analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. current rating sufficient for the application. remains ≊ 1 µF over the entire operating temperature range.

9.2.2.3 Output Capacitor

Correct selection of the output capacitor is critical to ensure stable operation in the intended application. results if the capacitance drops below the minimum specified value. (dielectric type X7R or X5R) with an ESR between 5 mΩ to 500 mΩ, is suitable in the LP8900 application circuit.

Other ceramic types such as Y5V and Z5U are less suitable owing to their inferior temperature characteristics. low impedance, ground connection.

9.2.2.4 No-Load Stability

circuits, for example CMOS RAM keep-alive applications.

9.2.2.5 Capacitor Characteristics

design options in terms of low cost and minimal area. poorer performance figures in general. Figure 12. Effect of DC Bias on Capacitance Value the temperature changes significantly above or below 25°C.

–40°C, so some guard band must be allowed.

9.2.3 Application Curves

Figure 13. OUT1 Load Transient Figure 14. OUT1 Load Transient Figure 15. Load Transient Figure 16. Line Transient

Figure 17. Enable Start-Up Characteristics Figure 18. VIN and EN Tied Together Figure 19. Shutdown Characteristics

10 Power Supply Recommendations

supply must be well regulated. A minimum capacitor value of 1 µF is required to be within 1 cm of the IN pin.

11 Layout

11.1 Layout Guidelines

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP8900. LP8900 ground pin using as wide and as short of a copper trace as is practical. Connections using long trace lengths, narrow trace widths, and/or connections through vias must be avoided.

11.2 Layout Example

Figure 20. LP8900 Example Layout

11.3 DSBGA Mounting

11.4 DSBGA Light Sensitivity

halogen lamps can affect the electrical performance if brought near to the device. lighting used inside most buildings has little effect on performance.

www.ti.com SNVS542E –MAY 2008–REVISED JUNE 2016 Product Folder Links: LP8900 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following: AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009)

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 31-May-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LP8900TLE-3333/NOPB ACTIVE DSBGA YZR 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM B LP8900TLE-AAAH/NOPB ACTIVE DSBGA YZR 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 3 LP8900TLE-AAEB/NOPB ACTIVE DSBGA YZR 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 A LP8900TLE-AAEC/NOPB ACTIVE DSBGA YZR 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 D LP8900TLX-3333/NOPB ACTIVE DSBGA YZR 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 31-May-2016 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8900TLE-3333/NOPB DSBGA YZR 6 250 210.0 185.0 35.0 LP8900TLE-AAAH/NOPB DSBGA YZR 6 250 210.0 185.0 35.0 LP8900TLE-AAEB/NOPB DSBGA YZR 6 250 210.0 185.0 35.0 LP8900TLE-AAEC/NOPB DSBGA YZR 6 250 210.0 185.0 35.0 LP8900TLX-3333/NOPB DSBGA YZR 6 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2016 Pack Materials-Page 2

www.ti.com TLA06XXX (Rev C) 0.600±0.075 D E NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. 4215044/A 12/12 D: Max = E: Max = 1.49 mm, Min = 1.09 mm, Min = 1.43 mm 1.03 mm

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