LP8900

LP8900 NSC | Alldatasheet

Document overview

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Technical content

Features

■ Operation from 1.8V to 5.5V Input ■ 1% accuracy Over Temperature ■ Output Voltage from 1.2V to 3.6V ■ 6µVRMSOutput Voltage Noise ■ PSRR 75dB at 1kHz ■ 110mV Dropout at 200mA load ■ 48µA Quiescent Current per regulator ■ 80µs Start-Up time ■ Stable with Ceramic Capacitors as small as 0402 ■ Thermal-Overload and Short-Circuit Protection Package ■ 6 pin micro SMD (1.5mm x 1.1mm)

Applications

■ Battery Operated Devices ■ Hand-Held Information Appliances ■ Noise Sensitive RF Applications ■ DC/DC Convertor Post Regulation/Filter Typical Application Circuit 30039302 © 2009 National Semiconductor Corporation 300393 www.national.com LP8900 Ultra Low Noise, Dual 200mA Linear Regulator for RF/Analog Circuits

Pin No. Symbol Name and Function A1 VEN 1 Enable Input; Enables the Regulator when ≥ 1.2V. Disables the Regulator when ≤ 0.4V. Enable Input has an internal 3MΩ pull-down resistor to GND. B1 GND Common Ground. C1 VEN 2 Enable Input; Enables the Regulator when ≥ 1.2V. Disables the Regulator when ≤ 0.4V. Enable Input has an internal 3MΩ pull-down resistor to GND. C2 VOUT 2 Voltage output. A Low ESR Ceramic Capacitor should be connected from this pin to GND. (See Application Information) Connect this output to the load circuit. B2 VIN Voltage Supply Input. A 1.0µF capacitor should be connected from this pin to GND. A2 VOUT 1 Voltage output. A Low ESR Ceramic Capacitor should be connected from this pin to GND. (See Application Information) Connect this output to the load circuit. Connection Diagram

6 Bump Thin Micro SMD, Large Bump

See NS package number TLA06 www.national.com 2 LP8900

Ordering Information (6-Bump Micro SMD) Only available as Lead Free. Output Voltage (V) Grade Order Number Supplied as 250 Units, Tape and Reel Order Number Supplied as 3000 Units, Tape and ReelVout 1 Vout2 2.8V 2.8V LP8900TLE_3333 LP8900TLX_3333 2.8V 2.7V LP8900TLE_AAEB LP8900TLX_AAEB 2.8V 1.2V LP8900TLE_AAEC LP8900TLX_AAEC *2.8V 1.8V LP8900TLE_AACB LP8900TLX_AACB 2.7V 2.7V LP8900TLE_AAAH LP8900TLX_AAAH * Contact your local NSC Sales Office for availability 3 www.national.com LP8900

(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN, VOUT Pins: Voltage to GND -0.3 to 6.5V VEN : Voltage to GND -0.3 to (VIN + 0.3V) to 6.5V (max) Junction Temperature 150°C Lead/Pad Temp. (Note 3) Micro SMD 260°C Storage Temperature -65 to 150°C Continuous Power Dissipation (Note 4) Internally Limited ESD (Note 5) Human Body Model 2KV Machine Model 200V Operating Ratings (Note 1) Input Voltage Range 1.8 to 5.5V Recommended Load Current per channel 200mA Junction Temperature -40°C to 125°C Ambient Temperature TA Range (Note 6) -40°C to 85°C Thermal Properties (Note 1) Junction To Ambient Thermal Resistance(Note 7) θJA JEDEC Board (Note 8) 108°C/W θJA 4 Layer Board 172°C/W

Electrical Characteristics

Unless otherwise noted, VEN =1.2V, VIN = VOUT + 0.5V, or 1.8V, whichever is higher , where VOUT is the higher of VOUT1 and VOUT2. CIN = COUT = 1µF, IOUT = 1.0mA . Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full junction temperature range for operation, −40 to +125°C. (Note 9) Symbol Parameter Conditions Typ Limit UnitsMin Max VIN Input Voltage (Note 10) 1.8 5.5 V ΔVOUT Output Voltage Tolerance VIN = VOUT(NOM) + 0.5V to 5.5V ILOAD = 1mA -1.0 1.0 % VIN = 1.8V to 5.5V ILOAD = 1mA, VOUT = 1.2V -2.25 2.25 % Line Regulation Error VIN = VOUT(NOM) +0.5V to 5.5V, IOUT = 1mA 0.05 %/V Load Regulation Error IOUT = 1mA to 200mA 4 9 mV VDO Dropout Voltage(Note 11) IOUT = 200mA VOUT = 3.6V 55 82 mVVOUT = 2.8V 110 164 VOUT = 1.8V 185 260 ILOAD Load Current (Note 12) 0 200 mA IQ Quiescent Current VEN1 = 1.2V, VEN2 = 0V IOUT = 0mA 48 120 µA VEN1 = 1.2V, VEN2 = 1.2V IOUT = 0mA 85 200 VEN1 = 1.2V, VEN2 = 1.2V IOUT = 200mA 210 VEN ≤ 0.4V 0.003 1.0 ISC Short Circuit Current Limit VIN = 3.6V (Note 13) 600 900 mA PSRR Power Supply Rejection Ratio (Note 14) f = 1kHz, IOUT = 200mA 75 dB f = 10kHz, IOUT = 200mA 65 f = 100kHz, IOUT = 200mA 45 f = 1MHz, IOUT = 200mA 30 en Output noise Voltage (Note 14) BW = 10Hz to 100kHz, VIN = 4.2V, COUT = 1.0µF IOUT = 0mA 6 µVRMS IOUT = 1mA 10 IOUT = 200mA 6 TSHUTDOWN Thermal Shutdown Temperature 155 °CHysteresis 15 www.national.com 4 LP8900

Electrical Characteristics con't. Unless otherwise noted, VEN =1.2V, VIN = VOUT + 0.5V, or 1.8V, whichever is higher, where VOUT is the higher of VOUT1and VOUT2. CIN= COUT = 1µF, IOUT = 1mA. Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full junction temperature range for operation, −40 to +125°C. (Note 9) Symbol Parameter Conditions Typ Limit UnitsMin Max Enable Control Characteristics IEN Maximum Input Current at VEN Input(Note 15) VEN = 0V, VIN = 5.5V 0.003 µAVEN = VIN = 5.5V 4 VIL Low Input Threshold VIN = 1.8V to 5.5V 0.4 V VIH High Input Threshold VIN = 1.8V to 5.5V 1.2 V Timing\\Transient Characteristics(Note 14) TON Turn On Time To 95% Level VOUT(nom) 80 200 µs TOFF Turn Off Time 5% of VOUT(NOM),IOUT= 0mA 0.4 1 ms Line Transient Response |δVOUT| Trise = Tfall = 30µs δVIN = 600mV 1 mV (pk - pk) Transient Response Load Transient Response |δVOUT| Trise = Tfall = 1µs IOUT = 1 mA to 200mA 80 mVIOUT = 200mA to 1mA 70 Overshoot on Start-up 0 1 % Note 1: Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All Voltages are with respect to the potential at the GND pin. Note 3: For further information on these packages please refer to the following application notes,AN-1112 Micro SMD Wafer Level Chip Scale Package. Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Note 5: The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. Note 6: The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125°C), the maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part / package in the application (θJA), as given by the following equation: TA(max) = TJ(max-op) - (θJA × PD(max)). Note 7: Junction to ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power dissipation is possible, special care must be paid to thermal dissipation issues in board design. Note 8: Full details can be found in JESD61-7 Note 9: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production at TJ = 25°C or correlated using Statistical Quality Control methods. Operation over the temperature specification is guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 10: The minimum input voltage = VOUT(NOM) + 0.5V or 1.8V, whichever is greater. Note 11: Dropout voltage is voltage difference between input and output at which the output voltage drops to 100mV below its nominal value. This parameter is only specified for output voltages above 1.8V. Note 12: The device maintains the regulated output voltage without a load. Note 13: Short circuit current is measured with VOUT pulled to 0V. Note 14: This electrical specification is guaranteed by design. Note 15: Enable Pin has an internal 3MΩ typical, resistor connected to GND. Note 16: The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R or X5R. (See capacitor section in Applications Hints) Recommended Capacitor Specifications Symbol Parameter Conditions Typ Limit UnitsMin Max CIN Input Capacitor Capacitance (Note 16) 1.0 0.33 10 µF COUT Output Capacitor 1.0 0.33 4.7 ESR 5 500 mΩ 5 www.national.com LP8900

Typical Performance Characteristics. Unless otherwise specified, CIN = COUT=1.0µF Ceramic, VIN = VOUT(NOM) + 1.0V or 1.8V whichever is greater, TA = 25°C, VOUT(NOM) = 2.85V , Enable pin is tied to VIN. Power Supply Rejection Ratio 30039310 Power Supply Rejection Ratio 30039309 Noise Density 30039312 Output Voltage Change vs Temperature 30039311 Ground Current vs Load Current 30039314 Ground Current vs Load Current 30039315 www.national.com 6 LP8900

Typical Performance Characteristics con't. Unless otherwise specified, CIN = COUT= 1.0µF Ceramic, VIN = VOUT(NOM) + 1.0V or 1.8V whichever is greater, TA = 25°C, VOUT(NOM) = 2.85V , Enable pin is tied to VIN. Ground Current vs VIN 30039318 Vout 1 Load Transient 1 to 200mA 30039321 Vout 1 Load Transient 0 to 200mA 30039319 Load Transient. Vin = 1.8V, Vout = 1.2V 30039320 Line Transient, 200mA per Channel 30039323 Short Circuit Current 30039322 7 www.national.com LP8900

Typical Performance Characteristics con't. Unless otherwise specified, CIN= COUT = 1.0µF Ceramic, VIN = VOUT(NOM) + 1.0V or 1.8V whichever is greater, TA = 25°C, VOUT(NOM) = 2.85V , Enable pin is tied to VIN. Enable Start-up Characteristics 30039325 Vin and Enable Tied Together 30039342 Shutdown Characteristics 30039326 Dropout Voltage 30039328 Dropout Voltage vs Output Voltage 30039341 www.national.com 8 LP8900

Application Information

In common with most regulators, the LP8900 requires exter- nal capacitors for regulator stability. The LP8900 is specifi- cally designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitor is required for stability. It is recommended that a 1.0µF capacitor be connected between the LP8900 in- put pin and ground (this capacitance value may be increased to 10µF). This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic fail- ures due to surge current when connected to a low- impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance, tempera- ture, and voltage coefficients must be considered when se- lecting the capacitor to ensure the capacitance will remain ≊ 1.0µF over the entire operating temperature range. OUTPUT CAPACITOR Correct selection of the output capacitor is critical to ensure stable operation in the intended application. The output capacitor must meet all the requirements specified in the recommended capacitor table over all conditions in the application. These conditions include DC bias, frequency and temperature. Unstable operation will result if the capacitance drops below the minimum specified value. The LP8900 is designed specifically to work with very small ceramic output capacitors. A 1.0µF ceramic capacitor (dielec- tric type X7R or X5R) with an ESR between 5mΩ to 500mΩ, is suitable in the LP8900 application circuit. Other ceramic types such as Y5V and Z5U are less suitable owing to their inferior temperature characteristics. (See sec- tion on Capacitor Characteristics). It is also recommended that the output capacitor is placed within 1cm of the output pin and returned to a clean, low impedance, ground connection. It is possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see the section Capacitor Characteristics). NO-LOAD STABILITY The LP8900 will remain stable and in regulation with no ex- ternal load. This is an important consideration in some cir- cuits, for example CMOS RAM keep-alive applications. CAPACITOR CHARACTERISTICS The LP8900 is designed to work with ceramic capacitors on the input and outputs to take advantage of the benefits they offer. For capacitance values around 1.0µF, ceramic capaci- tors give the circuit designer the best design options in terms of low cost and minimal area. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly dependant on the conditions of operation and capacitor type. In particular, to ensure stability, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. Capaci- tance value can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The ca- pacitor parameters are also dependant on the particular case size with smaller sizes giving poorer performance figures in general. 30039340 FIGURE 1. Effect of DC bias on Capacitance Value.

range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed. ENABLE CONTROL The LP8900 may be switched ON or OFF by a logic input at the ENABLE pin.A high voltage at this pin will turn the device on. When the enable pin is low, the regulator output is off and the device typically consumes 3nA. However if the application does not require the shutdown feature, the VEN pin can be tied to VIN to keep the regulator permanantly on. To ensure fast start-up is achieved, VEN should be driven separately. A 3MΩ pulldown resister ties the VEN input to ground, this en- sures that the device will remain off when the enable pin is left open circuit. To ensure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. micro SMD MOUNTING The micro SMD package requires specific mounting tech- niques which are detailed in the National Semiconductor Application Note (AN-1112). Referring to the section Surface Mount Technology (SMT) Assenbly Considerations, it should be noted that the pad style which must be used with the 6 pin package is NSMD (non-solder mask defined) type. For best results during assembly, alignment ordinals on the PCB may be used to facilitate placement of the micro SMD device. micro SMD LIGHT SENSITIVITY Exposing the micro SMD device to direct sunlight may cause mis-operation of the device. Light sources such as halogen lamps can affect the electrical performance if brought near to the device. The wavelengths which have most detrimental effect are reds and infra-reds, which means that fluorescent lighting, used inside most buildings will have little effect on performance. www.national.com 10 LP8900

11 www.national.com LP8900

Physical Dimensions inches (millimeters) unless otherwise noted The Dimensions for X1, X2 and X3 as given as: X1 = 1.057mm ± 0.030mm X2 = 1.463mm ± 0.03mm X3 = 0.60mm ± 0.075mm www.national.com 12 LP8900

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