Driver IC

LP8869CQPWPRQ1.A

Texas Instruments

LP8867C-Q1, LP8869C-Q1 Low EMI Automotive LED Driver with 4-, 3- Channels AUGUST 2019

Manufacturer: Texas Instruments

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PDF pages: 42

Technical content

4.5...40 V COUTCIN RISET Up to 120 mA/string SW LDO FSET VDDIO/EN SYNC PGND GND PAD VIN ISETFAULT EN BRIGHTNESS RFSET R1R2 CLDO CFB FAULT VDDIO Output Current (mA) System Efficiency (%) 80 160 240 320 400 480 100 D000 VIN = 16V VIN = 12V VIN = 8V VIN = 6V Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP8867C-Q1, LP8869C-Q1 SNVSBC7 –AUGUST 2019 LP8867C-Q1,LP8869C-Q1LowEMIAutomotiveLEDDriverwith4-,3-Channels

1 Features

1• AEC-Q100 Qualified for automotive applications: – Device temperature grade 1: –40°C to +125°C, TA

3-, 4-Channel 120-mA LED driver for automotive LCD display – High dimming ratio of 10 000:1 at 100 Hz – Current matching 1% (typical) – LED String current up to 120 mA per channel – Outputs can be combined externally for higher current per string
Integrated boost and SEPIC converter for LED string power – Input voltage operating range 4.5 V to 40 V – Output voltage up to 45 V – Integrated 3.3-A Switch FET – Switching frequency 300 kHz to 2.2 MHz – Switching synchronization input – Spread spectrum for lower EMI
Protection and fault detection – Fault output – Input voltage OVP, UVLO – Boost OVP – SW OVP – LED Open and short fault detection – Thermal shutdown Simplified Schematic

2 Applications

Backlight for: – Automotive infotainment – Automotive instrument clusters – Smart mirrors – Heads-up displays (HUD)

3 Description

The LP8867C-Q1, LP8869C-Q1 is an automotive highly-integrated, low-EMI, easy-to-use LED driver with DC-DC converter. The DC-DC converter supports both boost and SEPIC mode operation. The device has four or three high-precision current sinks that can be combined for higher current capability. The DC-DC converter has adaptive output voltage control based on the LED forward voltages. This feature minimizes the power consumption by adjusting the voltage to the lowest sufficient level in all conditions. For EMI reduction DC-DC supports spread spectrum for switching frequency and an external synchronization with dedicated pin. A wide- range adjustable frequency allows the LP886xC-Q1 to avoid disturbance for sensitive frequency band. The input voltage range for the LP886xC-Q1 is from

4.5 V to 40 V to support automotive stop, start and

load dump condition. The LP886xC-Q1 integrates extensive fault detection features. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LP8867C-Q1 HTSSOP (20) 6.50 mm × 4.40 mm LP8869C-Q1 (1) For all available packages, see the orderable addendum at the end of the data sheet. System Efficiency

12.3 Receiving Notification of Documentation Updates 32

13 Mechanical, Packaging, and Orderable

4 Revision History

August 2019 * Initial Release

11EP* *EXPOSED PAD OUT2 GND OUT3 GND NC LDO VDDIO/EN FSET VIN VIN NC FB PGND SW OUT1 GND PWM FAULT ISET SYNC 11EP* *EXPOSED PAD OUT2 GND OUT3 OUT4 NC LDO VDDIO/EN FSET VIN VIN NC FB PGND SW OUT1 GND PWM FAULT ISET SYNC LP8867C-Q1, LP8869C-Q1 www.ti.com SNVSBC7 –AUGUST 2019 Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

5 Device Comparison Table

LP8869-Q1 LP8869C-Q1 LP8867-Q1 LP8867C-Q1 Number of LED channels 3 3 4 4 LED current / channel 120 mA 120 mA 120 mA 120 mA Power Line FET Control and Automatic Current De-rating Support Yes No Yes No

6 Pin Configuration and Functions

20-Pin HTSSOP With Exposed Thermal Pad Top View 20-Pin HTSSOP With Exposed Thermal Pad Top View

LP8867C-Q1, LP8869C-Q1 SNVSBC7 –AUGUST 2019 www.ti.com Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME

1 VIN A Input power pin and pin for input voltage detection for OVP protection

2 LDO A Output of internal LDO; connect a 1-μF decoupling capacitor between this pin and noise-free GND. Put the capacitor as close to the chip as possible. 3 FSET A DC-DC (boost or SEPIC) switching frequency setting resistor; for normal operation, resistor value from 24 kΩ to 219 kΩ must be connected between this pin and ground. 4 VDDIO/EN I Enable input for the device as well as supply input (VDDIO) for digital pins. 5 FAULT OD Fault signal output. If unused, the pin may be left floating. 6 SYNC I Input for synchronizing DC-DC converter. If synchronization is not used, connect this pin to GND to disable spread spectrum or to VDDIO/EN to enable spread spectrum. 7 PWM I PWM dimming input.

8 NC — No connect

9 GND G Ground

10 ISET A LED current setting resistor; for normal operation, resistor value from 20 kΩ to 129 kΩ must be connected between this pin and ground. 11 GND G Ground.

12 OUT4/GND A

Current sink output for LP8867C-Q1 This pin must be connected to GND if not used. GND pin for LP8869C-Q1 13 OUT3 A Current sink output. This pin must be connected to GND if not used. 14 OUT2 A Current sink output. This pin must be connected to GND if not used. 15 OUT1 A Current sink output. This pin must be connected to GND if not used.

16 FB A

DC-DC (boost or SEPIC) feedback input; for normal operation this pin must be connected to the middle of a resistor divider between VOUT and ground using feedback resistor values greater than 5kΩ. 17 PGND G DC-DC (boost or SEPIC) power ground. 18 SW A DC-DC (boost or SEPIC) switch pin.

19 NC — No connect

20 VIN A Input power pin and pin for input voltage detection for OVP protection

LP8867C-Q1, LP8869C-Q1 www.ti.com SNVSBC7 –AUGUST 2019 Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the potential at the GND pins. (3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and disengages at TJ = 145°C (typical). (4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Voltage on pins VIN, SD, SW, FB –0.3 50 VOUT1, OUT2, OUT3, OUT4 –0.3 45 LDO, SYNC, FSET, ISET, PWM, VDDIO/EN, FAULT –0.3 5.5 Continuous power dissipation(3) Internally Limited Ambient temperature, TA (4) –40 125 °C Junction temperature, TJ (4) –40 150 °C Storage temperature, Tstg –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002, all pins (1) ±2000 VCharged-device model (CDM), per AEC Q100-011 Corner pins (1, 10, 11 and 20) ±750 All pins ±500 (1) All voltages are with respect to the potential at the GND pins.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT Voltage on pins VIN 4.5 12 45 V SW 0 45 OUT1, OUT2, OUT3, OUT4 0 40 FB, FSET, LDO, ISET, VDDIO/EN, FAULT 0 5.25 SYNC, PWM 0 VDDIO/EN

LP8867C-Q1, LP8869C-Q1 SNVSBC7 –AUGUST 2019 www.ti.com Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. (2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.4 Thermal Information

THERMAL METRIC(1) LP886xC-Q1 UNITPWP (HTSSOP)

20 PINS

RθJA Junction-to-ambient thermal resistance(2) 44.2 °C/W RθJCtop Junction-to-case (top) thermal resistance 26.5 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 22.2 °C/W RθJCbot Junction-to-case (bottom) thermal resistance 2.5 °C/W

7.5 Electrical Characteristics

Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ Standby supply current Device disabled, VVDDIO/EN = 0 V, VIN = 12 V 4.5 20 μA Active supply current VIN = 12 V, VOUT = 26 V, output current 80 mA/channel, converter ƒSW = 300 kHz 5 12 mA

7.6 Internal LDO Electrical Characteristics

Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLDO Output voltage VIN = 12 V 4.15 4.3 4.55 V VDR Dropout voltage 120 300 430 mV ISHORT Short circuit current 50 mA IEXT Current for external load 5 mA

7.7 Protection Electrical Characteristics

Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOVP VIN OVP threshold voltage 41 42 44 V VUVLO VIN UVLO Falling threshold 3.7 3.85 4 V VUVLO_HYST VIN UVLO Rising threshold - VIN UVLO Fallling threshold 150 mV VFB_OVP FB threshold for BST_OVP fault 2.3 V TTSD Thermal shutdown Rising threshold 150 165 175 ℃ TTSD_HYS Thermal shutdown Rising threshold - Thermal shutdown Falling threshold 20 ℃

LP8867C-Q1, LP8869C-Q1 www.ti.com SNVSBC7 –AUGUST 2019 Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUTx), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all parts. LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.

7.8 Current Sinks Electrical Characteristics

Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ILEAKAGE Leakage current Outputs OUT1 to OUT4 , VOUTx = 45 V, EN = L 0.1 5 µA IMAX Maximum current OUT1, OUT2, OUT3, OUT4, RISET = 20 kΩ 120 mA IOUT Output current accuracy IOUT = 100 mA −5% 5% IMATCH Output current matching(1) IOUT = 100 mA, PWM duty =100% 1% 5% VLOW_COMP Low comparator threshold 0.9 V VMID_COMP Mid comparator threshold 1.9 V VHIGH_COMP High comparator threshold 5.6 6 7 V (1) This specification is not ensured by ATE.

7.9 PWM Brightness Control Electrical Characteristics

Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ƒPWM PWM input frequency 100 20 000 Hz tON/OFF Minimum on/off time(1) 0.5 µs (1) This specification is not ensured by ATE.

7.10 Boost and SEPIC Converter Characteristics

Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage 4.5 40 V VOUT Output voltage 6 45 ƒSW_MIN Minimum switching frequency Defined by RFSET resistor 300 kHz ƒSW_MAX Maximum switching frequency Defined by RFSET resistor 2 200 kHz tOFF Minimum switch OFF time(1) ƒSW ≥ 1.15 MHz 55 ns ISW_MAX SW current limit first triggerred 3.3 3.7 4.1 A tSW_MAX SW current limit first triggerred period 1.6 s ISW_LIM SW current limit 3 3.35 3.7 A RDSON FET RDSON 240 400 mΩ fSYNC External SYNC frequency 300 2 200 kHz tSYNC_ON External SYNC on time(1) 150 ns tSYNC_OFF External SYNC off time(1) 150 ns

7.11 Logic Interface Characteristics

Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUT VDDIO/EN VIL Input low level 0.4 V VIH Input high level 1.65 IEN Input DC current −1 5 30 µA Input transient current during VDDIO/EN powering up 1.2 mA LOGIC INPUT SYNC, PWM

LP8867C-Q1, LP8869C-Q1 SNVSBC7 –AUGUST 2019 www.ti.com Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Logic Interface Characteristics (continued) Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Input low level 0.2 × VDDIO/E N V VIH Input high level 0.8 × VDDIO/E N II Input current −1 1 μA LOGIC OUTPUT FAULT VOL Output low level Pullup current 3 mA 0.3 0.5 V ILEAKAGE Output leakage current V = 5.5 V 1 μA

7.12 Typical Characteristics

Figure 1. Maximum Boost Current Figure 2. Maximum Boost Current Figure 3. Maximum Boost Current Figure 4. LED Current Sink Matching Figure 5. Boost Efficiency Figure 6. Boost Efficiency

8 Detailed Description

8.1 Overview

The LP8867C-Q1, LP8869C-Q1 is a highly integrated LED driver for automotive infotainment , cluster and HUD medium-size LCD backlight applications. It includes a DC-DC with an integrated FET, supporting both boost and SEPIC modes, an internal LDO enabling direct connection to battery without need for a pre-regulated supply and 3 or 4 LED current sinks. The VDDIO/EN pin provides the supply voltage for digital IOs (PWM and SYNC inputs) and at the same time enables the device. The switching frequency on the DC-DC converter is set by a resistor connected to the FSET pin. The maximum voltage of the DC-DC is set by a resistive divider connected to the FB pin. For the best efficiency, the output voltage is adapted automatically to the minimum necessary level needed to drive the LED strings. This is done by monitoring LEDs' cathode voltage in real time. For EMI reduction, two optional features are available:

Spread spectrum, which reduces EMI noise around the switching frequency and its harmonic frequencies
DC-DC can be synchronized to an external frequency connected to SYNC pin The 3 or 4 constant current outputs OUT1, OUT2, OUT3, and OUT4 provide LED current up to 120 mA. Value for the current per OUT pin is set with a resistor connected to ISET pin. Current sinks that are not used must be connected to ground. Grounded current sink is disabled and excluded from boost adaptive voltage detection loop. Brightness is controlled with the PWM input. Frequency range for the input PWM is from 100 Hz to 20 kHz. LED output PWM behavior follows the input PWM so the output frequency is equal to the input frequency. LP886xC-Q1 has extensive fault detection features:
LED open and short detection
VIN input overvoltage protection
VIN input undervoltage protection
VBoost output overvoltage protection
SW overvoltage protection
Thermal shutdown in case of chip overheated Fault condition is indicated through the FAULT output pin.

D VIN LDO CLDO SW FB BOOST CONTROLLER VIN SYNC PGND OUT1 OUT2 OUT3 OUT4 GND 4 x LED CURRENT SINK ANALOG BLOCKS (CLOCK GENERATOR, VREF, TSD etc.) DIGITAL BLOCKS (FSM, ADAPTIVE VOLTAGE CONTROL, SAFETY LOGIC etc.) VDDIO/EN FAULT RISET EXPOSED PAD LDO ISET CURRENT SETTING FSETRFSET PWM VDDIO CIN L LP8867C-Q1, LP8869C-Q1 SNVSBC7 –AUGUST 2019 www.ti.com Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Integrated DC-DC Converter

SEPIC mode. The output voltage, switching frequency are all configured by external resistors.

8.3.1.1 DC-DC Converter Parameter Configuration

Figure 9. Boost Block Diagram

8.3.1.1.1 Switching Frequency

ƒSW is switching frequency, kHz
RFSET is frequency setting resistor, kΩ (1) For example, if RFSET is set to 163 kΩ, fSW will be 400 kHz. In most cases, lower switching frequency has higher system efficiency and lower internal temperature increase.

8.3.1.1.2 Spread Spectrum and External SYNC

is low, spread spectrum function is disabled. If SYNC pin level is high, spread spectrum function is enabled. will be enabled/disabled depending on the final SYNC pin level. kHz switching with external clock.

Table 1. DC-DC Synchronization Mode (2) Due to current sensing comparator delay the actual minimum off time is 6 ns (typical) longer than in the table.

8.3.1.1.3 Recommended Component Value and Internal Parameters

are chosen automatically according to the selected switching frequency (see Table 2) to ensure stability. Table 2. Boost Converter Parameters(1)

8.3.1.1.4 DC-DC Converter Switching Current Limit

cycle-by-cycle when the internal FET current reaches the limit. of 1.6 seconds when a 3.35-A limit is reached. seconds, and this 3.2-second period repeats.

8.3.1.1.5 DC-DC Converter Light Load Mode

VIN voltage is very close to VOUT
Loading current is very low
PWM pulse width is very short When DC-DC converter enters into light load mode, DC-DC converter stops switching occasionally to make sure boost output voltage won't rise up too much. It could also be called as PFM mode, since the DC-DC converter switching frequency will change in this mode.

8.3.1.2 Adaptive Voltage Control

§ u u ¨ ¸ © ¹ OUT1 OUT2 OUT3 OUT4 No actions Boost decreases voltage Boost Increases voltage No output is close to VLOW_COMP threshold One output is lower than VLOW_COMP threshold Normal Conditions Dynamic Conditions OUT 1-4 VOLTAGE VLOW_COMP The lowest channel voltage touches VLOW_COMP threshold OUT1 OUT2 OUT3 OUT4 OUT1 OUT2 OUT3 OUT4 LP8867C-Q1, LP8869C-Q1 www.ti.com SNVSBC7 –AUGUST 2019 Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated VLOW_COMP threshold. The boost voltage is also lowered if all OUTx voltages are higher than VLOW_COMP threshold. The boost voltage keeps unchanged when one of OUTx voltage touches the VLOW_COMP threshold. In normal operation, the lowest voltage among the OUTx pins is around VLOW_COMP, and boost voltage stays constant. VLOW_COMP level is the minimum voltage which could guarantee proper LED current sink operation. See Figure 10 for how the boost voltage automatically scales based on the OUT1-4 pin voltage.

Figure 10. Adaptive Boost Voltage Control Loop Function

8.3.1.2.1 Using Two-Divider

VBG = 1.2 V
R2 recommended value is 10 kΩ to 200 kΩ
R1/R2 recommended value is 5 to 10 for <1150kHz DC-DC switching frequency
R1/R2 recommended value is 10 to 20 for >1150kHz DC-DC switching frequency
K = 1 for maximum adaptive boost voltage (typical)
K = 0 for minimum adaptive boost voltage (typical)
K = 0.88 for initial boost voltage (typical) (2) For example, if R1 is set to 750 kΩ and R2 is set to 130 kΩ, VBOOST will be in the range of 8.1 V to 37.1 V.

Figure 11. FB External Two-Divider Resistors

8.3.1.2.2 Using T-Divider

Alternatively, a T-divider can be used if resistance less than 100 kΩ is required for the external resistive divider.

VBG = 1.2 V
R2 recommended value is 10 kΩ to 200 kΩ
R1/R2 recommended value is 5 to 10 for <1150kHz DC-DC switching frequency
R1/R2 recommended value is 10 to 20 for >1150kHz DC-DC switching frequency
K = 1 for maximum adaptive boost voltage (typical)
K = 0 for minimum adaptive boost voltage (typical)
K = 0.88 for initial boost voltage (typical) (3) For example, if R1 is set to 100 kΩ, R2 is set to 10 kΩ and R3 is set to 60 kΩ, VBOOST will be in the range of 13.2 V to 42.6 V.

Figure 12. FB external T-divider resistors

8.3.1.2.3 Feedback Capacitor

fz = 20 kHz (4) For example, if R1 is set to 750 kΩ, CFB needs to be around 11 pF.

Figure 13. FB External Resistors With Capacitor When Operating With No Electrolytic Capacitor In Boost

8.3.2 Internal LDO

The internal LDO regulator converts the input voltage at VIN to a 4.3-V output voltage for internal use. Connect a minimum of 1-µF ceramic capacitor from LDO pin to ground, as close to the LDO pin as possible.

8.3.3 LED Current Sinks

8.3.3.1 LED Output Configuration

LP886xC-Q1 detects LED output configuration during start-up. Any current sink output connected to ground is disabled and excluded from the adaptive voltage control of the DC-DC converter and fault detections. If more current is needed, LP886xC-Q1's output could also be connected together to support the high current LED.

8.3.3.2 LED Current Setting

The output current of the LED outputs is controlled with external RISET resistor. RISET value for the target LED current per channel can be calculated using Equation 5: where

VBG = 1.2 V
RISET is current setting resistor, kΩ
ILED is output current per OUTx pin, mA (5) For example, if RISET is set to 20 kΩ, ILED will be 120 mA per channel.

8.3.3.3 Brightness Control

LP886xC-Q1 controls the brightness of the display with conventional PWM. Output PWM directly follows the input PWM. Input PWM frequency can be in the range of 100 Hz to 20 kHz.

8.3.4 Protection and Fault Detections

The LP886xC-Q1 has fault detection for LED open and short, VIN input overvoltage protection (VIN_OVP) , VIN undervoltage protection (VIN_UVLO), Boost output overvoltage protection (BST_OVP), SW overvoltage protection (SW_OVP) and thermal shutdown (TSD).

8.3.4.1 Supply Fault and Protection

8.3.4.1.1 VIN Undervoltage Fault (VIN_UVLO)

The LP886xC-Q1 device supports VIN undervoltage protection. The VIN undervoltage falling threshold is 3.85-V typical and rising threshold is 4-V typical. If during operation of the LP886xC-Q1 device, the VIN pin voltage falls below the VIN undervoltage falling threshold, the boost, LED outputs, and power-line FET will be turned off, and the device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low. The LP886xC-Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again. VIN_UVLO fault detection is available in SOFT START, BOOST START, and NORMAL state.

8.3.4.1.2 VIN Overvoltage Fault (VIN_OVP)

The LP886xC-Q1 device supports VIN overvoltage protection. The VIN overvoltage threshold is 42-V typical. If during LP886xC-Q1 operation, VIN pin voltage rises above the VIN overvoltage threshold, the boost, LED outputs and the power-line FET will be turned off, and the device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low. The LP886xC-Q1 will exit FAULT RECOVERY mode after 100 ms and try the start- up sequence again. VIN_OVP fault detection is available in SOFT START, BOOST START and NORMAL state.

8.3.4.2 Boost Fault and Protection

8.3.4.2.1 Boost Overvoltage Fault (BST_OVP)

fault detection is available in NORMAL state.

VBOOST is the current target boost adaptive voltage, which in most time is the current largest LED string forward voltage among multiple strings + 0.9 V in steady state
VFB_OVP = 2.3 V
VBG = 1.2 V
R1 and R2 is the resistor value of FB external network in Using Two-Divider and Using T-Divider (6) For example, if R1 is set to 750 kΩ and R2 is set to 130 kΩ, VBOOST will report OVP when the boost voltage is 7.4 V above target boost voltage. This equation holds true in both two-divider FB external network and T-divider FB external network.

8.3.4.2.2 SW Overvoltage Fault (SW_OVP)

SOFT START, BOOST START and NORMAL state.

8.3.4.3 LED Fault and Protection

Every LED current sink has 3 comparators for LED fault detections. Figure 14. Comparators for LED Fault Detection Figure 15 shows cases which generates LED faults. Any LED faults will pull the Fault pin low.

8.3.4.3.1 LED Open Fault (LED_OPEN)

8.3.4.3.2 LED Short Fault (LED_SHORT)

and 1.9 V). The shorted string is disconnected from the boost adaptive control loop and its output is disabled. LED Open fault detection and LED Short fault detection are available only in NORMAL state. Figure 15. Protection and DC-DC Voltage Adaptation Algorithms device goes to STANDBY and restarts when EN goes high again. faults by toggling VDDIO/EN pin low for a short period of 2 µs to 20 µs.

8.3.4.4 Thermal Fault and Protection (TSD)

start-up normally. TSD fault detection is available in SOFT START, BOOST START and NORMAL state.

8.3.4.5 Overview of the Fault and Protection Schemes

Table 3. Fault Detections off for this period but device stays in NORMAL. off for this period but device stays NORMAL.

8.4 Device Functional Modes

8.4.1 STANDBY State

will re-enter the STANDBY state when VDDIO/EN is pulled low for more than 50 µs.

8.4.2 SOFT START State

8.4.3 BOOST START State

the adaptive voltage control loop. Then the device enters into NORMAL state.

8.4.4 NORMAL State

8.4.5 FAULT RECOVERY State

Non-LED faults can trigger fault recovery state. LED drivers, boost converter and power-line FET are all disabled. After 100 ms, the device attempts to restart from SOFT START state if VDDIO/EN is still high.

8.4.6 State Diagram and Timing Diagram for Start-up and Shutdown

Figure 16. State Diagram

Figure 17. Timing Diagram for the Typical Start-Up and Shutdown

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

VDDIO/EN for enable
PWM input for brightness control
SYNC pin for boost synchronisation (optional)
FAULT output to indicate fault condition (optional)

9.2 Typical Applications

9.2.1 Typical Application for 4 LED Strings

boost switching frequency of 400 kHz. Figure 18. Four Strings 100 mA per String Configuration

ISAT > x(VOUT - VIN) VOUT VIN Where D = Where IRIPPLE = (2 x L x f) DQG'¶= (1 - D)(VOUT ± VIN) (VOUT) + IRIPPLE IOUTMAX '¶ For Boost LP8867C-Q1, LP8869C-Q1 www.ti.com SNVSBC7 –AUGUST 2019 Product Folder Links: LP8867C-Q1 LP8869C-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Typical Applications (continued)

9.2.1.1 Design Requirements

VIN voltage range 5 V – 28 V LED string 4P8S LEDs (30 V max) LED string current 100 mA Maximum boost voltage 34 V Boost switching frequency 400 kHz External boost sync not used Boost spread spectrum enabled L1 33 μH CIN 100 µF, 50 V CIN BOOST 2 × (10 µF, 50-V ceramic) + 33 µF, 50-V electrolytic COUT 2 × (10 µF, 50-V ceramic) + 33 µF, 50-V electrolytic CLDO 1 µF, 10 V RISET 24 kΩ RFSET 160 kΩ R1 685 kΩ R2 130 kΩ R8 10 kΩ

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Inductor Selection

There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferred. The saturation current must be greater than the sum of the maximum load current, and the worst case average- to-peak inductor current. Equation 7 shows the worst case conditions

IRIPPLE - peak inductor current
IOUTMAX - maximum load current
VIN - minimum input voltage in application
L - min inductor value including worst case tolerances
f - minimum switching frequency
VOUT - output voltage
D - Duty Cycle for CCM Operation (7) As a result, the inductor should be selected according to the ISAT. A more conservative and recommended approach is to choose an inductor that has a saturation current rating greater than the maximum current limit. A saturation current rating of at least 4.1 A is recommended for most applications. See Table 2 for recommended inductance value for the different switching frequency ranges. The inductor’s resistance should be less than 300 mΩ for good efficiency.

See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies. Power Stage Desinger Tool can be used for the boost calculation.

9.2.1.2.2 Output Capacitor Selection

9.2.1.2.3 Input Capacitor Selection

frequencies are shown in Table 2.

9.2.1.2.4 LDO Output Capacitor

value selection. Typically a 1-µF capacitor is sufficient.

9.2.1.2.5 Diode

switching. A <500-pF junction capacitance at VR= 0.1 V Schottky diode is recommended.

9.2.1.3 Application Curves

Figure 19. System Efficiency Figure 20. Typical Start-Up

9.2.2 SEPIC Mode Application

the efficiency. Also, in this example, an external clock is used to synchronize SEPIC switching frequency. External clock input can be modulated to spread switching frequency spectrum. Figure 21. SEPIC Mode, 4 Strings 100 mA and String Configuration

9.2.2.1 Design Requirements

VIN voltage range 4.5 V – 30 V LED string 4P4S LEDs (15 V max) LED string current 100 mA Maxmum output voltage 20 V SEPIC switching frequency 2.2 MHz External sync for SEPIC used Spread spectrum Internal spread spectrum disabled (external sync used) L1, L2 4.7 μH CIN 10 µF 50 V CIN SEPIC 2 × 10 µF, 50-V ceramic + 33 µF, 50-V electrolytic C1 10-µF 50-V ceramic C2 30 pF COUT 2 × 10 µF, 50-V ceramic + 33 µF, 50-V electrolytic CLDO 1 µF, 10 V RISET 24 kΩ RFSET 24 kΩ R1 265 kΩ R2 37 kΩ R3 10 kΩ

9.2.2.2 Detailed Design Procedure

In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output voltage. Because of this, the maximum sum of input and output voltage must be limited below 49 V. See the Detailed Design Procedure section for general external component guidelines. Main differences of SEPIC compared to boost are described below. Power Stage Designer™ Tool can be used for modeling SEPIC behavior. For detailed explanation on SEPIC see Texas Instruments Analog Applications Journal Designing DC/DC Converters Based on SEPIC Topology.

9.2.2.2.1 Inductor

In SEPIC mode, currents flowing through the coupled inductors or the two separate inductors L1 and L2 are the input current and output current, respectively. Values can be calculated using Power Stage Designer™ Tool or using equations in Designing DC/DC Converters Based on SEPIC Topology.

9.2.2.2.2 Diode

In SEPIC mode diode peak current is equal to the sum of input and output currents. Diode rating for peak repetitive current should be greater than SW pin current limit (up to 4.1 A for transients) to ensure reliable operation in boost mode. Average current rating should be greater than the maximum output current. Diode voltage rating must be higher than sum of input and output voltages.

9.2.2.2.3 Capacitor C1

TI recommends a ceramic capacitor with low ESR. Capacitor voltage rating must be higher than maximum input voltage.

9.2.2.3 Application Curves

Figure 22. SEPIC Efficiency Figure 23. System Efficiency

10 Power Supply Recommendations

wires, additional bulk capacitance may be required in addition to the ceramic bypass capacitors in the VIN line.

11 Layout

11.1 Layout Guidelines

Figure 24 is a layout recommendation for LP886xV-Q1 used to demonstrate the principles of a good layout. This layout can be adapted to the actual application layout if or where possible. It is important that all boost components are close to the chip, and the high current traces must be wide enough. By placing boost components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor must be placed as close as possible to the device. Here are some main points to help the PCB layout work:

Current loops need to be minimized: – For low frequency the minimal current loop can be achieved by placing the boost components as close as possible to the SW and PGND pins. Input and output capacitor grounds must be close to each other to minimize current loop size. – Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High-frequency return currents find a route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the positive current route in the ground plane, if the ground plane is intact under the route. To minimize the current loop for high frequencies: – Inductor's pin in SW node needs to be as near as possible to chip's SW pin – Put a small capacitor as near as possible to the diode's pin in boost output node and arrange vias to PGND plane close to the capacitor's GND pin.
Use separate power and noise-free grounds. PGND is used for boost converter return current and noise-free ground is used for more sensitive signals, such as LDO bypass capacitor grounding as well as grounding the GND pin of the device.
Boost output feedback voltage to LEDs must be taken out after the output capacitors, not straight from the diode cathode.
Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.
Input and output capacitors require strong grounding (wide traces, many vias to GND plane).

11.2 Layout Example

Figure 24. LP886xC-Q1 Boost Layout

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

Power Stage Designer™ Tool can be used for both boost and SEPIC: http://www.ti.com/tool/powerstage- designer

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

PowerPAD™ Thermally Enhanced Package
Understanding Boost Power Stages in Switch Mode Power Supplies
Designing DC-DC Converters Based on SEPIC Topology

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

Power Stage Designer, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LP8867CQPWPRQ1 Active Production HTSSOP (PWP) | 20 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8867CQ LP8867CQPWPRQ1.A Active Production HTSSOP (PWP) | 20 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8867CQ LP8869CQPWPRQ1 Active Production HTSSOP (PWP) | 20 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8869CQ LP8869CQPWPRQ1.A Active Production HTSSOP (PWP) | 20 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8869CQ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8867CQPWPRQ1 HTSSOP PWP 20 2000 350.0 350.0 43.0 LP8869CQPWPRQ1 HTSSOP PWP 20 2000 350.0 350.0 43.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 18X 0.65 5.85 20X 0.30 0.17 6.6

6.2 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.2 MAX

2X 1.25 MAX NOTE 5 2X 0.4 MAX NOTE 5 3.20 2.45 2.45 1.65 4X (0 -12 ) B 4.5 4.3 A 6.6 6.4 NOTE 3 0.75 0.50 (0.15) TYP PowerPAD TSSOP - 1.2 mm max heightPWP0020N SMALL OUTLINE PACKAGE 4218982/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may differ or may not be present. TM PowerPAD is a trademark of Texas Instruments. A 15 DETAIL A TYPICAL SCALE 2.300 THERMAL PAD 10 11

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP (3.4) NOTE 9 (6.5) NOTE 9 (1.35) TYP (1.3) TYP ( 0.2) TYP VIA (2.45) (3.2) PowerPAD TSSOP - 1.2 mm max heightPWP0020N SMALL OUTLINE PACKAGE 4218982/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 10 11 METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP (3.2) BASED ON

0.125 THICK

(2.45) BASED ON PowerPAD TSSOP - 1.2 mm max heightPWP0020N SMALL OUTLINE PACKAGE 4218982/B 12/2023 2.07 X 2.700.175 2.24 X 2.920.15 2.5 X 3.2 (SHOWN)0.125 2.74 X 3.580.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 10 11 METAL COVERED BY SOLDER MASK SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES

www.ti.com PACKAGE OUTLINE C 18X 0.65 5.85 20X 0.30 0.17 6.6 0.15 0.05 0.25 GAGE PLANE 0 -8 2X 0.27 MAX NOTE 5 3.64 2.94 2.79 2.24 4X (0 -12 ) 2X 0.7 MAX NOTE 5 B 4.5 4.3 A 6.6 6.4 NOTE 3 0.75 0.50 (0.15) TYP PowerPAD TSSOP - 1.2 mm max heightPWP0020W SMALL OUTLINE PACKAGE 4231145/A 08/2024 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may differ or may not be present. TM PowerPAD is a trademark of Texas Instruments. A 15 DETAIL A TYPICAL SCALE 2.300 THERMAL PAD 10 11

www.ti.com EXAMPLE BOARD LAYOUT 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP (3.4) NOTE 9 (6.5) NOTE 9 (1.3) TYP (1.3) TYP ( 0.2) TYP VIA (2.79) (3.64) PowerPAD TSSOP - 1.2 mm max heightPWP0020W SMALL OUTLINE PACKAGE 4231145/A 08/2024 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 10 11 METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP (3.64) BASED ON (2.79) BASED ON PowerPAD TSSOP - 1.2 mm max heightPWP0020W SMALL OUTLINE PACKAGE 4231145/A 08/2024 2.36 X 3.080.175 2.55 X 3.320.15 2.79 X 3.64 (SHOWN)0.125 3.12 X 4.070.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 10 11 METAL COVERED BY SOLDER MASK SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES

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Product Information

LP8869CQPWPRQ1.A specifications and overview.

Summary

LP8867C-Q1, LP8869C-Q1 Low EMI Automotive LED Driver with 4-, 3- Channels AUGUST 2019

Description

LP8867C-Q1, LP8869C-Q1 Low EMI Automotive LED Driver with 4-, 3- Channels AUGUST 2019

Source title LP8869CQPWPRQ1.A Datasheet(PDF) - Texas Instruments

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