Driver IC

LP8868VQDMTRQ1

Texas Instruments

LP8868-Q1 Automotive Multi-Topology LED Driver with Inductive Fast Dimming REVISED NOVEMBER 2023

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LP8868-Q1 Automotive Multi-Topology LED Driver with Inductive Fast Dimming

1 Features

AEC-Q100 Qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA
Integrated MOSFET for buck, buck-boost and boost topology – Wide input voltage: 4.5 V to 65 V – Integrated 5.2-A and 150-mΩ MOSFET – Switching frequency 100 kHz to 2.2 MHz – Spread spectrum for lower EMI
High precision power FET dimming – Up to 4-A output current in buck topology – Analog dimming (dimming ratio 256 :1) – Fast PWM dimming (150-ns pulse width) – Hybrid and flexible dimming
Full protection features: – Fault output – LED open and short protection – Cycle-by-cycle current limit – Switching FET failure protection – Thermal shutdown – Configurable thermal foldback curve

2 Applications

Automotive infotainment
Automotive instrument clusters
Heads-up displays(HUD)
Automotive lighting CSENSE SW CSP CSN OVP FSET TEMP COMP PGND AGND VIN VCC EN/PWM FAULT ADIM/HD LP8868X/U RTEMP RFSET RCOMP RDAMP CCOMP ROVP2 100nF D R SENSE L ROVP1 COUT CVCCCVIN CIN VIN = 9 - 16V X8 LED VCC Typical Boost LED Driver Application Schematic

3 Description

The LP8868-Q1 family is a non-synchronous multi- topology solution with 4.5-V to 65-V wide input range. By integrating the low-side NMOS switch, the device is capable of driving LEDs with high power density and high efficiency. The family also supports common cathode connection and single layer PCB design. The switching frequency is configurable from 100 kHz to

2.2 MHz with an optional spread spectrum feature for

better EMI performance. The LP8868-Q1 family supports four dimming options, including analog, PWM, hybrid and flexible dimming. Each dimming method can be configured through the PWM and ADIM input pins by means of simple high and low signals. The family adopts an adaptive off-time current mode control along with smart and accurate sampling to enable inductive fast dimming (IFD) and achieve high dimming accuracy. The LP8868-Q1 family also provides multiple systematic protections, including LED open and short, sense resistor open and short, configurable thermal foldback and thermal shutdown. Fault output will send out acknowledge signals as soon as any fault condition is detected.

Package Information

PART NUMBER PACKAGE1 BODY SIZE (NOM) LP8868-Q1 VSON (14) 4.5 mm x 3.0 mm HVSSOP (12)2 4 mm x 3.0 mm 1. For all available packages, see the orderable addendum at the end of the data sheet. 2. Product preview V IN (V) Efficiency 8 9 10 11 12 13 14 15 16 60% 65% 70% 75% 80% 85% 90% 95% 100% V out = 8LED, I LED = 1 A Efficiency VS Input Voltage LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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4 Comparison Table

Part Number Topology MOSFET Current Limit (Typical) Spread Spectrum LP8868XQDMTRQ1 Boost 6 A Enabled LP8868YQDMTRQ1 Buck-boost 6 A Enabled LP8868ZQDMTRQ1 Buck 6 A Enabled LP8868UQDMTRQ1 Boost 6 A Disabled LP8868VQDMTRQ1 Buck-boost 6 A Disabled LP8868WQDMTRQ1 Buck 6 A Disabled www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

5 Pin Configuration and Functions

(GND) FSET UVP VCC 7 8 GND GND Figure 5-1. 14-Pin Buck VSON Top View ADIM/ HD EN/ PWM TEMP FSET FAULT VIN SW CSN CSP Thermal Pad (GND) COMP UVP VCC HVSSOP is product preview Figure 5-2. 12-Pin Buck HVSSOP Top View Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION No. NAME 1 PGND G Power ground pin. 2 AGND G Analog ground pin. 3 VIN P Input power pin. 4 VCC P Internal LDO output pin. Connect with a 10-V, 1-uF capacitor to GND. 5 ADIM/HD I Analog dimming or hybrid dimming pin. Pull high for PWM dimming only, pull low for hybrid dimming, input PWM signal for analog dimming. 6 PWM/EN I PWM dimming or EN pin. Pull high for always on, pull low for disabling the device, input PWM signal for PWM dimming. LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION No. NAME 7 FAULT O Open drain output. Pull low when fault is detected. 8 TEMP I/O Thermal foldback pin. Put different resistor values to GND to set different thermal foldback behavior curves. 9 FSET I/O Switching frequency set pin, with range of 100 kHz ~ 2.2 MHz. Put different resistor values to GND for different switching frequencies. 10 COMP I/O Error-amilifier output. Connect capacitors to GND. Different capacitor values determine different softstart times and bandwidths. 11 UVP I Undervoltage detection pin. Put different resistor dividers to set the LED open detection thresholds. 12 CSP I LED current sense positive pin. 13 CSN I LED current sense negative pin. 14 SW P Switching node pin. Internally connected to the low-side MOSFET. Connect with the power inductor and the schottky diode. Pad Thermal Pad G Power ground pin. www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

(GND) FSET OVP VCC 7 8 GND GND Figure 5-3. 14-Pin Boost/Buck-Boost VSON Top View ADIM/ HD EN/ PWM COMP TEMPFAULT VIN SW CSN CSP Thermal Pad (GND) FSET UVP VCC 7 8 GND GND HVSSOP is product preview Figure 5-4. 12-Pin Boost/Buck-Boost HVSSOP Top View Table 5-2. Pin Functions for boost/buck-boost topology PIN TYPE(1) DESCRIPTIONVSON Package NAME 1 PGND G Power ground pin. 2 AGND G Analog ground pin. 3 VIN P Input power pin. 4 VCC P Internal LDO output pin. Connect with a 10-V, 1-uF capacitor to GND. 5 ADIM/HD I Analog dimming or hybrid dimming pin. Pull high for PWM dimming only, pull low for hybrid dimming, input PWM signal for analog dimming. LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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Table 5-2. Pin Functions for boost/buck-boost topology (continued) PIN TYPE(1) DESCRIPTIONVSON Package NAME 6 PWM/EN I PWM dimming or EN pin. Pull high for always on, pull low for disabling the device, input PWM signal for PWM dimming. 7 FAULT O Open drain output. Pull low when fault is detected. 8 TEMP I/O Thermal foldback pin. Put different resistor values to GND to set different thermal foldback behavior curves. 9 FSET I/O Switching frequency set pin, with range of 100 kHz ~ 2.2 MHz. Put different resistor values to GND for different switching frequencies. 10 COMP I/O Error-amilifier output. Connect capacitors to GND. Different capacitor values determine different softstart times and bandwidths. 11 OVP I Overvoltage detection pin. Put different resistor dividers to set the LED open detection thresholds. 12 CSN I LED current sense negative pin. 13 CSP I LED current sense positive pin. 14 SW P Switching node pin. Internally connected to the low-side MOSFET. Connect with the power inductor and the schottky diode. Pad Thermal Pad G Power ground pin. (1) I = Input, O = Output, P = Supply, G = Ground www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage on pins VIN, UVP, OVP, CSP, CSN, SW, –0.3 65 V Voltage on pins VCC, ADIM/HD, EN/PWM, FAULT, TEMP, FSET, COMP –0.3 5.5 V Operation junction temperature TJ –40 125 °C Storage temperature Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted) MIN MAX UNIT Input voltage range VIN 4.5 63 V Input voltage range UVP, OVP, CSP, CSN 0 63 V Input voltage range VCC, ADIM/HD, EN/PWM, TEMP, FSET 0 5 V Output voltage range SW 0 63 V FAULT, COMP 0 5 V Operating junction temperature, TJ –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) Device UNITSON

14 PINS

RθJA Junction-to-ambient thermal resistance 39.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.5 °C/W RθJB Junction-to-board thermal resistance 14.7 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 14.7 °C/W (1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package Thermal Metricsapplication report, SPRA953. LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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6.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of the product containing it. TJ = –40°C to +125°C, VIN = 4.5 V to 60 V, (unlessotherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VVIN_UVLO VIN undervoltage lockout Rising VIN 3.0 3.2 3.4 V Falling VIN 2.8 3.0 3.2 V Hysteresis 0.2 V ISD Shut down current from VIN VIN = 12 V, VEN/PWM = 0 V 0.8 2.3 µA IOFF PWM off current from VIN VIN = 12 V, VEN/PWM = 0 V 2.5 mA IOP Normal operating current 400-kHz switching frequency 4.6 mA IOP Normal operating current 2.2-MHz switching frequency 10.0 mA VVCC Internal LDO output voltage IVCC = 10mA 5.0 5.15 5.3 V IVCC_LIM Internal LDO output current limit 38 47 56 mA DIMMING VPWM_L Low-level input voltage 0.4 V VPWM_H High-level input voltage 1.2 V VADIM_L Low-level input voltage 0.4 V VADIM_H High-level input voltage 1.2 V tPWM_OUT_ON PWM output minimum on time 150 ns tPWM_IN_ON PWM input minimum on time 150 ns tPWM_IN_OFF PWM input minimum off time to disable device 57 77 ms fADIM Analog Dimming input frequency 6-bit ADIM resolution 0.1 156 kHz fADIM Analog Dimming input frequency 8-bit ADIM resolution 0.1 39 kHz FAULT VOL Output level low I = 3mA 0.1 V ILEAKAGE Output leakage current V = 5 V 1 µA FEEDBACK AND ERROR AMPLIFIER gM(ea) Transconductance gain ADIM 100% duty cycle, VCSP-CSN = 200mV, VCOMP = 1.5V 205 265 325 μA/V ICOMP Source/sink current ADIM 100% duty cycle, VCSP-CSN = 200mV ± 200mV, VCOMP = 1.5V ±24 ±40 ±56 µA VCSP-CSN Current sense threshold ADIM 100% duty cycle 194 200 206 mV VCSP-CSN Current sense threshold ADIM 12.5% duty cycle, compared with 100% duty cycle 11.875 12.5 13.125 % VCSP-CSN Current sense threshold ADIM 1.17% duty cycle, compared with 100% duty cycle 0.82 1.17 1.52 % ILEAK_CSP/N CSP+CSN pin leakage current VIN = 60 V, VEN/PWM = 5 V 22 31 µA ILEAK_CSP/N CSP+CSN pin leakage current VIN = 60 V, VEN/PWM = 0 V 10 15 µA POWER STAGE RDSON Switching FET on resistance VIN ≥ 5 V 150 mΩ tmin_ON Switching FET minimum on time 100 ns tmin_OFF Switching FET minimum off time 100 ns fSW Switching FET frequency 0.1 2.2 MHz CURRENT LIMIT ILIM Switching FET cycle-by-cycle current limit (LP8868X/LP8868Y/LP8868U/LP8868V) 5.8 6.5 7.6 A ILIM Switching FET cycle-by-cycle current limit (LP8868Z/LP8868W) 5.2 6 7 A THERMAL PROTECTION Tth Thermal foldback starting temperature threshold RTEMP = 20 kΩ 130 °C www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

6.6 Typical Characteristics

VIN = 12 V, L = 22 µH, FSW = 400 kHz, unless otherwise specified ADIM Duty Cycle (%) Internal Reference Voltage (V) 0 10 20 30 40 50 60 70 80 90 100 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Figure 6-1. ADIM Duty Cycle vs. Reference Voltage in Analog Dimming Junction Temperature (°C) Shutdown Current (uA) -25 0 25 50 75 100 125 Figure 6-2. Shutdown Current vs. Junction Temperature Junction Temperature (°C) LDO Output Voltage (V) -25 0 25 50 75 100 125 5.1 5.12 5.14 5.16 5.18 5.2 Figure 6-3. Internal LDO Output vs. Junction Temperature Junction Temperature (°C) Switching FET R dson (m  ) -25 0 25 50 75 100 125 100 125 150 175 200 225 Figure 6-4. Switching FET Rdson vs. Junction Temperature LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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6.6 Typical Characteristics (continued)

Junction Temperature (°C) V IN UVLO Threshold (V) -25 0 25 50 75 100 125 2.9 3.1 3.2 3.3 3.4 3.5 Rising Threshold Falling Threshold Figure 6-5. VIN UVLO Threshold vs. Junction Temperature Junction Temperature (°C) EN/PWM Threshold (V) -25 0 25 50 75 100 125 0.5 0.6 0.7 0.8 0.9 1.1 Rising Threshold Falling Threshold Figure 6-6. EN/PWM Threshold vs. Junction Temperature Junction Temperature (°C) ADIM/HD Threshold (V) -25 0 25 50 75 100 125 0.5 0.6 0.7 0.8 0.9 1.1 Rising Threshold Falling Threshold Figure 6-7. ADIM/HD Threshold vs. Junction Temperature Brightness Efficiency 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 8LED 10LED Figure 6-8. Efficiency at 1-A Max Output Current with PWM Dimming, 22uH Inductor, Boost Topology Brightness Efficiency 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 3LED 5LED Figure 6-9. Efficiency at 1-A Max Output Current with PWM Dimming, 22uH Inductor, Buck-Boost Topology Brightness Efficiency 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1LED 2LED 3LED Figure 6-10. Efficiency at 3-A Max Output Current with PWM Dimming, 22uH Inductor, Buck Topology www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

70% 73% 76% 79% 82% 85% 88% 91% 94% 97% 100% 8LED 10LED Figure 6-11. Efficiency at 1-A Max Output Current with Analogy Dimming, 22uH Inductor, Boost Topology Brightness Efficiency 70% 73% 76% 79% 82% 85% 88% 91% 94% 97% 100% 3LED 5LED Figure 6-12. Efficiency at 1-A Max Output Current with Analogy Dimming, 22uH Inductor, Buck-Boost Topology Brightness Efficiency 70% 73% 76% 79% 82% 85% 88% 91% 94% 97% 100% 1LED 2LED 3LED Figure 6-13. Efficiency at 3-A Max Output Current with Analogy Dimming, 22uH Inductor, Buck Topology LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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7 Detailed Description

7.1 Overview

The LP8868-Q1 family is a 4-A non-synchronous Buck / Boost / Buck-Boost LED driver with 4.5-V to 65-V wide input range. By integrating the low-side NMOS switch with constant current and constant voltage controls, the device is capable of not only driving LEDs but also charging batteries with high power density and high efficiency. The switching frequency is configurable through FSET pin, ranging from 100 kHz to 2.2 MHz, with optional spread spectrum feature to decrease the EMC emission and reduce the input filter size. The device supports four dimming options, including analog dimming, PWM dimming, hybrid dimming and flexible dimming. Each dimming method can be configured through the PWM and ADIM input pins by means of simple high/low sequensing signals at startup. The device adopts an adaptive off-time current mode control along with smart and accurate sampling to enable inductive fast dimming (IFD) and achieve high dimming ratio. The compensation bandwidth can be adjusted through an external capacitor on COMP pin based on system requirement. The LP8868-Q1 family has extensive fault detection feature:

LED open and short detection
Sense resistor open and short detection
Configurable thermal foldback and thermal shutdown protection Fault condition is indicated through the FAULT output pin.

7.2 Functional Block Diagram

R Q LDO Dimming Logic Thermal Foldback _ +_ PWM Reference Voltage UVP / OVP www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

7.3 Feature Description

7.3.1 Adaptive Off-Time Current Mode Control

The LP8868-Q1 family adopts an adaptive off-time current mode control to support fast transient response over a wide range of operation. The switching frequency is configurable through FSET pin, ranging from 100 kHz to 2.2 MHz. For average output current regulation, the sensed voltage across the sensing resistor between the CSP and CSN pins is compared with the internal voltage reference, V REF , through the error amplifier. The output of the error amplifier, VCOMP, passes through an external compensation network and is then compared with the peak current feedback at the PWM comparator During each switching cycle, when the internal N-MOSFET is turned on, the peak currernt is sensed through the internal FET. When the sensed value of peak current reaches VCOMP at the input of PWM comparator, the N-MOSFET is turned off and the adaptive off-time counter starts counting. Once the adaptive off-time counter stops counting, the counter keeps reset until when the N-MOSFET turns off. The counting off time is determined by the external resistor connected to the FSET pin and the input/output feedforward. Thus, the device is able to maintain a nearly constant switching frequnecy at steady state and regulate the output average current at a desired value. Adaptive OFF Adaptive OFF EA Triggers MOSFET OFF VCOMP IL X Rdson V t Figure 7-1. Adaptive off-time current mode control method LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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7.3.1.1 Switching Frequency Settings

The switching frequency of LP8868 family is adjustable from 100 kHz to 2.2 MHz by means of changing R FSET connected between FSET pin and AGND. The default switching frequency is 100 kHz when the FSET pin is connected to nothing. The resistor value and the corresponding switching frequency are listed in the below table: Table 7-1. Switching Frequency vs. RFSET resistor value Switching Frequency Resistor Value (kΩ) 100 kHz 232 200 kHz 138 300 kHz 83 400 kHz 59 600 kHz 38 800 kHz 28

1 MHz 23

1.2 MHz 18

1.5 MHz 13

1.8 MHz 11

2.2 MHz 9

For example, if RFSET is set to 59 kΩ, the corresponding switching frequency is 400 kHz. In most cases, lower switching frequency has higher system efficiency and better thermal performance.

7.3.1.2 Spread Spectrum

The LP8868X/Y/Z-Q1 enables the spread spectrum feature (±7% from central frequency, 2-kHz modulation frequency) which reduces EMI noise at the switching frequency and its harmonic frequencies. On the other hand, the LP8868U/V/W-Q1 disables the spread spectrum feature toward better brightness performance in low brightness scenario.

7.3.2 Setting LED Current

The output current of the LED is controlled with external resistor R sense between CSP and CSN pins. R sense value for the target current can be calculated using equation Equation 1 . Noted that, to relised IFD function and improve the accuracy of the output current in low duty cycle, the capacitor in parallel with sense resistor is required for boost and buck-boost topology. And it is optional for buck topology. R SE NS E = V RE F I L ED _ FS (1) where

VREF = 200 mV
RSENSE is current setting resistor, mΩ
ILED is output current, mA For example, if Rsense is set to 100 mΩ. ILED will be 2 A. www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

7.3.3 Internal Soft Start

The LP8868-Q1 family implements the internal soft-start function. Once V IN rises above V VIN_MIN, the internal LDO starts to charge V CC capacitor. It takes approximately 800 μs for V CC to rise above V VIN_UVLO if a 1- μF capacitor is connected to V CC pin. If EN/PWM pin is pulled high before V CC rises above V VIN_UVLO, the POR is enabled right after V CC above V VIN_UVLO and waits for 100 μs to start dimming mode. EN/PWM pin has to stay high for more than 5 μs after V CC rises above V VIN_UVLO. In this case, if using 1- μF V CC capacitor, it is recommended to wait for 1 ms to start dimming mode after VIN rises above VVIN_MIN. If EN/PWM pin has the first PWM pulse appearing after V CC rises above V VIN_UVLO, the device waits for 200 μs to enable POR and another 100 μs to start dimming mode. Hence, without triggering V IN UVLO, the device can be renabled after disabled and waits for 300 μs to start dimming mode. Note that the initial enable PWM pulse lasting more than 5 μs is required at EN/PWM input pin to enable the device. After dimming mode is started, the device enters four different dimming modes based on the configuration of ADIM/HD pin and EN/PWM pin. VIN VCC EN POR Dimming Mode Start VVIN_MIN VVIN_UVLO 100 s VIN VCC EN POR VVIN_UVLO 200 s 100 s EN High Before VCC > VVIN_UVLO >5 s EN High After VCC > VVIN_UVLO Dimming Mode Start >5 s VVIN_MIN Figure 7-2. Startup Sequence LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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7.3.4 Dimming Mode

The LP8868 family has four optional dimming modes determined by the waveform in PWM and ADIM pins. The dimming mode is started either 1 ms after VIN exits UVLO or 300 μs after renable by EN/PWM pin. The configuration to one of the four dimming modes are shown as below. Table 7-2. Dimming Mode Configuration Dimming Mode EN/PWM Pin ADIM/HD Pin PWM Dimming PWM signal High Analog Dimming High PWM signal Hybrid Dimming PWM signal Low Flexible Dimming PWM signal PWM signal

7.3.4.1 PWM dimming

The PWM dimming mode is enabled when the ADIM/HD input pin is always high and the PWM/EN input pin is configured by a PWM input signal. Device supports PWM input signals with ultra-narrow pulse width down to 200 ns in PWM dimming mode. The PWM output duty cycle can be changed in the opposite direction only when PWM input duty cycle changes by more than 0.38%. In PWM dimming mode, when the PWM input signal at the PWM pin turns from low to high, the internal NMOS FET starts switching and the inductor current rises to the determined value. The LED current is then regulated at the determined value as long as the PWM input signal stays high. When the PWM input signal turns from high to low, the internal FET is turned off causing the inductor current falling to zero. The internal FET maintains off and the LED current stays zero if the PWM input signal stays low.

7.3.4.2 Analog dimming

The LP8868 family supports analog dimming which regulates the LED current through the ADIM/HD pin. The analog dimming mode is enabled when the PWM/EN pin is always high and the ADIM/HD pin is configured by a PWM input signal. And the internal digital circuits is able to respond to the duty cycle change of the PWM input signal with tens of micro-seconds delay The internal voltage reference, V REF, changes in proportion to the duty cycle of the PWM input signal at the ADIM/HD pin. V REF is 200 mV when the PWM input signal at the ADIM/HD pin has a 100% duty cycle, for instance, and VREF is 20 mV when the PWM input signal has a 10% duty cycle. www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

7.3.4.3 Hybrid Dimming

The LP8868 family supports a unique hybid dimming function to maximize the dimming performance, especially when both high dimming frequency and high dimming ratio are needed. The hybrid dimming mode is enabled when the ADIM/HD pin is always low and the PWM/EN pin is configured by a PWM input signal. When the hybrid dimming is enabled, the LED current is regulated by the analog dimming at high brightness level (12.5% - 100%) and by the PWM dimming at low brightness level (0% - 12.5%), respectively. At high brightness level, the internal voltage reference, V REF, changes in proportion to the duty cycle of the PWM input signal at the PWM/EN pin. At low brightness level, V REF stays unchanged and an internal PWM generator is enabled. Thus, the LED is turned on and off corresponding to the on and off of the internal PWM signal of which the frequency and the duty cycle are configured by the PWM input signal at the PWM/EN pin. The detailed hybrid dimming behavior is illustrated in the below figure. TON TPWM PWM Input 100% ILED D=6.25% D=50% 75% 50% 25% D=25% Hybrid Mode D=3.125% ILED 12.5% Figure 7-3. Hybrid Dimming

7.3.4.4 Flexible Dimming

The LP8868 family also supports flexible dimming to maximize the flexibility of dimming control, in which the LED current value and the on/off behavior can be controlled independently. The flexible dimming mode is enabled when both the ADIM/HD pin and the PWM/EN pin are configured by PWM input signals at the same time. Therefore, in flexible dimming mode, the LED is turned on and off corresponding to the on and off of the PWM input signal at the PWM/EN pin while the reference voltage changes in proportion to the duty cycle of the PWM input signal at the ADIM/HD pin.

7.3.5 Undervoltage Lockout

The LP8868 family implements an internal undervoltage-lockout (UVLO) circuitry connecting to the VCC pin. The UVLO is triggered and then device is disabled when the VCC pin voltage falls below the internal UVLO threshold voltage, V VCC_UVLO typically 3.0 V, with a typical 0.2-V hysteresis. The VCC pin is the output of an internal regulator of which the input is supplied by the VIN pin. Therefore, if VIN pin voltage falls close to above the VVCC_UVLO (around 500 mV above), the UVLO will be triggered. LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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7.3.6 Fault Protection

The LP8868 family is able to provide fault protections and send fault report signals in many fault conditions, including LED open, LED short to GND, sense resistor open and short, internal switching FET fault and thermal shutdown. The fault criterion for different topology is shown in below. Table 7-3. Protections in Buck topology TYPE CRITERION BEHAVIOR LED open load VUVP < 1.2 V for 100us Fault pin pulls low. The device stops switching when VUVP < 1.2 V. LED+ and LED- short circuit VIN - VCSP < 300 mV for 30ms Fault pin pulls low. The keeps normal behavior. LED- short to GND VUVP < 1.2 V for 100us Fault pin pulls low. The device stops switching and recovers when fault is removed. Sense-resistor open load VCSP - VCSN > 300mV for 20us Fault pin pulls low. The device stops switching and recovers when fault is removed. Sense-resistor short circuit Error Amplifer output high for 100us Fault pin pulls low. The device keeps switching under the cycle-by-cycle current limit. Switching FET open Error Amplifer output high for 100us Fault pin pulls low. The device keeps maximum duty cycle turn-on switching. Switching FET short VCSP - VCSN > 300 mV for 20us Fault pin pulls low. The device stops switching and recovers when fault is removed. Thermal shutdown TJ > TTSD for 100us Fault pin pulls low. The device stops switching when TJ>TTSD, and is re-activated when TJ falls below the hysteresis level. VIN UVLO VCC < 3 V Fault pin pulls low. The device stops switching and recovers when fault is removed. Table 7-4. Protections in Boost / Buck-Boost topology TYPE CRITERION BEHAVIOR LED open load VOVP > 1.2 V for 100us Fault pin pulls low. The device stops switching when VOVP > 1.2 V. LED+ and LED- short circuit (Buck- Boost) VCSP - VIN < 300mV for 30ms Fault pin pulls low. The device keeps normal behavior. LED+ short to GND CSP - VCSN > 300mV for 20us Fault pin pulls low. The device stops switching and recovers when fault is removed. Sense-resistor open load VCSP - VCSN > 300mV for 20us Fault pin pulls low. The device stops switching and recovers when fault is removed. Sense-resistor short circuit Error Amplifer output high for 100us Fault pin pulls low. The device keeps switching under the cycle-by-cycle current limit. Switching FET open Error Amplifer output high for 100us Fault pin pulls low. The device keeps maximum duty cycle turn-on switching. Switching FET short Error Amplifer output high for 100us Fault pin pulls low. The device tries to keep switching. Thermal shutdown TJ > TTSD for 100us Fault pin pulls low. The device stops switching when TJ>TTSD, and is re-activated when TJ falls below the hysteresis level. VIN UVLO VCC < 3 V Fault pin pulls low. The device stops switching and recovers when fault is removed. www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

7.3.7 Thermal Foldback

The LP8868 family integrates thermal shutdown protection to prevent the device from overheating. In order to provide design margin of system thermal performance, the device enables a programmable thermal foldback function which automatically reduces the full-scale output current, I FS, at high junction temperature. When the device along with the LEDs are mounted on the same thermal substrate, the thermal performance is effectively improved due to the reduction of dissipation need for both and LED. As the junction temperature rises above the thermal foldback threshold temperature, T th, the full-scale current starts to reduce following the current-temperature curve shown in the below figure. The current starts to reduce from the 100% level at typically rate of 2% of I FS per °C until it drops to 50% of the full scale. Once the junction temperature rises 25°C above the T th, the current continues to decrease at a lower rate until the temperature reaches above the overtemperature shutdown threshold temperature, TTSD. Full-Scale Current TTSDTth IFS 50% 2% decrease of IFS per ºC Tth + 25°C 100% Figure 7-4. Thermal Foldback The Tth can be adjusted by changing the resistor R TEMP connected between the TEMP and GND pin. The T th and the corresponding RTEMP value are listed in below table. Table 7-5. Tth vs. RTEMP resistor value Tth (°C) Resistor Value (kΩ) 80 200 90 100 100 60 110 40 120 28 130 20 140 15 150 10 LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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8 Application and Implementation

8.1 Application Information

LP8868 family can support buck / boost / buck-boost topology with different part number. The LP8868X is typically used as a boost converter, the LP8868Y is typically used as a buck-boost converter and the LP8868Z is typically used as a buck converter.

8.2 Typical Application

8.2.1 LP8868XQDMTRQ1 12-V Input, 1-A Output, 8-piece LED With Boost Topology

Figure 8-1 shows a typical application for the LP8868X in a boost topology. The switching current limit is 5.8 A and it will limit the output current. CSENSE SW CSP CSN OVP FSET TEMP COMP PGND AGND VIN VCC EN/PWM FAULT ADIM/HD LP8868X/U RTEMP RFSET RCOMP RDAMP CCOMP ROVP2 100nF D R SENSE L ROVP1 COUT CVCCCVIN CIN VIN = 9 - 16V X8 LED VCC Figure 8-1. Typical Application for Boost Topology with LP8868X

8.2.1.1 Design Requirements

For this design example, use the parameters in the following table. Table 8-1. Design Parameters PARAMETER VALUE Input voltage range 9 V -16 V LED string 8 LED Output voltage 24 V Switching frequency 400 kHz Maximum LED current 1 A Inductor current ripple 40% of maximum inductor current Dimming type PWM dimming/ADIM dimming www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Inductor Selection

For this design, the input voltage is 9 V to 16 V. The output is 8 white LEDs in series and the inductor current ripple by requirement is less than 40% of maximum LED current. To choose a proper peak-to-peak inductor current ripple, the low-side FET current limit should not be violated when the converter works in no-load condition. This requires half of the peak-to-peak inductor current ripple to be lower than that limit. Another consideration is to ensure reasonable inductor core loss and copper loss caused by the peak-to-peak current ripple. Once this peak-to-peak inductor current ripple is chosen, use Equation 2 to calculate the recommended value of the inductor L. L = V I N m ax × V OU T − V IN max V OU T × K I N D × I L ma x × f SW (2) where

KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum LED current.
IL(max) is the maximum inductor current.
fSW is the switching frequency.
VIN(max) is the maximum input voltage.
VOUT is the sum of the voltage across LED load and the voltage across sense resistor. With the chosen inductor value, the user can calculate the actual inductor current ripple using Equation 3. I L ri p pl e = V IN max × V O UT − V I N max V O U T × L × f S W (3) The design ratings of inductor RMS current and saturation current must be greater than those seen in the system requirement. This is to ensure no inductor overheat or saturation occurring. During power up, transient conditions or fault conditions, the inductor current may exceed its normal operating current and reach the current limit. Therefore, it is preferred to select a saturation current rating equal to or greater than the converter current limit. The peak-inductor-current and RMS current equations are shown in Equation 4 and Equation 5. I L peak = I L m ax + I L r i p pl e 2 (4) I L rm s = I L max 2 + I L ri p pl e 2 2 (5) In this design, V IN(max) = 16V, V OUT = 24 V, I LED = 1 A, considering the efficiency as 0.9, I L(max) = 2.96 A, fSW = 400 kHz, choose K IND = 0.4, the calculated inductance is 11.25 µH. A 10-µH inductor is chosen. With this inductor, the ripple, peak, and rms currents of the inductor are 1.212 A, 3.569 A, 3.084 A, respectively.

8.2.1.2.2 Input Capacitor Selection

An input capacitor is required to reduce the surge current drawn from the input supply and the switching noise coming from the device. Electrolytic capacitors are recommended for energy storage. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, it is recommended to place a 10- μF ceramic capacitor along with a 0.1-µF capacitor from VIN to PGND/AGND to provide high-frequency filtering. The input capacitor voltage rating must be greater than the maximum input voltage. Use Equation 6 to calculate the input ripple voltage, where ESR CIN is the ESR of input capacitor, and KDR is the derating coefficient of ceramic capacitance at the applied DC voltage. V I N ri p pl e = I L ri p pl e 8 × C I N × f SW (6) LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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In this design, a 33-µF, 100V electrolytic capacitor, a 1-µF, 100V X7R ceramic capacitor and a 0.1-µF, 100V X7R ceramic capacitor are chosen, yielding around 100-mV input ripple voltage.

8.2.1.2.3 Output Capacitor Selection

The output capacitor reduces the high-frequency current ripple through the LED string. Excessive current ripple increases the RMS current in the LED string, therefore increasing the LED temperature. 1. Calculate the total dynamic resistance of the LED string (RLED) using the LED manufacturer's datasheet. 2. Calculate the required impedance of the output capacitor (Z OUT) given the acceptable peak-to-peak ripple current through the LED string, I LED(ripple) . IL(ripple) is the peak-to-peak inductor ripple current as calculated with the selected inductor. 3. Calculate the minimum effective output capacitance required. 4. Increase the output capacitance appropriately due to the derating effect of applied DC voltage. See Equation 7, Equation 8, and Equation 9. R LE D = ∆ V F ∆ I F × # o f L ED s (7) Z C OU T = R LE D × I LE D r i pp l e I L max − I L ED ri p p l e (8) C CO U T = 1 2 π × f S W × Z CO U T (9) Once the output capacitor is chosen, Equation 10 can be used to estimate the peak-to-peak ripple current through the LED string. I L ED ri p pl e = Z C OU T × I L r ip p l e Z C OU T + R L ED (10) Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. In this design, a 10-µF, 50-V X7R ceramic capacitor is chosen.

8.2.1.2.4 Sense Resistor Selection

The maximum LED current is 1 A at 100% PWM duty and the corresponding VREF is 200 mV. By using Equation 11, the sense resistance is calculated as 200 mΩ. Note that the power consumption of the sense resistor is 200 mW, requiring enough margin of the resistor's power rating in selection. R SE NS E = V RE F I L ED _ FS (11) In boost topology, CSENSE is required to achieve the IFD control. Using Equation 12, a 10-µF, 50-V X7R ceramic capacitor is chosen for CSENSE to suppress the ac magnitude of sense feedback less than 200 mV. C SEN SE = 0.25 × I L max 200 mV × f SW (12)

8.2.1.2.5 Other External Components Selection

In this design, a 0.1-µF, 50-V X7R ceramic capacitor is chosen for high-frequency filtering of sense feedback. For loop stability, it is recommended to select a 1-nF, 10-V X7R ceramic capacitor for C COMP and a 1-kΩ resistor for RCOMP. A 1-MΩ resistor is chosen for RDAMP to suppress the overshoot current at rising edge of PWM on. www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

8.2.1.3 Application Curves

Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Ripple (AC) Figure 8-2. LED Current Ripple at ADIM = 100%, 1 kHz and FSW = 400 kHz Ch 1: PWM/EN, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-3. LED Current Ripple at PWM = 50%, 20 kHz and FSW = 400 kHz Ch 1: PWM/EN, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-4. LED Current Transient for a PWM Transition from 10% to 99%, 4 kHz Ch 1: ADIM, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-5. Startup at ADIM = 100%, 500Hz LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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8.2.2 LP8868YQDMTRQ1 12-V Input, 1-A Output, 5-piece LED With Buck-Boost Topology

Figure 8-8 shows a typical application for the LP8868Y in a buck-boost topology. The switching current limit is 5.8 A and it will limit the output current. CSENSE SW CSP CSN OVP FSET TEMP COMP PGND AGND VIN VCC EN/PWM FAULT ADIM/HD LP8868Y/V RTEMP RFSET RCOMP RDAMP CCOMP ROVP2 100nF D R SENSE L ROVP1 COUTCVCCCVIN CIN VIN = 9 - 16V X5 LED VCC Figure 8-8. Typical Application for Buck-Boost Topology with LP8868Y

8.2.2.1 Design Requirements

For this design example, use the parameters in the following table. Table 8-2. Design Parameters PARAMETER VALUE Input voltage range 9 V -16 V LED string 5 LED Output voltage 15 V Switching frequency 400 kHz Maximum LED current 1 A Inductor current ripple 40% of maximum inductor current Dimming type PWM dimming/ADIM dimming LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Inductor Selection

For this design, the input voltage is 9 V to 16 V. The output is 8 white LEDs in series and the inductor current ripple by requirement is less than 40% of maximum LED current. To choose a proper peak-to-peak inductor current ripple, the low-side FET current limit should not be violated when the converter works in no-load condition. This requires half of the peak-to-peak inductor current ripple to be lower than that limit. Another consideration is to ensure reasonable inductor core loss and copper loss caused by the peak-to-peak current ripple. Once this peak-to-peak inductor current ripple is chosen, use Equation 13 to calculate the recommended value of the inductor L. L = V I N m ax × V O UT V OU T + V I N ma x × K I ND × I L max × f S W (13) where

KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum LED current.
IL(max) is the maximum inductor current.
fSW is the switching frequency.
VIN(max) is the maximum input voltage.
VOUT is the sum of the voltage across LED load and the voltage across sense resistor. With the chosen inductor value, the user can calculate the actual inductor current ripple using Equation 14. I L ri p pl e = V I N max × V OU T V O U T + V I N max × L × f SW (14) The design ratings of inductor RMS current and saturation current must be greater than those seen in the system requirement. This is to ensure no inductor overheat or saturation occurring. During power up, transient conditions or fault conditions, the inductor current may exceed its normal operating current and reach the current limit. Therefore, it is preferred to select a saturation current rating equal to or greater than the converter current limit. The peak-inductor-current and RMS current equations are shown in Equation 15 and Equation 16. I L peak = I L m ax + I L r i p pl e 2 (15) I L rm s = I L max 2 + I L ri p pl e 2 2 (16) In this design, V IN(max) = 16V, V OUT = 15 V, I LED = 1 A, considering the efficiency as 0.8, I L(max) = 2.083 A, fSW = 400 kHz, choose K IND = 0.4, the calculated inductance is 23.22 µH. A 22-µH inductor is chosen. With this inductor, the ripple, peak, and rms currents of the inductor are 1.09 A, 2.629 A, 2.222 A, respectively.

8.2.2.2.2 Input Capacitor Selection

An input capacitor is required to reduce the surge current drawn from the input supply and the switching noise coming from the device. Electrolytic capacitors are recommended for energy storage. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, it is recommended to place a 10- μF capacitor along with a 0.1-µF capacitor from VIN to PGND/AGND to provide high-frequency filtering. The input capacitor voltage rating must be greater than the maximum input voltage. Use Equation 17 to calculate the input ripple voltage, where ESR CIN is the ESR of input capacitor, and KDR is the derating coefficient of ceramic capacitance at the applied DC voltage. V I N ri p pl e = I L max × V OU T K DR × C I N × f SW × V I N m ax + V OU T + E SR C I N (17) www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

In this design, a 10-µF, 100V electrolytic capacitor, a 2.2-µF, 100V X7R ceramic capacitor and a 0.1-µF, 100V X7R ceramic capacitor are chosen, yielding around 504-mV input ripple voltage.

8.2.2.2.3 Output Capacitor Selection

The output capacitor reduces the high-frequency current ripple through the LED string. Excessive current ripple increases the RMS current in the LED string, therefore increasing the LED temperature. 1. Calculate the total dynamic resistance of the LED string (RLED) using the LED manufacturer's datasheet. 2. Calculate the required impedance of the output capacitor (Z OUT) given the acceptable peak-to-peak ripple current through the LED string, I LED(ripple), IL(ripple) is the peak-to-peak inductor ripple current as calculated with the selected inductor. 3. Calculate the minimum effective output capacitance required. 4. Increase the output capacitance appropriately due to the derating effect of applied DC voltage. See Equation 18, Equation 19, and Equation 20. R LE D = ∆ V F ∆ I F × # o f L ED s (18) Z C OU T = R LE D × I LE D r i pp l e I L max − I L ED ri p p l e (19) C CO U T = 1 2 π × f S W × Z CO U T (20) Once the output capacitor is chosen, Equation 21 can be used to estimate the peak-to-peak ripple current through the LED string. I L ED ri p pl e = Z C OU T × I L r ip p l e Z C OU T + R L ED (21) Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. In this design, a 10-µF, 50-V X7R ceramic capacitor is chosen.

8.2.2.2.4 Sense Resistor Selection

The maximum LED current is 1 A at 100% PWM duty and the corresponding VREF is 200 mV. By using Equation 22, the sense resistance is calculated as 200 mΩ. Note that the power consumption of the sense resistor is 200 mW, requiring enough margin of the resistor's power rating in selection. R SE NS E = V RE F I L ED _ FS (22) In buck-boost topology, C SENSE is required to achieve the IFD control. Using Equation 23, a 10-µF, 50-V X7R ceramic capacitor is chosen for CSENSE to suppress the ac magnitude of sense feedback less than 200 mV. C SEN SE = 0.25 × I L max 200 mV × f SW (23)

8.2.2.2.5 Other External Components Selection

In this design, a 0.1-µF, 50-V X7R ceramic capacitor is chosen for high-frequency filtering of sense feedback. For loop stability, it is recommended to select a 1-nF, 10-V X7R ceramic capacitor for C COMP and a 1-kΩ resistor for RCOMP. A 1-MΩ resistor is chosen for RDAMP to suppress the overshoot current at rising edge of PWM on. LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

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8.2.2.3 Application Curves

Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Ripple (AC) Figure 8-9. LED Current Ripple at ADIM = 100%, 1 kHz and FSW = 400 kHz Ch 1: PWM/EN, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-10. LED Current Ripple at PWM = 50%, 20 kHz and FSW = 400 kHz Ch 1: PWM/EN, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-11. LED Current Transient for a PWM Transition from 10% to 99%, 4 kHz Ch 1: ADIM, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-12. Startup at ADIM = 100%, 500Hz www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

Ch 1: PWM/EN, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-13. Shutdown at PWM = 1%, 4kHz Ch 1: ADIM, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-14. Shutdown at ADIM = 100%, 500 Hz LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

8.2.3 LP8868ZQDMTRQ1 12-V Input, 2-A Output, 1-piece LED With Buck Topology

Figure 8-15 shows a typical application for the LP8868Z in a buck topology. The switching current limit is 5.2 A and the output current limit is equal to the limit of switching current limit. SW CSN CSP UVP FSET TEMP COMP PGND AGND VIN VCC EN/PWM FAULT ADIM/HD LP8868Z/W RTEMP RFSET RCOMP RDAMP CCOMP RUVP2 100nF D RSENSEL RUVP1 COUT CVCCCVIN CIN VIN = 9 - 16V X1 LED VCC Figure 8-15. Typical Application for Buck Topology with LP8868Z

8.2.3.1 Design Requirements

For this design example, use the parameters in the following table. Table 8-3. Design Parameters PARAMETER VALUE Input voltage range 9 V -16 V LED string 1 LED Output voltage 3 V Switching frequency 400 kHz Maximum LED current 2 A Inductor current ripple 40% of maximum inductor current Dimming type PWM dimming/ADIM dimming www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

8.2.3.2 Detailed Design Procedure

8.2.3.2.1 Inductor Selection

For this design, the input voltage is 9V to 16V. The output is single white LED and the inductor current ripple by requirement is less than 40% of maximum LED current. To choose a proper peak-to-peak inductor current ripple, the low-side FET current limit should not be violated when the converter works in no-load condition. This requires half of the peak-to-peak inductor current ripple to be lower than that limit. Another consideration is to ensure reasonable inductor core loss and copper loss caused by the peak-to-peak current ripple. Once this peak-to-peak inductor current ripple is chosen, use Equation 24 to calculate the recommended value of the inductor L. L = V O U T × V I N m ax − V OU T V I N m ax × K I N D × I L max × f SW (24) where

KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum LED current.
IL(max) is the maximum LED current.
fSW is the switching frequency.
VIN(max) is the maximum input voltage.
VOUT is the sum of the voltage across LED load and the voltage across sense resistor. With the chosen inductor value, the user can calculate the actual inductor current ripple using Equation 25. I L ri p pl e = V OU T × V IN max − V OU T V I N ma x × L × f S W (25) The design ratings of inductor RMS current and saturation current must be greater than those seen in the system requirement. This is to ensure no inductor overheat or saturation occurring. During power up, transient conditions or fault conditions, the inductor current may exceed its normal operating current and reach the current limit. Therefore, it is preferred to select a saturation current rating equal to or greater than the converter current limit. The peak-inductor-current and RMS current equations are shown in Equation 26and Equation 27. I L peak = I L m ax + I L r i p pl e 2 (26) I L rm s = I L max 2 + I L ri p pl e 2 2 (27) In this design, VIN(max) = 16V, VOUT = 3 V, ILED = 2 A, considering the efficiency as 0.9, IL(max) = 0.741 A, fSW = 400 kHz, choose KIND = 0.4, the calculated inductance is 20.57 µH. A 22-µH inductor is chosen. With this inductor, the ripple, peak, and rms currents of the inductor are 0.277 A, 0.879 A, 0.766 A, respectively.

8.2.3.2.2 Input Capacitor Selection

An input capacitor is required to reduce the surge current drawn from the input supply and the switching noise coming from the device. Electrolytic capacitors are recommended for energy storage. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, it is recommended to place a 10- μF capacitor along with a 0.1-µF capacitor from VIN to PGND/AGND to provide high-frequency filtering. The input capacitor voltage rating must be greater than the maximum input voltage. Use Equation 28 to calculate the input ripple voltage, where ESR CIN is the ESR of input capacitor, and KDR is the derating coefficient of ceramic capacitance at the applied DC voltage. V I N ri p pl e = I L max × V OU T K D R × C I N × f S W × V I N m ax + ES R C I N (28) LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

In this design, a 33-µF, 100V electrolytic capacitor, a 2.2-µF, 100V X7R ceramic capacitor and a 0.1-µF, 100V X7R ceramic capacitor are chosen, yielding around 70-mV input ripple voltage.

8.2.3.2.3 Output Capacitor Selection

The output capacitor reduces the high-frequency current ripple through the LED string. Excessive current ripple increases the RMS current in the LED string, therefore increasing the LED temperature. 1. Calculate the total dynamic resistance of the LED string (RLED) using the LED manufacturer's datasheet. 2. Calculate the required impedance of the output capacitor (Z OUT) given the acceptable peak-to-peak ripple current through the LED string, I LED(ripple) . IL(ripple) is the peak-to-peak inductor ripple current as calculated with the selected inductor. 3. Calculate the minimum effective output capacitance required. 4. Increase the output capacitance appropriately due to the derating effect of applied DC voltage. See Equation 29, Equation 30, and Equation 31. R LE D = ∆ V F ∆ I F × # o f L ED s (29) Z C OU T = R LE D × I LE D r i pp l e I L max − I L ED ri p p l e (30) C CO U T = 1 2 π × f S W × Z CO U T (31) Once the output capacitor is chosen, Equation 32 can be used to estimate the peak-to-peak ripple current through the LED string. I L ED ri p pl e = Z C OU T × I L r ip p l e Z C OU T + R L ED (32) Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. In this design, a 10-µF, 35-V X7R ceramic capacitor is chosen.

8.2.3.2.4 Sense Resistor Selection

The maximum LED current is 2 A at 100% PWM duty and the corresponding VREF is 200 mV. By using Equation 33, the sense resistance is calculated as 100 mΩ. Note that the power consumption of the sense resistor is 400 mW, requiring enough margin of the resistor's power rating in selection. R SE NS E = V RE F I L ED _ FS (33) In buck topology, Csense is optional to use,

8.2.3.2.5 Other External Components Selection

In this design, a 0.1-µF, 50-V X7R ceramic capacitor is chosen for high-frequency filtering of sense feedback. For loop stability, it is recommended to select a 1-nF, 10-V X7R ceramic capacitor for C COMP and a 1-kΩ resistor for RCOMP. A 1-MΩ resistor is chosen for RDAMP to suppress the overshoot current at rising edge of PWM on. www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

8.2.3.3 Application Curves

Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Ripple (AC) Figure 8-16. LED Current Ripple at ADIM = 100%, 1 kHz and FSW = 400 kHz Ch 1: PWM/EN, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-17. LED Current Ripple at PWM = 50%, 20 kHz and FSW = 400 kHz Ch 1: PWM/EN, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-18. LED Current Transient for a PWM Transition from 10% to 99%, 4 kHz Ch 1: ADIM, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-19. Startup at ADIM = 100%, 500Hz LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

Ch 1: PWM/EN, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-20. Shutdown at PWM = 1%, 4kHz Ch 1: ADIM, Ch 2: SW, Ch 3: Inductor Current, Ch 4: LED Current Figure 8-21. Shutdown at ADIM = 100%, 500 Hz

8.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply ranging between 4.5 V and 65 V. This input supply must be well regulated. The device requires an input capacitor to reduce the surge current drawn from the input supply and the switching noise from the device. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 10-μF capacitor is enough.

8.4 Layout

The LP8868-Q1 family requires a proper layout for optimal performance. The following section gives some guidelines to ensure a proper layout.

8.4.1 Layout Guidelines

Examples of a proper layout for boost topolgy, buck-boost topology and buck topology of LP8868 family is shown below.

Creating a large GND plane for good electrical and thermal performance is important.
The IN and GND traces should be as wide as possible to reduce trace impedance. Wide traces have the additional advantage of providing excellent heat dissipation.
Thermal vias can be used to connect the top-side GND plane to additional printed-circuit board (PCB) layers for heat dissipation and grounding.
The input capacitors must be located as close as possible to the IN pin and the GND pin.
The VCC capacitor should be placed as close as possible to VCC pin to ensure stable LDO output voltage.
The SW trace must be kept as short as possible to reduce parasitic inductance and thereby reduce transient voltage spikes. Short SW trace also reduces radiated noise and EMI.
Do not allow switching current to flow under the device.
The routing of CSN and CSP traces are recommended to be in parallel and kept as short as possible and placed away from the high-voltage switching trace and the ground shield.
The compensation capacitor must be placed as close as possible to COMP pin so as to prevent oscillation and system instability. www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

8.4.2 Layout Example

Figure 8-22. Boost Topology Top View Layout Example VLED-VIN GND CSN OVP FSET TEMP COMP VIN VCC EN/PWM FAULT ADIM/HD SW1 PGND AGND Figure 8-23. Buck-Boost Topology Top View Layout Example LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

Figure 8-24. Buck Topology Top View Layout Example www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Changes from Revision * (July 2023) to Revision A (November 2023) Page LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 www.ti.com

Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most- current data available for the designated s. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. www.ti.com LP8868U-Q1, LP8868V-Q1, LP8868W-Q1, LP8868X-Q1, LP8868Y-Q1, LP8868Z-Q1 SLVSH98A – JULY 2023 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LP8868U-Q1 LP8868V-Q1 LP8868W-Q1 LP8868X-Q1 LP8868Y-Q1 LP8868Z-Q1

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated

Product Information

LP8868VQDMTRQ1 specifications and overview.

Summary

LP8868-Q1 Automotive Multi-Topology LED Driver with Inductive Fast Dimming REVISED NOVEMBER 2023

Description

LP8868-Q1 Automotive Multi-Topology LED Driver with Inductive Fast Dimming REVISED NOVEMBER 2023

Source title LP8868VQDMTRQ1 Datasheet(PDF) - Texas Instruments

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LP8868VQDMTRQ1

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LP8868U-Q1 TI | Alldatasheet

Document overview

Technical content

1 Features

2 Applications

3 Description

2.2 MHz with an optional spread spectrum feature for

Package Information

11 Mechanical, Packaging, and Orderable

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4 Comparison Table

5 Pin Configuration and Functions

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6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

14 PINS

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6.5 Electrical Characteristics

6.6 Typical Characteristics

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6.6 Typical Characteristics (continued)

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7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Adaptive Off-Time Current Mode Control

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7.3.1.1 Switching Frequency Settings

1 MHz 23

1.2 MHz 18

1.5 MHz 13

1.8 MHz 11

2.2 MHz 9

7.3.1.2 Spread Spectrum

7.3.2 Setting LED Current

7.3.3 Internal Soft Start

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7.3.4 Dimming Mode

7.3.4.1 PWM dimming

7.3.4.2 Analog dimming

7.3.4.3 Hybrid Dimming

7.3.4.4 Flexible Dimming

7.3.5 Undervoltage Lockout

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7.3.6 Fault Protection

7.3.7 Thermal Foldback

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8 Application and Implementation

8.1 Application Information

8.2 Typical Application

8.2.1 LP8868XQDMTRQ1 12-V Input, 1-A Output, 8-piece LED With Boost Topology

8.2.1.1 Design Requirements

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Inductor Selection

8.2.1.2.2 Input Capacitor Selection

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8.2.1.2.3 Output Capacitor Selection

8.2.1.2.4 Sense Resistor Selection

8.2.1.2.5 Other External Components Selection

8.2.1.3 Application Curves

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8.2.2 LP8868YQDMTRQ1 12-V Input, 1-A Output, 5-piece LED With Buck-Boost Topology

8.2.2.1 Design Requirements

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8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Inductor Selection

8.2.2.2.2 Input Capacitor Selection

8.2.2.2.3 Output Capacitor Selection

8.2.2.2.4 Sense Resistor Selection

8.2.2.2.5 Other External Components Selection

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8.2.2.3 Application Curves

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