Driver IC

LP8860NQVFPRQ1

Texas Instruments

Low-EMI Automotive LED Driver With Four 150-mA Channels

Manufacturer: Texas Instruments

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L D Up to 48V3...40 V FILTER VSYNC C OUT C IN SD GDVSENSE_N R ISET Up to 150 mA/string R SENSE ISENSE_GNDCPUMP C1P C1N VDD SYNC VIN C 2x VDDIO/EN SCLK/SCL MOSI/SDA MISO NSS PGND LGND PAD IF VSENSE_P R ISENSE TSENSE ISET FAULT SQW VDDIO R T° NTC FAULT EN FAULT RESET BRIGHTNESS V/H SYNC BOOST SYNC VDD 3.3V C VDD C CPUMP Copyright © 2016, Texas Instruments Incorporated 0 10 20 30 40 50 60 70 80 90 100 Efficiency (%) Brightness (%) VIN = 5 V VIN = 6 V VIN = 8 V VIN = 12 V VIN = 15 V C001 Product Folder Order Now T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP8860-Q1 SNVSA21F –MAY 2014–REVISED JULY 2017 LP8860-Q1Low-EMIAutomotiveLEDDriverWithFour150-mAChannels

1 Features

1• Qualified for Automotive Applications

AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature
Input Voltage Operating Range 3 V to 48 V
Four High-Precision Current Sinks – Current Matching 0.5% (typical) – LED String Current up to 150 mA per Channel – Dimming Ratio > 13 000:1 With External PWM Brightness Control – 16-bit Dimming Control with SPI or I2C – Supports Display Mode (Global Dimming) and Cluster Mode (Independent Dimming)
Hybrid PWM and Current Dimming for Higher LED Drive Optical Efficiency
Synchronization for LED PWM Frequency
Boost Controller With Programmable Switching Frequency 100 kHz to 2.2 MHz and Spread- Spectrum Option for Lower EMI
Boost Synchronization Input
Power-Line FET Control for Inrush Current Protection and Standby Energy Saving
Automatic LED Current Reduction With External Temperature Sensor
Extensive Fault Diagnostics Simplified Schematic

2 Applications

Backlight for: – Automotive Infotainment – Automotive Instrument Clusters – Smart Mirrors – Heads-Up Displays (HUD) – Central Information Displays (CID) – Audio-Video Navigation (AVN)

3 Description

The LP8860-Q1 is an automotive high-efficiency LED driver with boost controller. It has 4 high-precision current sinks that can be controlled by a PWM input signal, an SPI or I2C master, or both. The boost converter has adaptive output voltage control based on the headroom voltages of the LED current sinks. This feature minimizes the power consumption by adjusting the voltage to the lowest sufficient level in all conditions. A wide-range adjustable frequency allows the LP8860-Q1 to avoid disturbance for AM radio band. The LP8860-Q1 supports built-in hybrid PWM and current dimming, which reduces EMI, extends the LED lifetime, and increases the total optical efficiency. Phase-shift PWM reduces audible noise and output ripple. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LP8860-Q1 HLQFP (32) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. System Efficiency

7.13 Power-Line FET Control Electrical

7.14 External Temp Sensor Control Electrical

7.15 I2C Serial Bus Timing Parameters (SDA, SCLK) . 13

12.3 Receiving Notification of Documentation

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision E (November 2016) to Revision F Page Changes from Revision D (September 2016) to Revision E Page

www.ti.com SNVSA21F –MAY 2014–REVISED JULY 2017 Product Folder Links: LP8860-Q1 Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated Changes from Revision C (December 2015) to Revision D Page Changes from Revision B (March 2015) to Revision C Page Changes from Revision A (June 2014) to Revision B Page Changes from Original (May 2014) to Revision A Page

5 Device Comparison Table

LP8860-Q1 LP8862-Q1 LP8861-Q1 TPS61193-Q1 TPS61194-Q1 TPS61196-Q1 VIN range 3 V to 48 V 4.5 V to 45 V 4.5 V to 45 V 4.5 V to 45 V 4.5 V to 45 V 8 V to 30 V Number of LED channels 4 2 4 3 4 6 LED current / channel 150 mA 160 mA 100 mA 100 mA 100 mA 200 mA I2C/SPI support Yes No No No No No SEPIC support No Yes Yes Yes Yes No

EP* *EXPOSED PADFAULT SQW OUT4 IF VDDIO/EN C1P C1N CPUMP VDD SD VSENSE_P OUT1 OUT2 LGND FB SGND FILTER ISET TSENSE SYNC VSYNC PWM MISO NSS OUT3 VSENSE_N SCLK/SCL MOSI/SDA ISENSE PGND ISENSE_GND GD LP8860-Q1 www.ti.com SNVSA21F –MAY 2014–REVISED JULY 2017 Product Folder Links: LP8860-Q1 Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated

6 Pin Configuration and Functions

32-Lead PowerPAD™ Quad Flatpack S-PQFP-G32 Top View

SNVSA21F –MAY 2014–REVISED JULY 2017 www.ti.com Product Folder Links: LP8860-Q1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated (1) A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin Pin Functions PIN TYPE(1) DESCRIPTION NUMBER NAME 1 C1P A Positive pin for charge pump flying capacitor. If feature is disabled, the pin may be left floating. 2 C1N A Negative pin for charge pump flying capacitor. If feature is disabled, the pin may be left floating. 3 VDD P Input voltage pin for internal circuit. 4 SQW A Square wave output. Can be used for generating extra voltage rail. If unused, the pin may be left floating. 5 VSENSE_N A Pin for input current sense. 6 VSENSE_P A Pin for OVP/UVLO protection and input current sense. 7 ISET A Optional resistor for setting LED maximum current. If feature is disabled, the pin may be left floating. 8 TSENSE A External temperature sensor for LED current control. If feature is disabled, the pin may be left floating. 9 FILTER A Low pass filter for PLL. If feature is disabled, the pin may be left floating. 10 SGND G Signal ground. 11 FAULT OD Fault signal output. If unused, the pin may be left floating. 12 SYNC I Input for synchronizing boost. This pin must be connected to GND if not used. 13 VSYNC I Input for synchronizing PWM generation to display refresh. This pin must be connected to GND if feature is disabled. 14 MISO O Slave data output (SPI). If unused, the pin may be left floating. 15 MOSI/SDA I/O Slave data input (SPI) or serial data (I2C). This pin must be connected to GND if not used. 16 SCLK/SCL I Serial clock for SPI or I2C. This pin must be connected to GND if not used. 17 NSS I Slave select (SPI mode) or fault reset (I2C or standalone mode). This pin must be connected to GND if not used. 18 PWM I PWM dimming input. This pin must be connected to GND if feature is disabled. 19 VDDIO/EN I Enable input pin and reference voltage for digital pins. 20 IF I Interface selection: low – I2C or standalone mode; high – SPI. 21 OUT4 A LED current sink output. If unused, the pin may be left floating. 22 OUT3 A LED current sink output. If unused, the pin may be left floating. 23 LGND G LED current ground. 24 OUT2 A LED current sink output. If unused, the pin may be left floating. 25 OUT1 A LED current sink output. If unused, the pin may be left floating. 26 FB A Boost feedback input. 27 ISENSE_GND A Boost controller’s current sense resistor GND. 28 ISENSE A Boost current sense pin. 29 PGND G Power ground. 30 GD A Gate driver output for boost FET. 31 CPUMP P Charge pump output pin. 32 SD A Power line FET control. If unused, the pin may be left floating.

www.ti.com SNVSA21F –MAY 2014–REVISED JULY 2017 Product Folder Links: LP8860-Q1 Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the potential at the GND pins. (3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and disengages at TJ = 135°C (typical). (4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX ). (5) For detailed soldering specifications and information, refer to PowerPAD™ Thermally Enhanced Package Application Note .

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Voltage on pins VSENSE_N, VSENSE_P, OUT1 to OUT4, FB, SD –0.3 52 V Voltage on pins VDD, FILTER, SYNC, VSYNC, PWM, SCLK/SCL, MOSI/SDA, MISO, NSS, VDDIO/EN, IF, ISENSE, ISENSE_GND, FAULT, ISET, TSENSE, C1N –0.3 6 V Voltage on pins C1P, CPUMP, GD, SQW –0.3 12 V Continuous power dissipation(3) Internally Limited Ambient temperature, TA (4) –40 125 °C Junction temperature, TJ(4) –40 150 °C Maximum lead temperature (soldering) See(5) °C Storage temperature, Tstg –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 All pins ±500 Corner pins (1) All voltages are with respect to the potential at the GND pins.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage on pins VSENSE_N, VSENSE_P 3 48 V VDD input voltage 3 5.5 V VDDIO/EN input voltage 1.65 VDD V Voltage on pins FILTER, ISENSE, ISENSE_GND, ISET, TSENSE, C1N 0 5.5 V FAULT, PWM, SCLK/SCL, MOSI/SDA, NSS, IF, SYNC, MISO, VSYNC 0 VDDIO V Voltage on pins C1P, CPUMP, GD, SQW 0 11 V Voltage on pins OUT1 to OUT4, FB, SD 0 48 V

SNVSA21F –MAY 2014–REVISED JULY 2017 www.ti.com Product Folder Links: LP8860-Q1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. (2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.4 Thermal Information

THERMAL METRIC(1) LP8860 UNITHLQFP PowerPAD (VLP)

32 PINS

RθJA Junction-to-ambient thermal resistance(2) 36.0 °C/W RθJCtop Junction-to-case (top) thermal resistance 23.3 °C/W RθJB Junction-to-board thermal resistance 15.5 °C/W ψJT Junction-to-top characterization parameter 3.2 °C/W ψJB Junction-to-board characterization parameter 15.5 °C/W RθJCbot Junction-to-case (bottom) thermal resistance 1.6 °C/W (1) All voltages are with respect to the potential at the GND pins. (2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis.

7.5 Electrical Characteristics

TJ = −40°C to +125°C (unless otherwise noted).(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES IQ Shutdown supply current for VDD Device disabled, VDDIO/EN = 0 V 1 5 μA Active supply current for VDD, VDD = 5 V Backlight enabled (no load), boost enabled, PLL and CP disabled, DRV_LED_BIAS_CTRL[1:0] = 10 , boost ƒSW = 300 kHz 2.5 6 mA Backlight enabled (no load), boost enabled, CP disabled, ƒPLL = 10 MHz, DRV_LED_BIAS_CTRL[1:0] = 11, boost ƒSW = 400 kHz 4.5 15 VVDD_POR_R Power-on reset rising threshold 2.2 V VVDD_POR_F Power-on reset falling threshold 1.1 TTSD Thermal shutdown threshold 150 165 180 TTSD_THR Thermal shutdown hysteresis 30 INTERNAL OSCILLATOR ƒOSC Frequency 10 MHz Frequency accuracy –7% 7% (1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT4), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that some manufacturers have different definitions in use.

7.6 Current Sinks Electrical Characteristics

Limits apply over the full ambient temperature range –40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12 V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33 μF electrolytic, COUT = 2 × 10 μF ceramic and 33 μF electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ILEAKAGE Leakage current Outputs OUT1 to OUT4, VOUT = 48 V 0.1 1 µA IMAX Maximum source current OUT1 to OUT4 150 mA IOUT Output current accuracy IOUT = 150 mA −3% 3% IMATCH Output current matching(1) IOUT = 150 mA, 100% brightness 0.5% 2% ƒLED_PWM LED PWM output frequency for display mode PWM_FREQ[3:0] = 0000b PWM_FREQ[3:0] = 1111b 4883 39 063 Hz

www.ti.com SNVSA21F –MAY 2014–REVISED JULY 2017 Product Folder Links: LP8860-Q1 Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated Current Sinks Electrical Characteristics (continued) Limits apply over the full ambient temperature range –40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12 V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33 μF electrolytic, COUT = 2 × 10 μF ceramic and 33 μF electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V. ƒPWM PWM input frequency BRT_MODE[1:0] = 00, 01 and 10 100 500 Hz tPWM MIN Minimum on and off time for PWM input 400 ns IDIM Dimming ratio (input resolution) External 100 Hz PWM 13 000:1 SPI or I2C control 16 bit PWMRES PWM output resolution, PWM control for BRT_MODE[1:0] = 00, 01, and 10 (without dithering) ƒLED_PWM = 5 kHz, ƒOSC = 5 MHz 10 bits ƒLED_PWM= 10 kHz, ƒOSC = 5 MHz 9 ƒLED_PWM = 20 kHz, ƒOSC = 5 MHz 8 ƒLED_PWM = 40 kHz, ƒOSC = 5 MHz 7 ƒLED_PWM = 5 kHz, ƒOSC = 40 MHz 13 ƒLED_PWM = 10 kHz, ƒOSC = 40 MHz 12 ƒLED_PWM = 20 kHz, ƒOSC = 40 MHz 11 ƒLED_PWM = 40 kHz, ƒOSC = 40 MHz 10 ΔIOUT Individual output current adjustment range DRV_OUTx_CORR[3:0] = 1111 –7.4% DRV_OUTx_CORR[3:0] = 0000 6.5% VSAT Saturation voltage(2) IOUT = 150 mA 0.5 0.75 V VSHORT_FAULT_THR LED short detection threshold DRV_LED_FAULT_THR[1:0] = 00 3.6 V DRV_LED_FAULT_THR[1:0] = 01 3.6 DRV_LED_FAULT_THR[1:0] = 10 6.9 DRV_LED_FAULT_THR[1:0] = 11 10.6 (1) Start-up time is measured from the moment the boost is activated until the VOUT crosses 90% of its initial voltage value.

7.7 Boost Converter Characteristics

Limits apply over the full ambient temperature range – 40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12 V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33-μF electrolytic, COUT = 2 × 10 μF ceramic and 33-μF electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ILOAD Maximum continuous load current VIN = 6 V, VBOOST = 48 V (ƒSW = 303 kHz) 600 mAVIN = 3 V, VBOOST = 30 V (ƒSW = 1.1 MHz) 150 VIN = 3 V, VBOOST = 30 V (ƒSW = 2.2 MHz) 100 VOUT/VIN Conversion ratio 10 ƒSW Switching frequency (central frequency if spread spectrum is enabled) BOOST_FREQ = 000 BOOST_FREQ = 001 BOOST_FREQ = 010 BOOST_FREQ = 011 BOOST_FREQ = 100 BOOST_FREQ = 101 BOOST_FREQ = 110 BOOST_FREQ = 111 –7% 100 200 303 400 629 800 1100 2200 7% kHz tBOOST START-UP Start-up time (1) 50 ms

SNVSA21F –MAY 2014–REVISED JULY 2017 www.ti.com Product Folder Links: LP8860-Q1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Boost Converter Characteristics (continued) Limits apply over the full ambient temperature range – 40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12 V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33-μF electrolytic, COUT = 2 × 10 μF ceramic and 33-μF electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IMAX SW current limit RSENSE = 25 mΩ A BOOST_IMAX_SEL=000 BOOST_IMAX_SEL=001 BOOST_IMAX_SEL=010 BOOST_IMAX_SEL=011 BOOST_IMAX_SEL=100 BOOST_IMAX_SEL=101 BOOST_IMAX_SEL=110 BOOST_IMAX_SEL=111 VGD Gate driver output voltage 0 11 V IGD_SOURCE_ PEAK Gate driver peak current, sourcing BOOST_DRIVER_SIZE[1:0] = 11 BOOST_GD_VOLT = 1 VDD= 5 V, VCPUMP = 10 V FET SQ4850EY 1.7 A IGD_SINK_PEA K Gate driver peak current, sinking 1.5

7.8 Logic Interface Characteristics

VDDIO/EN = 1.65 V to VDD, VDD = 3.3 V unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUT VDDIO/EN VIL Input low level 0.4 V VIH Input high level 1.2 II Input current −1 1 µA LOGIC INPUT SYNC, VSYNC, PWM, SCLK/SCL, MOSI/SDA, NSS, IF VIL Input low level 0.2 × VDDIO/EN V VIH Input high level 0.8 × VDDIO/EN II Input current −1 1 μA LOGIC OUTPUT FAULT VOL Output low level I = 3 mA 0.3 0.5 V ILEAKAGE Output leakage current V = 5.5 V 1 μA LOGIC OUTPUT MISO VOL Output low level IOUT = 3 mA 0.3 0.5 V VOH Output high level IOUT = –2 mA 0.7 × VDDIO/EN 0.9 × VDDIO/EN IL Output leakage current 1 μA LOGIC OUTPUTS SDA VOL Output low level I = 3 mA 0.3 0.5 V ILEAKAGE Output leakage current V = 5.5 V 1 μA

7.9 VIN Undervoltage Protection (VIN_UVLO)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VUVLO VIN UVLO threshold voltage UVLO[1:0] = 00 Disabled V UVLO[1:0] = 01 2.64 3 3.36 UVLO[1:0] = 10 4.4 5 5.6 UVLO[1:0] = 11 7.04 8 8.96

7.10 VDD Undervoltage Protection (VDD_UVLO)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVDD_UVLO VDD UVLO threshold voltage VDD_UVLO_LEVEL = 0 2.5 V VDD_UVLO_LEVEL = 1 3 VHYST VDD UVLO hysteresis 50 mV

7.11 VIN Overvoltage Protection (VIN_OVP)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOVP VIN OVP threshold voltage OVP[1:0] = 00 Disabled V OVP[1:0] = 01 6.16 7 7.84 OVP[1:0] = 10 9.68 11 12.32 OVP[1:0] = 11 19.8 22.5 25.2 (1) Refer to Selecting Current Sensing Resistor for LP8860-Q1 Power Input application note.

7.12 VIN Overcurrent Protection (VIN_OCP)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOCP VIN current protection limit with RISENSE = 20 mΩ, VIN = 12 V See(1) PL_SD_LEVEL[1:0] = 10 6 A PL_SD_LEVEL[1:0] = 11 8

7.13 Power-Line FET Control Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IL,VSENSE_P VSENSE_P pin leakage current VSENSE_P = 48 V 0.1 3 µAIL,VSENSE_N VSENSE_N pin leakage current VSENSE_N = 48 V IL,SD SD pin leakage current VSD = 48 V ISD PFET Pulldown current for power-line p-FET, NMOS_PLFET_EN=0 PL_SD_SINK_LEVEL = 00 PL_SD_SINK_LEVEL = 01 PL_SD_SINK_LEVEL = 10 PL_SD_SINK_LEVEL = 11 110 220 440 µA

7.14 External Temp Sensor Control Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RTEMP_HIGH TSENSE high level resistance value EXT_TEMP_LEVEL_HIGH[3:0] = 0000 EXT_TEMP_LEVEL_HIGH[3:0] = 0001 EXT_TEMP_LEVEL_HIGH[3:0] = 0010 EXT_TEMP_LEVEL_HIGH[3:0] = 0011 EXT_TEMP_LEVEL_HIGH[3:0] = 0100 EXT_TEMP_LEVEL_HIGH[3:0] = 0101 EXT_TEMP_LEVEL_HIGH[3:0] = 0110 EXT_TEMP_LEVEL_HIGH[3:0] = 0111 EXT_TEMP_LEVEL_HIGH[3:0] = 1000 EXT_TEMP_LEVEL_HIGH[3:0] = 1001 EXT_TEMP_LEVEL_HIGH[3:0] = 1010 EXT_TEMP_LEVEL_HIGH[3:0] = 1011 EXT_TEMP_LEVEL_HIGH[3:0] = 1100 EXT_TEMP_LEVEL_HIGH[3:0] = 1101 EXT_TEMP_LEVEL_HIGH[3:0] = 1110 EXT_TEMP_LEVEL_HIGH[3:0] = 1111 79.67 43.35 29.77 22.67 18.30 15.34 13.21 11.60 10.34 9.32 8.49 7.79 7.20 6.69 6.25 5.87 kΩ

SNVSA21F –MAY 2014–REVISED JULY 2017 www.ti.com Product Folder Links: LP8860-Q1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated External Temp Sensor Control Electrical Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RTEMP_LOW TSENSE low-level resistance value EXT_TEMP_LEVEL_LOW[3:0] = 0000 EXT_TEMP_LEVEL_LOW[3:0] = 0001 EXT_TEMP_LEVEL_LOW[3:0] = 0010 EXT_TEMP_LEVEL_LOW[3:0] = 0011 EXT_TEMP_LEVEL_LOW[3:0] = 0100 EXT_TEMP_LEVEL_LOW[3:0] = 0101 EXT_TEMP_LEVEL_LOW[3:0] = 0110 EXT_TEMP_LEVEL_LOW[3:0] = 0111 EXT_TEMP_LEVEL_LOW[3:0] = 1000 EXT_TEMP_LEVEL_LOW[3:0] = 1001 EXT_TEMP_LEVEL_LOW[3:0] = 1010 EXT_TEMP_LEVEL_LOW[3:0] = 1011 EXT_TEMP_LEVEL_LOW[3:0] = 1100 EXT_TEMP_LEVEL_LOW[3:0] = 1101 EXT_TEMP_LEVEL_LOW[3:0] = 1110 EXT_TEMP_LEVEL_LOW[3:0] = 1111 79.67 43.35 29.77 22.67 18.30 15.34 13.21 11.60 10.34 9.32 8.49 7.79 7.20 6.69 6.25 5.87 kΩ RTS_FLOAT TSENSE maximum resistance (missing resistor fault value) 2 MΩ

7.15 I2C Serial Bus Timing Parameters (SDA, SCLK)

3 Clock high time 600 ns

4 Set-up time for a repeated START condition 600 ns

5 Data hold time 50 ns

6 Data setup time 100 ns

9 Set-up time for STOP condition 600 ns

7.16 SPI Timing Requirements

1 Cycle time 70 ns

2 Enable lead time 35 ns

3 Enable lag time 35 ns

4 Clock low time 35 ns

5 Clock high time 35 ns

6 Data setup time 20 ns

7 Data hold time 20 ns

8 Disable time 10 ns

9 Data valid 29 ns

10 NSS inactive time 700 ns

Figure 1. I2C Timing Figure 2. SPI Timing Diagram

7.17 Typical Characteristics

Figure 3. System Efficiency Figure 4. System Efficiency Figure 5. Boost Maximum Output Current Figure 6. LED Current vs Headroom Voltage Figure 7. Boost Ripple Figure 8. Boost Ripple

8 Detailed Description

8.1 Overview

The LP8860-Q1 is a high-voltage LED driver for automotive infotainment, LED clusters, and medium-sized LCD backlight applications with a boost controller. The device can be used as a stand-alone device, with a simple four-wire control:

VDDIO/EN for enable
PWM input for brightness control
FAULT output to indicate fault condition
NSS input for fault reset Alternatively, the LP8860-Q1 can be controlled through I2C or SPI serial interface which allows wide range of user-specific configurable features.

8.1.1 Boost Controller

The boost controller generates a 16-V to 48-V supply for LED strings. To optimize LED drive efficiency the boost controller includes adaptive output voltage control which gets feedback from monitoring the internal LED current sinks voltage circuit. This feature minimizes power consumption by adjusting the boost voltage to lowest sufficient level in all conditions. Boost switching frequency can be set in a wide range from 100 kHz to 2.2 MHz. This enables system optimization for both high power applications, where efficiency is critical, and for lower power applications where small solution size can be achieved with high boost switching frequency. The LP8860-Q1 has several features for system EMI optimization:

Boost switching frequency can be selected either below or above AM band.
Spread spectrum can be enabled to reduce energy around the switching frequency and its harmonics.
Boost switching can be synchronized to an external clock with a dedicated SYNC input.
Gate drive strength for the external FET is controllable with EEPROM.

8.1.2 LED Output Configurations

The LP8860-Q1 has four high-precision current sinks with up to 150 mA per output capability. LED outputs can be connected parallel to reach higher current levels. LED outputs are highly configurable; for example, there are features such as brightness slope control, external clock synchronization, phase shifting, adaptive headroom control, etc. In general there are 2 main user modes:

Display Mode (with full feature set) and/or
Cluster Mode (with limited feature set) These modes and features are detailed in later sections.

8.1.3 Display Mode

In Display Mode LED outputs are configured to power an LCD backlight. Maximum current per string is set by RISET; alternatively, through a user-programmable EEPROM value. Brightness is controlled with PWM input or I2C/SPI register writes. An optional sloper feature enables automatic smooth transition between brightness levels. Sloper time can be programmed to EEPROM registers, and an advanced slope feature allows smoother response to eye compared to traditional linear slope. Outputs are controlled with a Phase Shift PWM (PSPWM) Scheme. Due to the phase shift between the outputs they are not activated simultaneously which brings several benefits:

Peak load current from the boost output is decreased, which reduces the voltage ripple seen at the boost output and allows smaller output capacitors.
Smaller ripple reduces the possible audible noise from the ceramic boost output capacitors.
PSPWM scheme multiplies the effective load frequency seen at the boost output by number of active channels. This further reduces the audible noise by transferring the output ripple frequency above human

Optical ripple through LCD panel is reduced, helping to reduce the “waterfall” effect which is caused by asynchronous backlight ripple and LCD refresh. PWM output frequency is set with EEPROM registers from 4.9 kHz to 39 kHz. Selecting output frequency depends on the number of strings used, system requirements for the frequency, and desired dimming ratio. Dimming resolution is a function of PWM output frequency — the higher the frequency, the lower the resolution. User can choose to increase resolution by:
enabling dithering function (optional through EEPROM), or
increasing internal clock frequency. Increasing internal clock frequency increases device current consumption. In high-quality display systems an "anti-waterfall" feature may be required. The LP8860-Q1 supports this by offering output synchronization to the LCD refresh signal through VSYNC input. VSYNC input is synchronized to outputs through internal PLL; EEPROM and filtering are described in later sections.

8.1.4 Cluster Mode

In Cluster mode LED strings have independent control but fewer features enabled than in Display Mode. Brightness (PWM and current) are independently controlled for all 4 outputs. When there is an unequal number of LEDs per channel, the LP8860-Q1 adaptive voltage control is not used in Cluster mode; therefore, boost output voltage is fixed (or externally controlled or powered). In Cluster mode PWM frequency can be set through EEPROM, and Phase Shift PWM mode is enabled. Cluster mode does not support the PWM input pin, hybrid dimming, slope control or dither mode.

8.1.5 Hybrid Dimming

Hybrid dimming combines both PWM and current-dimming benefits offering the best optical efficiency to drive LEDs. At higher brightness levels only the LED constant current is controlled; at lower brightness levels LED brightness is controlled by adding PWM on top of low constant current value. Because LED optical efficacy declines with high forward current, reducing the current yields better system optical efficiency compared with conventional PWM dimming. An additional benefit of current dimming is reduced EMI compared to PWM switching. PWM dimming is used with lower brightness values to achieve a higher dimming ratio. The optimum switch point between PWM and current dimming is programmable and depends on the LED type.

8.1.6 Charge Pump and Square Waveform (SQW) Output

The gate driver for the external boost FET can be powered directly from the VDD input or from the charge pump integrated into the LP8860-Q1. When a 5-V rail is available in the system for VDD supply, it is typically a high enough voltage to drive the external FET, and the internal charge pump can be disabled. In this case, the VDD and CPUMP pins must be shorted together, and the fly cap can be removed. When the system VDD is not high enough to drive the gate of the boost FET (typical case is 3.3 V), the charge pump can be used to multiply the gate drive voltage to 2× VDD. The SQW output provides a 100-kHz square wave signal (1 mA maximum) with amplitude equal to the charge- pump output voltage. When the charge pump is disabled, the amplitude of the SQW signal is equal to VDD. See Charge Pump and High Output Voltage Application sections for usage examples.

8.1.7 Power-Line FET

Some automotive systems require a safety switch to disconnect the driver device from the battery. The LP8860- Q1 offers a power-line FET control circuit, which limits inrush current from the power line during start-up and reduces standby power consumption by disconnecting device from the power-line during an off state. This FET disconnects the boost and LED strings from the input during fault conditions. For example, when the input voltage is above the overvoltage protection (OVP) level, the power-line FET disconnects the LED strings from the power-line to protect LED outputs against overheating.

www.ti.com SNVSA21F –MAY 2014–REVISED JULY 2017 Product Folder Links: LP8860-Q1 Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated Overview (continued) Depending on which fault has shut down the power-line FET, the device can enter automatic fault recovery state where the power-line FET is turned on in 100-ms time periods to see if the fault condition has been removed. If the fault was only short-term, and normal operation condition returns, the device turns back on automatically.

8.1.8 Protection Features

Extensive fault-detection and protection features of the LP8860-Q1 include:

Open-string and shorted LED detections – LED fault detection prevents system overheating in case of open in some of the LED strings
Boost overcurrent
Boost overvoltage
VIN input overvoltage protection – Threshold sensing from VSENSE_P pin
VIN input undervoltage protection – Threshold sensing from VSENSE_P pin
VIN input overcurrent protection – Threshold sensing across RISENSE resistor
VDD input undervoltage lockout
Thermal shutdown in case of die overtemperature (165°C nominal) Fault protection thresholds are EEPROM programmable and some protection features can be disabled, or masked, if necessary. A fault condition is indicated through the FAULT pin. If an I2C/SPI interface is used, the fault reason can be read from the register, and flags can be cleared with register write.

8.1.9 Advanced Thermal Protection Features

The LP8860-Q1 has a unique features for protecting against overheating: 1. Die temperature based Thermal de-rating function. Average LED current is automatically lowered when die temperature increases above a predefined (90ºC, 100ºC, or 110ºC) level. Decreasing LED current reduces thermal loading on the device and prevents overheating. 2. An external NTC sensor-based protection, where a sensor can be placed close to LEDs to protect them from overheating. The sensor is connected to the TSENSE pin of the device. Two methods are available: – Current de-rating, where the LED current is lowered proportionally to the temperature measured with the external NTC sensor. This method is available only if LED max current is set with RISET resistor. – Brightness limitation above a predefined temperature

D R SENSE GD ISENSE ISENSE_GND POWER-LINE FET CONTROL R ISENSE SDVSENSE_NVSENSE_P CHARGE PUMP C 2X C CPUMP C1P C1N CPUMP FB BOOST CONTROLLER VDD VIN SYNC C VDD VDD PGND OUT1 OUT2 OUT3 OUT4 LGND 4 x LED CURRENT SINKANALOG BLOCKS (CLOCK GENERATOR, PLL, VREF, ADC, DACs etc.) DIGITAL BLOCKS (FSM, PWM DETECTOR, BRIGTNESS CONTROL, SLOPER, HYBRID DIMMING, SAFETY LOGIC etc.) FILTER ISET TSENSE R ISET NTC tº PWM VSYNC FAULT VDDIO/EN SPI/I2C INTERFACE SCLK/SCL MOSI/SDA MISO NSS IF SGND EXPOSED PAD SQW EEPROM Copyright © 2016, Texas Instruments Incorporated LP8860-Q1 SNVSA21F –MAY 2014–REVISED JULY 2017 www.ti.com Product Folder Links: LP8860-Q1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated

8.2 Functional Block Diagram

10 MHz Internal

5 MHz

8.3 Feature Description

8.3.1 Clock Generation

multiplication is set with <PWM_RESOLUTION[1:0]> EEPROM bits.

8.3.1.1 LED PWM Clock Generation With VSYNC

output PWM frequency with video processor or timing controller VSYNC/HSYNC signal can reduce this effect. must be used only if a slow divider is enabled — otherwise the LP8860-Q1 uses internal compensation. active before VDDIO/EN is set high and present whenever VDDIO/EN is high. Figure 9. PLL Clock Generation

8.3.1.2 LED PWM Frequency and Resolution

LED PWM resolution. PWM frequencies with <EN_SYNC> = 0 are listed in Table 1.

section explains how all the dividers affect the output clocks. Figure 10. PWM Clocking With Internal Oscillator Figure 11. PWM Clocking With PLL, Internal Oscillator as Reference Table 1. Output PWM Frequency and Resolution With Internal Oscillator

Table 1. Output PWM Frequency and Resolution With Internal Oscillator (continued) Figure 12. PWM Synchronization With External VSYNC Input Table 2. PLL Clock and LED PWM Frequency

0 X 0 0 5 MHz See Table 1

GEN_DIV coefficients and resolution (bit) are listed on Table 3. Table 3. GEN_DIV Coefficients and Resolution

Table 3. GEN_DIV Coefficients and Resolution (continued) <EN_STEADY_DITHER> is high, otherwise during slope only. Figure 13. Example of the Dithering, 1-Bit Dither, 10-Bit Resolution

8.3.2 Brightness Control (Display Mode)

Table 4. Brightness Control Selection

00 PWM input duty cycle

01 PWM input duty cycle x Brightness register

10 Brightness register

11 PWM direct control (PWM in = PWM out)

8.3.2.1 PWM Input Duty Cycle Based Control

PWM period is measured from rising edge to the next rising edge. The ratio of input PWM frequency and 10-MHz sampling clock defines resolution reachable with external PWM. minimum on and off time for the PWM input signal is 400 ns.

8.3.2.2 Brightness Register Control

8.3.2.3 PWM Input Duty × Brightness Register

to achieve the LED output PWM.

8.3.2.4 PWM-Input Direct Control

PWM delay can be 5 to 6 clock cycles from input PWM. brightness slope, dither, Hybrid PWM and Current dimming, and LED current limitation with external NTC. turns off at 100% duty cycle.

8.3.2.5 Brightness Slope

slope makes brightness changes smooth for eye. Table 5. Slope Time

Figure 14. Sloper Operation

8.3.2.6 LED Dimming Methods

In additional to conventional PWM dimming control the LP8860-Q1 supports Hybrid PWM and Current dimming. illustrated by Figure 15. Only 25% switch points and slope gain = 1 are shown for simplicity. Figure 15. Principles of PWM Dimming and Hybrid PWM and Current Dimming <I_SLOPE[2:0]> EEPROM bits, respectively (see Table 6 and Table 7).

Figure 16. Optical Efficiency Improvement With PWM and Current Dimming

Table 6. Gain Control Selections Table 7. Current Slope Control Selections

Formula is only approximation for the actual value.
DISP_CL1_CURRENT[11:0] value must be chosen to avoid current saturation before 100%

8.3.2.7 PWM Calculation Data Flow for Display Mode

are bypassed, and this flow chart does not apply. Figure 17. PWM Data Flow Calculation Table 8. PWM Calculation Blocks input signal frequency. Hysteresis selection sets the minimum allowable change to the input. Smaller changes are ignored. duty cycle value, the brightness register value or multiplication. adjusted from 0 ms to 511 ms with <PWM_SLOPE[2:0]> EEPROM bits. PWM comparator compares the PWM counter output to the value received from the dither block. offset value to create different phases. <PWM_FREQ[3:0]> and <PWM_RESOLUTION[1:0]> bits, see Table 3.

8.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme

addition, “optical ripple”through the LCD panel is reduced helping in waterfall noise reduction. Figure 18. Phase Shift Modes

Table 9. Description of the LED Output Modes 5 101 1 LED string (1+2+3+4). All strings with same phase (can be tied together).

Table 10. Output Mode Configuration

8.3.4 LED Current Setting

Figure 19. LED Current Setting when that option is enabled. For strings in cluster mode current for every LED output can be set independently. for all outputs except OUT1. For OUT1 maximum current resolution is always 12 bits. Table 12 Maximum current settings are effective for display and cluster modes. Table 11. LED Current Scaling

3000 V DISP_CL1_CURRENT[11: 0] DRV _LED_CURRENT _SCALE[2 : 0] (DRV_OUTx _CORR[3 : 0] 100)I R 4095 150 100

Table 11. LED Current Scaling (continued) 24-kΩ RISET resistor is used, then the LED maximum current is 150 mA. Table 12. Individual Current Correction Formulas are only approximation for the actual current.

voltage control instability.

8.3.5 Cluster Mode

Cluster is a simplified mode which allows independent current and PWM control for every string in cluster mode. and resolution for strings in the cluster mode is the same as for strings in the display mode (see Table 1). Figure 20. Cluster Mode Block Diagram Table 13. Output PWM Frequency for Mode 7 (All Strings in Cluster Mode) level <DRV_HEADR[2:0]> (which depend upon saturation voltage); otherwise a fault is generated. same boost, LED open or short faults may be generated if the LED forward-voltage mismatch is too high. <EN_CL_LED_FAULT>=0 disables cluster LED fault detection, even if all LED strings are in the cluster mode. functionality is limited (LED shutdown for high temperature is not operational).

8.3.6 Boost Controller

The LP8860-Q1 boost controller generates a 16-V to 48-V supply voltage for the LEDs. Output voltage can be increased by an external resistive voltage divider connected to the FB pin, but voltage lower than 16 V is not supported. The output voltage can be controlled either with EEPROM register bits <BOOST_INITIAL_VOLTAGE[5:0]>, or automatic adaptive boost control can be used. During start-up the output voltage is ramped to default start-up voltage <BOOST_INITIAL_VOLTAGE[5:0]> where it then adapts to the required voltage based on LED output headroom voltage (if adaptive mode has been enabled in EEPROM). Initial voltage for adaptive voltage control mode must be higher than LED string voltage — otherwise the system may generate a boost overvoltage fault during VDDIO/EN pin toggling if the output boost capacitor is not discharged below the initial voltage before the next boost start-up. A different option is to set <MASK_BOOST_OVP_STATUS> bit high to prevent a boost overvoltage fault. The converter is a magnetic switching PWM mode DC-DC converter with a current limit. The topology of the magnetic boost converter is called Current Programmed Mode (CPM) control, where the inductor current is measured and controlled with the feedback. Switching frequency is selectable from 100 kHz and 2.2 MHz with EEPROM bits <BOOST_FREQ_SEL[2:0]>. In most cases lower frequency has the highest system efficiency. In adaptive mode the boost output voltage is adjusted automatically based on LED current sink headroom voltage. Boost output voltage control step size is, in this case, 125 mV to ensure as small as possible current sink headroom and high efficiency. The adaptive mode is enabled with the <EN_ADAP EEPROM> bit. If boost is started with adaptive mode enabled, then the initial boost output voltage value is defined with the <BOOST_INITIAL_VOLTAGE[5:0]> EEPROM register bits in order to eliminate long output voltage iteration time when boost is started after VDDIO/EN toggling or power-on reset. Boost can be clocked by an external SYNC signal (100 kHz to 2.2 MHz); minimum pulse length for the signal is 200 ns. If an external SYNC disappears, boost uses internal frequency defined by <BOOST_FREQ_SEL[2:0]> EEPROM bits. The boost frequency with external SYNC and EEPROM bits-defined frequency need to be close to each other; maximum frequency mismatch is ±25%. The boost controller has optional spread-spectrum switching operation (±3% from central frequency, 1.875-kHz modulation frequency) which reduces spectrum spikes around the switching frequency and its harmonic frequencies. Further EMI reduction can be achieved by limiting the rise and fall times of the FET with an additional external resistor on the GD pin. The boost gate driver is powered directly from VDD voltage or from the charge pump which multiplies VDD voltage by 2. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.

Figure 21. Boost Converter Topology

8.3.7 Charge Pump

enough to drive the boost FET gate, the charge pump can be used to increase gate-driver voltage. The charge pump effectively doubles the VDD voltage for gate driver. Maximum DC output current is 50 mA. charge pump output CPUMP pin must be connected to the VDD input pin. Figure 22. Charge Pump Table 14. Charge Pump Clock Frequency

8.3.8 Powerline Control FET

to be disconnected during a fault condition, when device is in fault recovery state. <PL_SD_SINK_LEVEL[1:0]> EEPROM bits. Figure 26. Power-line FET Control case the SD pin provides current to shut down the power-line nFET during fault condition.

8.3.9 Protection and Fault Detection Modes

LED overtemperature protection with an external NTC thermistor. occurred fault. Writing CLEAR_FAULTS or setting the NSS pin (I2C interface mode only) high resets the fault. Setting the VDDIO/EN pin low, then high again, resets the faults as well.

8.3.9.1 LED Fault Comparators and Adaptive Boost Control

adaptive control voltage step size is 125 mV. Boost adaptive control operates similarly with and without PSPWM. Additionally, when faster boost response is needed in larger brightness steps, the "jump" command can be used.

Figure 27. Boost Voltage Adaptation Figure 28. Output Voltage Comparators Figure 29 shows different cases which cause boost voltage increase, decrease, or generate faults. Figure 29. Protection and Boost Adaptation Algorithms

8.3.9.2 LED Current Dimming With Internal Temperature Sensor

current is used for average current reduction.

Figure 30. Thermal De-Rating Function Table 15. Temperature ADC Output for Different Temperatures

Table 15. Temperature ADC Output for Different Temperatures (continued)

8.3.9.3 LED Current Limitation With External NTC Sensor

limitation is shown in Figure 31. LEDs are turned on automatically when the temperature is below the <EXT_TEMP_LEVEL_LOW[3:0]> level. <TEMP_RES_MISSING> flag is set, if the NTC sensor is missing (resistance is 2 MΩ or more). Figure 31. LED Current Limitation With NTC

Figure 32. Timing Diagram for LED Current Limitation With NTC

8.3.9.4 LED Current Dimming With External NTC Sensor

by <EXT_TEMP_I_DIMMING_EN> and <EXT_TEMP_COMP_EN> EEPROM bits. Figure 33. Current Dimming for High Ambient Temperature Figure 34. NTC Linearization Figure 35 and Figure 36 show the block diagrams for current dimming.

Figure 35. Temperature-Dependent NTC Current Figure 36. NTC Current Processing — ITEMP cannot be negative; if ITEMP < 0, then ITEMP must be 0. ILED cannot go below a 5-mA level; if calculated ILED < 5 mA, then ILED = 5 mA.

ISET: Maximum current setting with external resistor RISET, µA
ITEMP: Temperature compensation, µA
RISET: External resistor, kΩ
R1, R2: Resistors for adjustment, kΩ
ILED: Output current per channel, mA
EXT_TEMP_MINUS[1:0]: 1, 5, 9, 13 µA
EXT_TEMP_GAIN[[3:0]: 50/n, n = 16 to 1
VBG: 1.2 V (8)

8.3.9.5 Protection Feature and Fault Summary

Table 16 summarizes protection features and related faults.

(1) Recovery time is 100 ms. (2) During fault recovery state the LED outputs and boost is shut down and power-line FET is turned off. (3) If fault recovery is masked, fault bit sets again after cleaning. (4) If fault is cleared during fault recovery state, FAULT pin is pulled low again after recovery state, if this fault still exists. (5) The NSS pin can be used for fault reset only for I2C interface mode. NSS is level sensitive; be aware NSS is set to low after fault reset. Table 16. Overview of the Fault/Protection Schemes

00 OFF

UVLO_LEVEL[1:0] (V) VIN undervoltage monitored from soft start. exception registers 0x00, 0x01, 0x04… 0x0C.

Table 16. Overview of the Fault/Protection Schemes (continued)

Detects overcurrent from soft start by
Detects FB voltage at the end of soft start. If

set only if LED faults are enabled in EEPROM. loop and LED current sink n is disabled. set only if LED faults enabled in EEPROM. Open string PWM generation is disabled.

111 VSAT+50

110 VSAT+175

101 VSAT+300

100 VSAT+450

011 VSAT+575

010 VSAT+700

001 VSAT+875

000 VSAT+1000

fault register bit is not automatically cleared.

brightness reduction as well. exceeded, the LED outputs are turned off.

Thermal shutdown is monitored from soft start.

8.4 Device Functional Modes

8.4.1 Standby Mode

8.4.2 Active Mode

8.4.3 Fault Recovery State

Figure 42. State Diagram

8.4.4 Start-Up and Shutdown Sequences

up/shutdown sequence is shown in Figure 43.

Figure 43. Timing Diagram for the Typical Start-Up and Shutdown

8.5 Programming

8.5.1 EEPROM

the normal VDD voltage is required. A complete EEPROM memory map is shown in the Table 22. programming/burn sequence to avoid memory corruption. Figure 44. EEPROM and Register Configuration

Table 18. EEPROM Pass Code Protection

8.5.2 Serial Interface

SPI interface (4-wire serial)
I2C-compatible (2-wire serial) The user can define the interface mode by IF pin as shown in Table 19. The LP8860-Q1 detects interface mode selection during start-up. When the device is in normal mode, the IF signal does not affect the interface selection.

Table 19. Interface Modes

8.5.2.1 SPI Interface

and Data are transmitted MSB first. The Slave Select signal NSS must be low during the Cycle transmission. on the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK. Figure 45. SPI Write Cycle Figure 46. SPI Read Cycle

8.5.2.2 I2C Serial Bus Interface

8.5.2.2.1 Interface Bus Overview

connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). whether it generates or receives the SCL. The LP8860-Q1 is always a slave device.

8.5.2.2.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL. information and data using the synchronous serial clock. Figure 47. Bit Transfer sections provide further details of this process. Figure 48. Start and Stop Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition. Figure 49. Stop and Start Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle.

8.5.2.2.3 Acknowledge Cycle

transferred, and the acknowledge signal sent by the receiving device.

8.5.2.2.4 Acknowledge After Every Byte Rule

signal after every byte received. but the SDA line is not pulled down.

8.5.2.2.5 Addressing Transfer Formats

signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. Figure 50. Address and Read/Write Bit

8.5.2.2.6 Control Register Write Cycle

Master device generates start condition.
Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).
Slave device sends acknowledge signal if the slave address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master sends data byte to be written to the address register.
Slave sends acknowledgement.
Write cycle ends when the master creates stop condition.

8.5.2.2.7 Control Register Read Cycle

Master device generates start condition.
Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).
Slave device sends acknowledge signal if the slave address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal if slave address is correct.
Master generates repeated start condition
Master sends the slave address (7 bits) and the data direction bit (r/w = “1”)
Slave sends acknowledgment if the slave address is correct.
Read cycle ends when master does not generate acknowledge signal after data byte and generates stop

8.6 Register Maps

Table 21. Register Map

(1) Unused bits data must not be changed. Table 22. EEPROM Register Map(1)

11 SLOW_PLL_DIV[12:5]

12 EN_SYNC PWM_SYNC

13 R_SELL[1:0] SEL_DIVIDER EN_PLL SYNC_PRE_DIVIDER[3:0]

14 RESERVED SYNC_TYPE PWM_FREQ[3:0]

16 RESERVED

18 BOOST_DRIVER_SIZE[1:0] EN_ADAP EN_JUMP BRIGHTNESS_JUMP_THRES[1:0] JUMP_STEP_SIZE[1:0]

19 RESERVED BOOST_INITIAL_VOLTAGE[5:0]

20 BOOST_SEL_LLC[1:0] BOOST_SEL_JITTER_FILTER[1:0

21 BOOST_OFFTIME_SEL[1:0] BOOST_BLANKTIME_SEL[1:0] RESERVED BOOST_VO_SLOPE_CTRL[2:0]

23 EXT_TEMP_LEVEL_HIGH[3:0] EXT_TEMP_LEVEL_LOW[3:0]

24 INT_TEMP_LIM[1:0] EXT_TEMP_PERIOD[4:0] EXT_TEMP_

8.6.1 Register Bit Explanations

8.6.1.1 Display/Cluster1 Brightness Control MSB

DISP_CL1_BRT MSB 7 6 5 4 3 2 1 0 DISP_CL1_BRT[15:8] Name Bit Access Description DISP_CL1_BRT[15:8] 7:0 R/W Backlight brightness control MSB

8.6.1.2 Display/Cluster1 Brightness Control LSB

DISP_CL1_BRT LSB 7 6 5 4 3 2 1 0 DISP_CL1_BRT[7:0] Name Bit Access Description DISP_CL1_BRT LSB 7:0 R/W Backlight brightness control LSB The DISP_CL1_BRT MSB register must be written first. New value is valid after writing DISP_CL1_BRT LSB. If output 1 is used in display mode, the Brightness/Cluster Output 1 Brightness Control register is used for all outputs in display mode (16-bits register). Otherwise it is the Brightness Control register for cluster output 1. For cluster bit control is 13 bit, most significant bit are used.

8.6.1.3 Display/Cluster1 Output Current MSB

Reset value loaded during start-up from EEPROM REG0 DISP_CL1_CURRENT MSB 7 6 5 4 3 2 1 0 RESERVED DISP_CL1_CURRENT[11:8] Name Bit Access Description DISP_CL1_CURRENT[11:8] 3:0 R/W Display/Cluster current control MSB

8.6.1.4 Display/Cluster1 Output Current LSB

Reset value loaded during start-up from EEPROM REG1 DISP_CL1_CURRENT LSB 7 6 5 4 3 2 1 0 DISP_CL1_CURRENT[7:0] Name Bit Access Description DISP_CL1_CURRENT[7:0] 7:0 R/W Display/Cluster current control LSB The DISP_CL1_CURRENT MSB register must be written first. New value is valid after writing DISP_CL1_CURRENT LSB. If one of few outputs is used in display mode, the DISP_CL1_CURRENT register is used for all outputs in display mode (12-bit), otherwise it is Cluster1 Output Current register. Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.

8.6.1.5 Cluster2 Brightness Control MSB

CL2_BRT MSB 7 6 5 4 3 2 1 0 RESERVED CL2_BRT[12:8] Name Bit Access Description CL2_BRT[12:8] 4:0 R/W Cluster output 2 brightness control MSB

8.6.1.6 Cluster2 Brightness Control LSB

CL2_BRT LSB 7 6 5 4 3 2 1 0 CL2_BRT[7:0] Name Bit Access Description CL2_BRT[7:0] 7:0 R/W Cluster output 2 brightness control LSB The CL2_BRT MSB register must be written first. New value is valid after writing CL2_BRT LSB.

8.6.1.7 Cluster2 Output Current

CL2_CURRENT 7 6 5 4 3 2 1 0 CL2_CURRENT[7:0] Name Bit Access Description CL2_CURRENT[7:0] 7:0 R/W Cluster output 2 current control Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.

8.6.1.8 Cluster3 Brightness Control MSB

CL3_BRT MSB 7 6 5 4 3 2 1 0 RESERVED CL3_BRT[12:8] Name Bit Access Description CL3_BRT[12:8] 4:0 R/W Cluster output 3 brightness control MSB

8.6.1.9 Cluster3 Brightness Control LSB

CL3_BRT LSB 7 6 5 4 3 2 1 0 CL3_BRT[7:0] Name Bit Access Description CL3_BRT[7:0] 7:0 R/W Cluster output 3 brightness control LSB The CL3_BRT MSB register must be written first. New value is valid after writing CL3_BRT LSB.

8.6.1.10 Cluster3 Output Current

CL3_CURRENT 7 6 5 4 3 2 1 0 CL3_CURRENT[7:0] Name Bit Access Description CL3_CURRENT[7:0] 7:0 R/W Cluster output 3 current control Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.

8.6.1.11 Cluster4 Brightness Control MSB

CL4_BRT MSB 7 6 5 4 3 2 1 0 RESERVED CL4_BRT[12:8] Name Bit Access Description CL4_BRT[12:8] 4:0 R/W Cluster output 4 brightness control MSB

8.6.1.12 Cluster4 Brightness Control LSB

CL4_BRT LSB 7 6 5 4 3 2 1 0 CL4_BRT[7:0] Name Bit Access Description CL4_BRT[7:0] 7:0 R/W Cluster output 4 brightness control LSB The CL4_BRT MSB register must be written first. New value is valid after writing CL4_BRT LSB.

8.6.1.13 Cluster4 Output Current

CL4_CURRENT 7 6 5 4 3 2 1 0 CL4_CURRENT[7:0] Name Bit Access Description CL4_CURRENT[7:0] 7:0 R/W Cluster output 4 current control Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.

8.6.1.14 Configuration

Reset value loaded during start-up from EEPROM CONFIGURATION 7 6 5 4 3 2 1 0 RESERVED DRV_LED_CURRENT_SCALE[2:0] EN_ADVANCED _SLOPE PWM_SLOPE[2:0] Name Bit Access Description DRV_LED_CURRENT_SCALE[2:0] 6:4 R/W Scales the maximum LED current when EN_EXT_LED_CUR_CTRL = 0 Effective for display and cluster mode. 000 = 25 mA 001 = 30 mA 010 = 50 mA 011 = 60 mA 100 = 80 mA 101 = 100 mA 110 = 120 mA 111 = 150 mA EN_ADVANCED_SLOPE 3 R/W Enable for advanced slope (smooth brightness change) 0 = Linear slope used only 1 = Advanced slope used PWM_SLOPE[2:0] 2:0 R/W Linear brightness sloping time (typical) 000 = 0 ms 001 = 1 ms 010 = 2 ms 011 = 52 ms 100 = 105 ms 101 = 210 ms 110 = 315 ms 111 = 511 ms

8.6.1.15 Status

RESERVED BRT_SLOPE_DONE TEMP_RES_MISSING EXT_TEMP_FLAG_L EXT_TEMP_FLAG_H Name Bit Access Description BRT_SLOPE_DONE 3 R Status bit for the brightness sloping 0 = Sloping ongoing 1 = Sloping done TEMP_RES_MISSING 2 R NTC sensor missing flag 0 = sensor OK 1 = NTC sensor missing EXT_TEMP_FLAG_L 1 R External temperature sensor low limit exceeded flag 0 = limit not detected 1 = low temperature limit detected EXT_TEMP_FLAG_H 0 R External temperature sensor high limit exceeded flaf 0 = limit not detected 1 = high temperature limit detected

8.6.1.16 Fault

RESERVED VIN_OVP VIN_UVLO TSD BOOST_OCP BOOST_OVP PL_FET_FAULT CP_2X_FAULT Name Bit Access Description VIN_OVP 6 R VIN overvoltage protection flag 0 = No fault 1 = Fault detected VIN_UVLO 5 R VIN undervoltage lockout flag 0 = No fault 1 = Fault detected TSD 4 R Thermal shutdown 0 = No flag 1 = Fault detected BOOST_OCP 3 R Boost overcurrent protection flag 0 = No flag 1 = Fault detected BOOST_OVP 2 R Boost output overvoltage protection flag 0 = No flag 1 = Fault detected PL_FET_FAULT 1 R VIN overcurrent protection flag 0 = No fault 1 = Fault detected CP_2X_FAULT 0 R Charge pump output voltage too low 0 = No fault 1 = Fault detected

8.6.1.17 LED Fault

RESERVED OPEN_LED SHORT_LED LED_FAULT[4:1] Name Bit Access Description OPEN_LED 5 R Open LED fault. 0 = No fault 1 = Fault detected SHORT_LED 4 R Short LED fault. 0 = No fault 1 = Fault detected LED_FAULT[4:1] 3:0 R Defines which string has either open or short fault. 0001 = LED OUT1 0010 = LED OUT2 0100 = LED OUT3 1000 = LED OUT4

8.6.1.18 Fault Clear

RESERVED CLEAR_FAULTS Name Bit Access Description CLEAR_FAULTS 0 W Write only bit, writing CLEAR_FAULTS high clears faults.

8.6.1.19 Identification

FULL_LAYER_REVISION[3:0] METAL REVISIONS[3:0] Name Bit Access Description FULL_LAYER_REVISION 7:4 R Manufacturer ID code – full layer revision METAL REVISIONS 3:0 R Manufacturer ID code – metal mask revision

8.6.1.20 Temp MSB

RESERVED TEMP[10:8] Name Bit Access Description TEMP[10:8] 2:0 R Device internal temperature sensor reading, first 3 MSB. MSB must be read before LSB, because reading of MSB register latches the data.

8.6.1.21 Temp LSB

TEMP[7:0] Name Bit Access Description TEMP[7:0] 7:0 R Device internal temperature sensor reading, last 8 LSB. MSB must be read before LSB, because reading of MSB register latches the data.

8.6.1.22 Display LED Current MSB

RESERVED LED_CURRENT[11:8] Name Bit Access Description LED_CURRENT[11:8] 3:0 R Display LED current value reading, first 3 MSB. DISP LED CURRENT MSB must be read before DISP LED CURRENT LSB, DISP LED PWM MSB, and DISP LED PWM LSB because reading of the MSB register latches the data for current and PWM.

8.6.1.23 Display LED Current LSB

LED_CURRENT[7:0] Name Bit Access Description LED_CURRENT[7:0] 7:0 R Display LED current value reading, last 8 LSB. Note: DISP LED CURRENT MSB latches the data for current and PWM.

8.6.1.24 Display LED PWM MSB

PWM[15:8] Name Bit Access Description PWM[7:0] 7:0 R Display LED current value reading, first 8 MSB. Note: DISP LED CURRENT MSB latches the data for current and PWM.

8.6.1.25 Display LED PWM LSB

PWM[7:0] Name Bit Access Description PWM[7:0] 7:0 R Display LED PWM reading, last 8 LSB. Note: DISP LED CURRENT MSB latches the data for current and PWM.

8.6.1.26 EEPROM Control

EE_READY RESERVED EE_PROG EE_READ Name Bit Access Description EE_READY 7 R EEPROM ready 0 = EEPROM programming or read in progress 1 = EEPROM ready, not busy EE_PROG 1 R/W EEPROM programming 0 = Normal operation 1 = Start the EEPROM programming sequence. Programs data currently in the EEPROM registers to non-volatile memory (NVM). EE_READ 0 R/W EEPROM read 0 = Normal operation 1 = Reads the data from NVM to the EEPROM registers. Can be used to restore default values if EEPROM registers are changed during testing. Programming sequence (program data permanently from registers to NVM): 1. Turn on the chip by setting VDDIO/EN pin high. 2. Unlock EEPROM by writing the unlock codes to register 0x1A. – Write 0x08 to address 0x1A – Write 0xBA to address 0x1A – Write 0xEF to address 0x1A 3. Write data to EEPROM registers (address 0x60… 0x78). 4. Write EE_PROG to high in address 0x19. (0x02 to address 0x19).

www.ti.com SNVSA21F –MAY 2014–REVISED JULY 2017 Product Folder Links: LP8860-Q1 Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated 5. Wait 200 ms. 6. Write EE_PROG to low in address 0x19. (0x00 to address 0x19). Read sequence (load data from NVM to registers): 1. Turn on the chip by writing setting VDDIO/EN pin high. 2. Unlock EEPROM by writing the unlock codes to register 0x1A. – Write 0x08 to address 0x1A – Write 0xBA to address 0x1A – Write 0xEF to address 0x1A 3. Write EE_READ to high in address 0x19. (0x01 to address 0x19). 4. Wait 1 ms. 5. Write EE_READ to low in address 0x19. (0x00 to address 0x19). NOTE EEPROM bits are intended to be set/programmed before normal operation only once during silicon production, but can be reprogrammed for evaluation purposes up to 1000 cycles.

8.6.1.27 EEPROM Unlock Code

EEPROM UNLOCK_CODE[7:0] Name Bit Access Description EEPROM_UNLOCK_CODE[7:0] 7:0 W Unlock EEPROM control register (0x19) and EEPROM registers. Writing 0x08, 0xBA, 0xEF sequence unlocks EEPROM registers. Lock is enabled again by writing any other code to the register.

8.6.2 EEPROM Bit Explanations

8.6.2.1 EEPROM Register 0

EXT_TEMP_MINUS[1:0] DRV_LED_BIAS_CTRL[1:0] LED_CURRENT_CTRL[11:8] Name Bit Access Description EXT_TEMP_MINUS[1:0] 7:6 R/W External temperature sensor current dimming knee point, see LED Current Dimming With Internal Temperature Sensor for details. 00 = 1 μA 01 = 5 μA 10 = 9 μA 11 = 13 μA DRV_LED_BIAS_CTRL[1:0] 5:4 R/W Controls the LED current sink bias current. Effects LED current sink rise time and current consumption. 150-mA LED current is suggested. 00 = slowest LED current sink setting and low Iq (typical 800-ns rise time / 200 μA per sink) 01 = slow (typical 400-ns rise time / 400 μA per sink) 10 = fast (typical 200-ns rise time / 800 μA per sink) 11 = fastest LED current sink and higher current consumption (typical100-ns rise time / 1.6 mA per sink) LED_CURRENT_CTRL[11:8] 3:0 R/W MSB bits for 12-bit LED current control. Step size is 150 mA / 4095 = 36.63 µA (typical) when max current is set to 150 mA. Max current can be scaled with RISET resistor or with DRV_LED_CURRENT_SCALE EEPROM bits. 000h = 0 mA 001h = 0.037 mA 002h = 0.073 mA 003h = 0.110 mA FFEh = 149.963 mA FFFh = 150.000 mA

8.6.2.2 EEPROM Register 1

LED_CURRENT_CTRL[7:0] Name Bit Access Description LED_CURRENT_CTRL[7:0] 7:0 R/W LSB bits for 12-bit LED current control. Step size is 150 mA / 4095 = 36.63 µA when max current is set to 150 mA. Max current can be scaled with RISET resistor or with DRV_LED_CURRENT_SCALE EEPROM bits. 000h = 0 mA 001h = 0.037 mA 002h = 0.073 mA 003h = 0.110 mA FFEh = 149.963 mA FFFh = 150.000 mA

8.6.2.3 EEPROM Register 2

RESERVED EN_STEADY_DITHER PWM_INPUT_HYSTERESIS[1:0] EN_ADVANCED_SLOPE PWM_SLOPE[2:0] Name Bit Access Description EN_STEADY_DITHER 6 R/W Enable dithering in steady state condition 0 = Disabled, dithering used in sloping (brightness changes) only 1 = Enabled, dithering used in sloping as well as steady-state condition. Dithering defined with DITHER[2:0] bits. PWM_INPUT_HYSTERESIS[1:0] 5:4 R/W PWM input hysteresis function. Defines how small changes in the PWM input are ignored. Hysteresis used to remove constant switching between two values. 00 = ±1-step hysteresis with 16-bit resolution 01 = ±8-step hysteresis with 16-bit resolution 10 = ±16-step hysteresis with 16-bit resolution 11 = ±256-step hysteresis with 16-bit resolution EN_ADVANCED_SLOPE 3 R/W Advanced smooth slope for brightness changes 0 = Advanced slope is disabled 1 = Use advanced slope for brightness change to make brightness changes smooth for eye PWM_SLOPE[2:0] 2:0 R/W Linear brightness sloping time (typical) 000 = Slope function disabled, immediate brightness change 001 = 1 ms 010 = 2 ms 011 = 52 ms 100 = 105 ms 101 = 210 ms 110 = 315 ms 111 = 511 ms

8.6.2.4 EEPROM Register 3

EN_DISPLAY_LED_FAULT DRV_LED_CURRENT_SCALE[2:0] LED_STRING_CONF[2:0] EN_PWM_I Name Bit Access Description EN_DISPLAY_LED_FAULT 7 R/W 0 = LED open/short faults disabled 1 = LED open/short faults enabled DRV_LED_CURRENT_SCALE[2:0] 6:4 R/W Scales the maximum LED current when EN_EXT_LED_CUR_CTRL = 0 Effective for both modes – display and cluster. 000 = 25 mA 001 = 30 mA 010 = 50 mA 011 = 60 mA 100 = 80 mA 101 = 100 mA 110 = 120 mA 111 = 150 mA LED_STRING_CONF[2:0] 3:1 R/W LED current sink configuration 000 = 4 separate LED strings with 90° phase shift 001 = 3 separate LED strings with 120° phase shift (String 4 in cluster mode or not used) 010 = 2 separate LED strings with 180° phase shift (Strings 3 and 4 in cluster mode or not used) 011 = 1 LED string. (Strings 2,3 and 4 in cluster mode or not used) 100 = 2 LED strings (1+2, 3+4) with 180° phase shift. Tied strings with same phase. 101 = 1 LED string (1+2+3+4). Tied strings with same phase 110 = 1 LED string (1+2). 1st and 2nd strings tied with same phase, strings 3 and 4 are in cluster mode or not used 111 = All strings are used in cluster mode EN_PWM_I 0 R/W Enable Hybrid PWM and Current dimming mode 0 = Disabled, dimming only with PWM 1 = Enabled

8.6.2.5 EEPROM Register 4

EN_CL_LED_FAULT DRV_LED_COMP_HYST[1:0] DRV_LED_FAULT_THR[1:0] DRV_HEADER[2:0] Name Bit Access Description EN_CL_LED_FAULT 7 R/W Enable open/short LED fault for cluster strings 0 = LED fault in cluster mode disabled 1 = LED fault in cluster mode enabled DRV_LED_COMP_HYST[1:0] 6:5 R/W LED comparator hysteresis – difference between mid and low comparator, used for boost adaptive voltage control (boost high level) 00 = 1000 mV 01 = 750 mV 10 = 500 mV 11 = 250 mV DRV_LED_FAULT_THR[1:0] 4:3 R/W LED Fault thresholds, used for short LED detection. 00 = 3.6 V 01 = 3.6 V 10 = 6.9 V 11 = 10.6 V DRV_HEADER[2:0] 2:0 R/W LED current sink headroom control, used for boost adaptive voltage control (boost low level) and open LED detection. VSAT is the saturation voltage of the sink, typically 500 mV with 150- mA current. 111 = VSAT + 50 mV 110 = VSAT + 175 mV 101 = VSAT + 300 mV 100 = VSAT + 450 mV 011 = VSAT + 575 mV 010 = VSAT + 700 mV 001 = VSAT + 875 mV 000 = VSAT + 1000 mV

8.6.2.6 EEPROM Register 5

I_SLOPE[2:0] PWM_RESOLUTION[1:0] DITHER[2:0] Name Bit Access Description I_SLOPE[2:0] 7:5 R/W Slope gain adjusts the current slope for Hybrid PWM and Current dimming mode 000 = 1.000 001 = 1.023 010 = 1.047 011 = 1.070 100 = 1.094 101 = 1.117 110 = 1.141 111 = 1.164 PWM_RESOLUTION[1:0] 4:3 R/W For PWM clocking with internal oscillator (VSYNC is not used) these bits control the PLL multiplier and hence the PWM output resolution 00 = 5-MHz clock used for generating PWM 01 = 10-MHz clock used for generating PWM 10 = 20-MHz clock used for generating PWM 11 = 40-MHz clock used for generating PWM DITHER[2:0] 2:0 R/W Dither function controls 000 = Dither function disabled 001 = 1-bit dither 010 = 2-bit dither 011 = 3-bit dither 1XX = 4-bit dither

8.6.2.7 EEPROM Register 6

RESERVED GAIN_CTRL[2:0] EN_EXT_LED_CUR_CTRL DRV_EN_SPLIT_FET BRT_MODE[1:0] Name Bit Access Description GAIN_CTRL[2:0] 6:4 R/W Switch point from PWM to current control for Hybrid PWM and Current dimming mode 000 = 50.0% 001 = 40.6% 010 = 31.3% 011 = 25.0% 100 = 21.9% 101 = 18.8% 110 = 15.6% 111 = 12.5% EN_EXT_LED_CUR_CTRL 3 R/W Enable LED current set resistor 0 = Resistor is disabled and current is scaled with SCALE[2:0] EEPROM register bits 1 = Enable LED current set resistor. LED current is scaled by the RISET resistor DRV_EN_SPLIT_FET 2 R/W LED current sink FET control 0 = big size FET is driving LED current 1 = enable use of smaller FET for driving low LED output currents. Smaller FET is selected automatically when current setting is below 1/16 of the scale. Automatic scaling improves accuracy for output currents below 1/16 of the full current scale. BRT_MODE[1:0] 1:0 R/W Brightness control mode 00 = PWM input pin duty cycle control 01 = PWM input duty x Brightness register 10 = Brightness register 11 = Direct PWM control from PWM input pin

8.6.2.8 EEPROM Register 7

DRV_OUT2_CORR[3:0] DRV_OUT1_CORR[3:0] Name Bit Access Description DRV_OUT2_CORR[3:0] 7:4 R/W Current correction for OUT2 LED current sink 0000 = 6.5% 0001 = 5.6% 0010 = 4.7% 0011 = 3.7% 0100 = 2.8% 0101 = 1.9% 0110 = 0.9% 0111 = 0.0% 1000 = –0.9% 1001 = –1.9% 1010 = –2.8% 1011 = –3.7% 1100 = –4.7% 1101 = –5.6% 1110 = –6.5% 1111 = –7.4%

SNVSA21F –MAY 2014–REVISED JULY 2017 www.ti.com Product Folder Links: LP8860-Q1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Name Bit Access Description DRV_OUT1_CORR[3:0] 3:0 R/W Current correction for OUT1 LED current sink 0000 = 6.5% 0001 = 5.6% 0010 = 4.7% 0011 = 3.7% 0100 = 2.8% 0101 = 1.9% 0110 = 0.9% 0111 = 0.0% 1000 = –0.9% 1001 = –1.9% 1010 = –2.8% 1011 = –3.7% 1100 = –4.7% 1101 = –5.6% 1110 = –6.5% 1111 = –7.4%

8.6.2.9 EEPROM Register 8

DRV_OUT4_CORR[3:0] DRV_OUT3_CORR[3:0] Name Bit Access Description DRV_OUT4_CORR[3:0] 7:4 R/W Current correction for OUT4 LED current sink 0000 = 6.5% 0001 = 5.6% 0010 = 4.7% 0011 = 3.7% 0100 = 2.8% 0101 = 1.9% 0110 = 0.9% 0111 = 0.0% 1000 = –0.9% 1001 = –1.9% 1010 = –2.8% 1011 = –3.7% 1100 = –4.7% 1101 = –5.6% 1110 = –6.5% 1111 = –7.4% DRV_OUT3_CORR[3:0] 3:0 R/W Current correction for OUT3 LED current sink 0000 = 6.5% 0001 = 5.6% 0010 = 4.7% 0011 = 3.7% 0100 = 2.8% 0101 = 1.9% 0110 = 0.9% 0111 = 0.0% 1000 = –0.9% 1001 = –1.9% 1010 = –2.8% 1011 = –3.7% 1100 = –4.7% 1101 = –5.6% 1110 = –6.5% 1111 = –7.4%

8.6.2.10 EEPROM Register 9

EXT_TEMP_GAIN[3:0] BL_COMP_FILTER_SEL[3:0] Name Bit Access Description EXT_TEMP_GAIN[3:0] 7:4 R/W External temperature sensor current dimming gain control, see LED Current Dimming With Internal Temperature Sensor for details. BL_COMP_FILTER_SEL[3:0] 3:0 R/W Filter selects how many PWM generator clock cycles high/mid comparator is filtered before it is used to detect shorted LEDs and boost voltage down scaling. 0000 = 5 0001 = 10 0010 = 20 0011 = 40 0100 = 60 0101 = 80 0110 = 100 0111 = 140 1000 = 180 1001 = 220 1010 = 260 1011 = 300 1100 = 340 1101 = 380 1110 = 420 1111 = 460

8.6.2.11 EEPROM Register 10

EXT_TEMP_I_DIMMING_ EN NMOS_PLFET_EN SOFT_START_SEL[1:0] PL_SD_LEVEL[1:0] PL_SD_SINK_LEVEL[1:0] Name Bit Access Description EXT_TEMP_I_DIMMING_EN 7 R/W External temperature sensor current dimming enabled 0 = disabled 1 = enabled NMOS_PLFET_EN 6 R/W Powerline FET selection: 0 = pFET 1 = nFET SOFT_START_SEL[1:0] 5:4 R/W Soft-start time selection 00 = 5 ms 01 = 10 ms 10 = 20 ms 11 = 50 ms PL_SD_LEVEL[1:0] 3:2 R/W Power-line FET current limit selection VIN OCP (assumed RISENSE = 20 mΩ). 10 = 6 A 11 = 8 A PL_SD_SINK_LEVEL[1:0] 1:0 R/W Power-line FET gate current NMOS_PLFET_EN = 0 (current for normal mode) NMOS_PLFET_EN = 1 (current for fault recovery mode, otherwise 0mA) 00 55 µA 0.3 mA 01 110 µA 0.5 mA 10 220 µA 1.0 mA 11 440 µA 2.2 mA

8.6.2.12 EEPROM Register 11

SLOW_PLL_DIV[12:5] Name Bit Access Description SLOW_PLL_DIV[12:5] 7:0 R/W Divider for VSYNC operation. 8 MSB bits

8.6.2.13 EEPROM Register 12

EN_SYNC PWM_SYNC PWM_COUNTER_RESET SLOW_PLL_DIV[4:0] Name Bit Access Description EN_SYNC 7 R/W VSYNC input enable 0 = VSYNC input disabled 1 = VSYNC input enabled PWM_SYNC 6 R/W Enable PWM generation synchronization to VSYNC signal 0 = Disabled 1 = Enabled. PWM output used for phase detector input after dividing with SLOW_PLL_DIV divider PWM_COUNTER_RESET 5 R/W Enable PWM generator resetting on VSYNC signal rising edge 0 = Disabled 1 = Enabled SLOW_PLL_DIV[4:0] 4:0 R/W Divider for VSYNC operation. 5 LSB bits

8.6.2.14 EEPROM Register 13

R_SEL[1:0] SEL_DIVIDER EN_PLL SYNC_PRE_DIVIDER[3:0] Name Bit Access Description R_SEL[1:0] 7:6 R/W Coefficient for the slow PLL divider 00 = 16 01 = 32 10 = 64 11 = 128 SEL_DIVIDER 5 R/W PLL divider selection 0 = Slow PLL divider with external compensation (when using VSYNC) 1 = Fast PLL divider with internal compensation (when using 5-MHz internal clock) EN_PLL 4 R/W PLL enable 0 = PLL disabled and internal 5-MHz oscillator used for PWM generation 1 = PLL is used for generating the PWM generation clock from the internal oscillator or VSYNC signal SYNC_PRE_DIVIDER[3:0] 3:0 R/W VSYNC signal pre-divider from 1 to 16. Used when VSYNC frequency is higher than PWM output frequency.

8.6.2.15 EEPROM Register 14

RESERVED SYNC_TYPE PWM_FREQ[3:0] Name Bit Access Description SYNC_TYPE 4 R/W Type of the VSYNC input. Affects the PLL functionality. 0 = HSYNC (50 to 150 kHz) 1 = VSYNC (50 to 150 Hz) PWM_FREQ[3:0] 3:0 R/W PWM output frequency setting when internal oscillator is used. See Brightness Control (Display Mode)

8.6.2.16 EEPROM Register 15

MASK_BOOST_OVP_ STATUS MASK_BOOST_OCP _FSM MASK_OVP_FSM MASK_VIN_UVLO UVLO_LEVEL[1:0] OVP_LEVEL[1:0] Name Bit Access Description MASK_BOOST_OVP_STATUS 7 R/W Boost overvoltage protection enable 0 = Enabled 1 = Fault bit and FAULT pin disabled. MASK_BOOST_OCP_FSM 6 R/W Boost overcurrent protection fault recovery state enable 0 = Enabled 1 = Entering fault recovery state disabled. Fault bit and FAULT pin operate normally. MASK_OVP_FSM 5 R/W VIN overvoltage fault recovery state enable 0 = Enabled 1 = Entering fault recovery state disabled. Fault bit and FAULT pin operate normally. MASK_VIN_UVLO 4 R/W VIN undervoltage lockout fault recovery state enable 0 = Enabled 1 = Entering fault recovery state disabled. Fault bit and FAULT pin operate normally. UVLO_LEVEL[1:0] 3:2 R/W VIN Undervoltage protection thresholds (UVLO) 00 = disabled 01 = 3 V 10 = 5 V 11 = 8 V OVP_LEVEL[1:0] 1:0 R/W VIN Overvoltage protection thresholds (OVP) 00 = disabled 01 = 7 V 10 = 11 V 11 = 22.5 V

8.6.2.17 EEPROM Register 16

RESERVED BOOST_EN_IRAMP_DELAY BOOST_EXT_CLK_SEL BOOST_IMAX_SEL[2:0] BOOST_GD_VOLT Name Bit Access Description BOOST_EN_IRAMP_DELAY 5 R/W Boost current ramp delay enable (for adjusting conversion ratio/stability, 35% of period) 1 = Delay enabled 0 = Delay disabled BOOST_EXT_CLK_SEL 4 R/W Boost clock selection 0 = Internal clock 1 = External clock (SYNC pin) If external clock selected and sync disappears for 1.5… 2 periods, boost automatically switches to using internal oscillator with frequency defined by BOOST_FREQ_SEL[2:0] BOOST_IMAX_SEL[2:0] 3:1 R/W Maximum current limit for boost SW mode. Values below based on 25-mΩ sense resistor value. 000 = 2 A 001 = 3 A 010 = 4 A 011 = 5 A 100 = 6 A 101 = 7 A 110 = 8 A 111 = 9 A BOOST_GD_VOLT 0 R/W Boost gate driver voltage selection 1 = Charge pump output (VGATE DRIVER > 6 V) 0 = VDD

8.6.2.18 EEPROM Register 17

BOOST_EN_SPREAD_ SPECTRUM BOOST_SEL_IND[1:0] BOOST_SEL_IRAMP[1:0] BOOST_FREQ_SEL[2:0] Name Bit Access Description BOOST_EN_SPREAD_ SPECTRUM 7 R/W Boost spread spectrum (±3% from central frequency, 1.875 kHz modulation frequency) enable 0 = Spread spectrum disabled 1 = Spread spectrum enabled BOOST_SEL_IND[1:0] 6:5 R/W See BOOST_SEL_IRAMP for selecting BOOST_SEL_IND setting BOOST_SEL_IRAMP[1:0] 4:3 R/W Boost artificial current ramp peak value, A/s. Select value higher than IRAMP_GAIN: IRAMP_GAIN =1.2 x 0.5 x (VOUTmax - VINmin)/(0.7 x L x 60000), where VIN, VOUT are boost input and output voltage, L - inductance, H. 25-mΩ RSENSE is suggested. BOOST_SEL_IND[1:0] BOOST_SEL_IRAMP [1:0] 00 01 10 11 00 130 65 34 29 01 88 43 23 20 10 56 28 15 13 11 37 18 10 8.5 BOOST_FREQ_SEL[2:0] 2:0 R/W BOOST_EXT_CLK_SEL=0 Boost output frequency selection (internal oscillator) 000= 100 kHz 001 = 200 kHz 010 = 303 kHz 011 = 400 kHz 100 = 629 kHz 101 = 800 kHz 110 = 1100 kHz 111 = 2200 kHz BOOST_EXT_CLK_SEL=1 Boost output frequency selection (for external sync mode if external sync disappears) 000= 100 kHz 001 = 200 kHz 010 = 303 kHz 011 = 400 kHz 100 = 625 kHz 101 = 833 kHz 110 = 1111 kHz 111 = 2500 kHz

8.6.2.19 EEPROM Register 18

BOOST_DRIVER_SIZE[1:0] EN_ADAP EN_JUMP BRIGHTNESS_JUMP_THRES[1:0] JUMP_STEP_SIZE[1:0] Name Bit Access Description BOOST_DRIVER_SIZE[1:0] 7:6 R/W Boost gate driver scaling. Affects gate driver peak current and SW node voltage rise/fall times 00 = 0.4/0.45 A (typical) peak sink/source current 01 = 0.75/0.87 A (typical) peak sink/source current 10 = 1.2/1.3 A (typical) peak sink/source current 11 = 1.5/1.7 A (typical) peak sink/source current EN_ADAP 5 R/W Enable boost converter adaptive mode 0 = adaptive mode disabled, boost converter output voltage is set with BOOST_INITIAL_VOLTAGE EEPROM register bits. 1 = adaptive mode enabled. Boost converter start-up voltage is set with BOOST_INITIAL_VOLTAGE EEPROM register bits. Further boost voltage is adapted to the highest LED string VF. If all LED outputs are in cluster mode, adaptive mode is disabled automatically. EN_JUMP 4 R/W Enable large boost voltage jump command for the fast brightness increase. 0 = Normal steps used for boost voltage control 1 = Jump command allowed in boost voltage control BRIGHTNESS_JUMP_THRES[1:0] 3:2 R/W Defines the magnitude of the input brightness change after which jump command is given. 00 = Jump command after 10% brightness change 01 = Jump command after 30% brightness change 10 = Jump command after 50% brightness change 11 = Jump command after 70% brightness change JUMP_STEP_SIZE[1:0] 1:0 R/W Boost control step size that jump command increases backlight boost output voltage 00: 8 steps (1.0 V typ) 01: 16 steps (2.0 V typ) 10: 32 steps (4.0 V typ) 11: 64 steps (8.0 V typ)

8.6.2.20 EEPROM Register 19

RESERVED BOOST_INITIAL_VOLTAGE[5:0] Name Bit Access Description BOOST_INITIAL_VOLTAGE[5:0] 5:0 R/W Boost voltage control from 16 V to 47.5 V with 0.5 V step (without FB resistive divider). When resistive divider is used on the FB pin, the voltages are scaled accordingly. If adaptive boost control is enabled, this sets the initial start voltage for the boost converter. If adaptive mode is disabled, this sets the output voltage of the boost converter. 000000 = 16.0 V (typical) 000001 = 16.5 V (typical) 000010 = 17.0 V (typical) 000011 = 17.5 V (typical) 000100 = 18.0 V (typical) ... 111100 = 46.0 V (typical) 111101 = 46.5 V (typical) 111110 = 47.0 V (typical) 111111 = 47.5 V (typical)

8.6.2.21 EEPROM Register 20

BOOST_SEL_LLC[1:0] BOOST_SEL_JITTER_FILTER[1:0] BOOST_SEL_I[1:0] BOOST_SEL_P[1:0] Name Bit Access Description BOOST_SEL_LLC[1:0] 7:6 R/W Light load comparator control. Selects boost PFM entry threshold (compensator current) 00 = 5 μA (boost switches from PFM to PWM early at light loads) 01 = 10 μA 10 = 15 μA 11 = 20 μA (boost operates in PFM mode to higher loads) BOOST_SEL_JITTER_FILTER[1:0] 5:4 R/W Boost jitter filter selection 00 = bypass 01 = 300 kHz 10 = 60 kHz 11 = 30 kHz BOOST_SEL_I[1:0] 3:2 R/W Boost PI compensator control: integral part 00 = 1 01 = 2 10 = 3 11 = 4 BOOST_SEL_P[1:0] 1:0 R/W Boost PI compensator control: proportional part 00 = 1 01 = 2 10 = 3 11 = 4

8.6.2.22 EEPROM Register 21

BOOST_OFFTIME_SEL[1:0] BOOST_BLANKTIME_SEL[1:0] RESERVED BOOST_VO_SLOPE_CTRL[2:0] Name Bit Access Description BOOST_OFFTIME_SEL[1:0] 7:6 R/W Boost time off selection 00 = 131 ns 01 = 68 ns 10 = 38 ns 11 = 24 ns BOOST_BLANKTIME_SEL[1:0] 5:4 R/W Boost blank time selection 00 = 162 ns 01 = 88 ns 10 = 63 ns 11 = 40 ns BOOST_VO_SLOPE_CTRL[2:0] 2:0 R/W Sets the speed for boost output voltage scaling up or down 000 = 1 (every PWM cycle) 001 = 2 (every other PWM cycle) 010 = 3 (every third PWM cycle) 011 = 4 (every 4th PWM cycle) 100 = 5 (every 5th PWM cycle) 101 = 6 (every 6th PWM cycle) 110 = 8 (every 8th PWM cycle) 111 = 16 (every 16th PWM cycle)

8.6.2.23 EEPROM Register 22

VDD_UVLO_ LEVEL RESERVED CP_2X_CLK[1:0] CP_2X_EN SQW_PULSE_ GEN_EN Name Bit Access Description VDD_UVLO_LEVEL 7 R/W VDD UVLO protection level 0 = 2.5 V 1 = 3.0 V Voltage hysteresis typically 50 mV. 2.5V level can be used if PLL frequency up to 20 MHz. With higher PLL frequency logic is not specified to work down to 2.5 V VDD CP_2X_CLK[1:0] 3:2 R/W Charge pump clock frequency 00 = 104 kHz 01 = 208 kHz 10 = 417 kHz 11 = 833 kHz CP_2X_EN 1 R/W Charge pump enable. CP is enabled at soft start if CP_2X_EN EEPROM bit asserted. 0 = disabled 1 = enabled SQW_PULSE_GEN_EN 0 R/W External charge pump clock enable (50% duty cycle 100 kHz). Clock connected to SQW pin. SQW clock enabled at soft start. 0 = disabled 1 = enabled

8.6.2.24 EEPROM Register 23

EXT_TEMP_LEVEL_HIGH[3:0] EXT_TEMP_LEVEL_LOW[3:0] Name Bit Access Description EXT_TEMP_LEVEL_HIGH[3:0] 7:4 R/W High external temperature sensor limit, kΩ 0000 = 79.67 0001 = 43.35 0010 = 29.77 0011 = 22.67 0100 = 18.30 0101 = 15.34 0110 = 13.21 0111 = 11.60 1000 = 10.34 1001 = 9.32 1010 = 8.49 1011 = 7.79 1100 = 7.20 1101 = 6.69 1110 = 6.25 1111 = 5.87 EXT_TEMP_LEVEL_LOW[3:0] 3:0 R/W Low external temperature sensor limit, kΩ 0000 = 79.67 0001 = 43.35 0010 = 29.77 0011 = 22.67 0100 = 18.30 0101 = 15.34 0110 = 13.21 0111 = 11.60 1000 = 10.34 1001 = 9.32 1010 = 8.49 1011 = 7.79 1100 = 7.20 1101 = 6.69 1110 = 6.25 1111 = 5.87

8.6.2.25 EEPROM Register 24

INT_TEMP_LIM[1:0] EXT_TEMP_PERIOD[4:0] EXT_TEMP_COMP_EN Name Bit Access Description INT_TEMP_LIM[1:0] 7:6 R/W Internal temperature sensor brightness thermal de-rating starting level. Thermal de-rating function temperature threshold: 00 = thermal de-rating function disabled 01 = 90°C 10 = 100°C 11 = 110°C EXT_TEMP_PERIOD[4:0] 5:1 R/W Step time for temperature limitation with external sensor 00000 = 2 s 00001 = 4 s 00010 = 6 s 00011 = 8 s 00100 = 10 s 00101 = 12 s 00110 = 14 s 00111 = 16 s 01000 = 18 s 01001 = 20 s 01010 = 22 s 01011 = 24 s 01100 = 26 s 01101 = 28 s 01110 = 30 s 01111 = 32 s 11110 = 62 s 11111 = 64 s EXT_TEMP_COMP_EN 0 R/W External temperature sensor (NTC) enable 0 = disabled 1 = enabled

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

the car battery. The device is internally powered from the VDD pin, and voltage must be in 3-V to 5.5-V range. driver. The charge pump is configured by EEPROM. The LP8860-Q1 can be used as a stand-alone device, using only the VDDIO/EN pin and the PWM signal. Alternatively, the device can be a part of system, connected to a microprocessor by an SPI or I2C interface. up to 48 V (typical) without external feedback divider in adaptive voltage control mode. protected by external components to prevent overvoltage.

9.2 Typical Applications

9.2.1 Typical Application for Display Backlight

Figure 53. VDD = 5 V, I2C, 4 LED Outputs in Display Mode

9.2.1.1 Design Requirements

Table 23. EEPROM Setting Example

ISAT > x(VOUT - VIN) VOUT VIN Where D = Where IRIPPLE = (2 x L x f) DQG'¶= (1 - D)(VOUT ± VIN) (VOUT ) + IRIPPLE IOUTMAX '¶ For Boost LP8860-Q1 SNVSA21F –MAY 2014–REVISED JULY 2017 www.ti.com Product Folder Links: LP8860-Q1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Inductor Selection

There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferable. The saturation current must be greater than the sum of the maximum load current and the worst case average- to-peak inductor current. The equation below shows the worst case conditions.

IRIPPLE: peak inductor current
IOUTMAX: maximum load current
VIN: minimum input voltage in application
L: min inductor value including worst case tolerances
f: minimum switching frequency
VOUT: output voltage
D: Duty Cycle for CCM Operation
VOUT: Output Voltage (9) As a result the inductor must be selected according to the ISAT. A more conservative and recommended approach is to choose an inductor that has a saturation current rating greater than the maximum switch current limit defined by <BOOST_IMAX_SEL[2:1]> EEPROM bits. A 22-µH to 33-µH inductor with a saturation current rating of at least 9 A is recommended for most applications. The inductor resistance must be less than 300 mΩ for good efficiency. See detailed information in Texas Instruments Application Note Understanding Boost Power Stages in Switch Mode Power Supplies (SLVA061). “Power Stage Designer™ Tools” can be used for the boost calculation: http://www.ti.com/tool/powerstage-designer.

9.2.1.2.2 Output Capacitor Selection

A ceramic capacitor with a 100-V voltage rating is recommended for the output capacitor. The DC-bias effect can reduce the effective capacitance by up to 80%, a consideration for capacitance value selection. Effectively the capacitance must be 33 µF for 600-mA loads. A different option is to use an aluminum electrolytic capacitor with low ESR and ceramic capacitor in parallel. Typically a 33-µF (ESR < 500 mΩ) with 10-µF (effective) ceramic capacitor in parallel is sufficient. If ESR is lower, capacitance for ceramic capacitor can be decreased. For higher switching frequency (2.2 MHz) and boost output current below 400 mA, two 10-µF ceramic capacitors in parallel are sufficient.

9.2.1.2.3 Input Capacitor Selection

A ceramic capacitor with 50-V voltage rating is recommended for the input capacitor. The DC-bias effect can reduce the effective capacitance by up to 80%, a consideration for capacitance value selection. Effectively the capacitance must be 33 µF for 600-mA loads. A different option is to use an aluminum electrolytic capacitor with low ESR and ceramic capacitor in parallel. Typically a 33-µF (ESR < 500 mΩ) with 10-µF (effective) ceramic capacitor in parallel is sufficient. If ESR is lower, capacitance for ceramic capacitor can be decreased. For higher switching frequency (2.2 MHz) and boost output current below 400 mA two 10-µF ceramic capacitors in parallel are sufficient.

9.2.1.2.4 Charge Pump Output Capacitor

A ceramic capacitor with at least 16-V voltage rating is recommended for the output capacitor of the charge pump. The DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance value selection. Typically a 10-µF capacitor is sufficient.

9.2.1.2.5 Charge Pump Flying Capacitor

A ceramic capacitor with at least 10-V voltage rating is recommended for the flying capacitor of the charge pump. Typically 1-µF capacitor is sufficient.

9.2.1.2.6 Diode

efficiency. Choose a reverse breakdown voltage of the Schottky diode significantly larger than the output voltage. and the load regulation to suffer.

9.2.1.2.7 Boost Converter Transistor

FET is VDD or about 2 x VDD, if the charge pump is enabled (EEPROM selection).

9.2.1.2.8 Boost Sense Resistor

from the inductor current and sense resistor resistance value.

9.2.1.2.9 Power Line Transistor

A pFET transistor with necessary voltage rating (VDS at least 5 V higher than max input voltage) must be used. the nFET as a power-line FET.

9.2.1.2.10 Input Current Sense Resistor

from the input current and sense resistor resistance value.

9.2.1.2.11 Filter Component Values

filter must be used only when external VSYNC is used; otherwise, the LP8860-Q1 uses internal compensation. Figure 54. Filter Components

Table 24. Filter Components Selection Figure 55. Critical Components for Design

Table 25. Bill of Materials for Design Example

9.2.1.3 Application Performance Plots

Figure 56. Voltage of LED Outputs Showing Phase-Shift Figure 57. Typical Start-up Figure 58. Slope with Phase-Shift Mode Figure 59. Slope With Hybrid Dimming and Phase Shift

9.2.2 Low VDD Voltage and Combined Output Mode Application

pump for gate driver powering is enabled. Figure 60. VDD = 3.3V, SPI, 2 Outputs in Display Mode,

9.2.2.1 Design Requirements

Table 26. EEPROM Setting Example

9.2.2.2 Detailed Design Procedure

See Detailed Design Procedure.

9.2.2.3 Application Performance Plots

See Application Performance Plots.

9.2.3 High Output Voltage Application

extra rail voltage for the transistor gates, if necessary voltage is not available in the system. Figure 61. VDD = 5 V, I2C, High-Voltage Output with Output Protection FETs Circuits

9.2.3.1 Design Requirements

Table 27. EEPROM Setting Example

10 LEDs per string, ƒLED_PWM= 10 kHz

9.2.3.2 Detailed Design Procedure

See Detailed Design Procedure.

9.2.3.3 Application Performance Plots

See Application Performance Plots.

9.2.4 High Output Current Application

2 outputs together. All 4 outputs connected together can drive up to a 600-mA LED string.

Figure 62. Two Channels at 300 mA/String, VDD = 3.3 V, SPI

9.2.4.1 Design Requirements

Table 28. EEPROM Setting Example

9.2.4.2 Detailed Design Procedure

See Detailed Design Procedure.

9.2.4.3 Application Performance Plots

See Application Performance Plots.

9.2.5 Three-Channel Configuration Without Serial Interface

programmed for brightness dimming with external PWM. LED current dimming with external NTC sensor is used in this application to protect LEDs against over-heating. Figure 63. Three-Channel Configuration without Serial Interface

9.2.5.1 Design Requirements

Table 29. EEPROM Setting Example

9.2.5.2 Detailed Design Procedure

NTC sensor with characteristic shown in Figure 64. Figure 64. NTC Sensor Resistance vs Temperature Figure 65. LED Current De-rating vs Temperature

9.2.5.3 Application Performance Plots

See Application Performance Plots.

9.2.6 Solution With Minimum External Components

current sensing. External synchronization functions are disabled. Figure 66. Solution With Minimum External Components

9.2.6.1 Design Requirements

Table 30. EEPROM Setting Example

10 Power Supply Recommendations

additional bulk capacitance may be required in addition to normal input capacitor .

11 Layout

11.1 Layout Guidelines

Figure 67 shows a layout recommendation for the LP8860-Q1. Figure 67 is used to show the principles of good layout. This layout can be adapted to the actual application layout if and where possible. It is important that all boost components are close to each other and to the device; the high-current traces must be wide enough. VDD must be as noise-free as possible. Place a VDD bypass capacitor near the pin and ground it to a noise-free ground. A charge-pump capacitor and boost input and output capacitors must be connected to PGND. Here are some main points to help the PCB layout work:

Current loops need to be minimized: – For low frequency the minimal current loop can be achieved by placing the boost components as close to each other as possible. Input and output capacitor grounds need to be close to each other to minimize current loop size. – Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High frequency return currents try to find route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the positive current route in the ground plane, if the ground plane is intact under the route. – For high frequency the copper area capacitance must be taken into account. For example, the copper area for the drain of boost nMOSFET is a tradeoff between capacitance and components cooling capacity.
GND plane must be intact under the high current boost traces to provide shortest possible return path and smallest possible current loops for high frequencies.
Current loops when the boost switch is conducting and not conducting must be in the same direction in optimal case.
Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating the inductor 180° changes current direction.
Use separate power and noise-free grounds. The power ground is used for boost converter return current and noise-free ground for more sensitive signals, like VDD bypass capacitor grounding as well as grounding the GND pins of the LP8860-Q1 itself.
Boost output feedback voltage to LEDs need to be taken out after the output capacitors, not straight from the diode cathode.
A small (for example, 39-pF) bypass capacitor must be placed close to the FB pin to suppress high frequency noise
VDD line must be separated from the high current supply path to the boost converter to prevent high frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD pin, and it is grounded to noise-free ground.
Capacitor connected to charge pump output CPUMP must have 10-µF capacitance, grounded by shortest way to boost switch current sensing resistor. This capacitor must be as close as possible to CPUMP pin. This capacitor provides a greater peak current for gate driver and must be used even if the charge pump is disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.
Input and output capacitors need strong grounding (wide traces, many vias to PGND plane).
If two or more output capacitors are used, symmetrical layout must be used to get all capacitors working ideally.
Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to become unstable on some loads. DC bias characteristics need to be obtained from the component manufacturer; it is not taken into account on component tolerance. TI recommends X5R/X7R capacitors.

11.2 Layout Example

Figure 67. LP8860-Q1 Layout

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

PowerPAD™ Thermally Enhanced Package Application Note
Understanding Boost Power Stages in Switch Mode Power Supplies
Power Stage Designer™ Tools

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 22-Aug-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LP8860AQVFPRQ1 ACTIVE HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LP8860AQ1 LP8860BQVFPRQ1 ACTIVE HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LP8860BQ1 LP8860CQVFPRQ1 ACTIVE HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LP8860CQ1 LP8860DQVFPRQ1 ACTIVE HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LP8860DQ1 LP8860HQVFPRQ1 ACTIVE HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LP8860HQ1 LP8860JQVFPRQ1 ACTIVE HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LP8860JQ1 LP8860LQVFPRQ1 ACTIVE HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LP8860LQ1 LP8860NQVFPRQ1 PREVIEW HLQFP VFP 32 1000 TBD Call TI Call TI -40 to 125 LP8860RQVFPRQ1 PREVIEW HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LP8860RQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 22-Aug-2017 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8860AQVFPRQ1 HLQFP VFP 32 1000 367.0 367.0 38.0 LP8860BQVFPRQ1 HLQFP VFP 32 1000 367.0 367.0 38.0 LP8860CQVFPRQ1 HLQFP VFP 32 1000 367.0 367.0 38.0 LP8860DQVFPRQ1 HLQFP VFP 32 1000 367.0 367.0 38.0 LP8860HQVFPRQ1 HLQFP VFP 32 1000 367.0 367.0 38.0 LP8860JQVFPRQ1 HLQFP VFP 32 1000 367.0 367.0 38.0 LP8860LQVFPRQ1 HLQFP VFP 32 1000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 Pack Materials-Page 2

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Product Information

LP8860NQVFPRQ1 specifications and overview.

Summary

Low-EMI Automotive LED Driver With Four 150-mA Channels

Description

Low-EMI Automotive LED Driver With Four 150-mA Channels

Source title LP8860NQVFPRQ1 Datasheet(PDF) - Texas Instruments

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