Power Management

LP87332DRHDT

Texas Instruments

Dual High-Current Buck Converter and Dual Linear Regulator

Manufacturer: Texas Instruments

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Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 3 100 D001 Vin=3.7V, Vout=1.0V Vin=3.7V, Vout=1.8V Vin=3.7V, Vout=2.5V SW_B0VIN_B0 VIN_B1 VANA VIN FB_B0 VOUT_B0 LOAD SDA SCL nINT CLKIN (GPO2) GNDs EN GPO SW_B1 FB_B1 VOUT_B1 LOAD PGOOD VOUT_LDO1 VOUT_LDO0 VIN_LDO0 VIN_LDO1 VOUT_LDO0 VOUT_LDO1 Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP87332D SNVSAU6 – NOVEMBER 2017 LP87332DDualHigh-CurrentBuckConverterandDualLinearRegulator

1 Features

1• Device Operating Temperature Range: –40°C to +125°C Ambient Temperature

Input Voltage: 2.8 V to 5.5 V
Two High-Efficiency Step-Down DC-DC Converters: – Output Voltage: 0.7 V to 3.36 V – Maximum Output Current 3 A – Programmable Output-Voltage Slew Rate From 0.5 mV/µs to 10 mV/µs – 2-MHz Switching Frequency – Spread-Spectrum Mode and Phase Interleaving for EMI Reduction
Two Linear Regulators: – Input Voltage: 2.5 V to 5.5 V – Output Voltage: 0.8 V to 3.3 V – Maximum Output Current 300 mA
Configurable General-Purpose Output Signals (GPO, GPO2)
Interrupt Function With Programmable Masking
Programmable Power-Good Signal (PGOOD)
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage Lockout (UVLO)
28-pin, 5-mm × 5-mm VQFN Package with Wettable Flanks Simplified Schematic

2 Applications

3 Description

The LP87332D is designed to meet the power management requirements of the latest processors and platforms in industrial applications. The device contains two step-down DC-DC converters and two linear regulators and general-purpose digital-output signals. The device is controlled by an I2C-compatible serial interface and by an enable signal. The automatic PWM/PFM (AUTO mode) operation gives high efficiency over a wide output-current range. The LP87332D supports remote voltage sensing to compensate IR drop between the regulator output and the point-of-load (POL) thus improving the accuracy of the output voltage. In addition the switching clock can be forced to PWM mode and also synchronized to an external clock to minimize the disturbances. The LP87332D device supports load-current measurement without the addition of external current- sense resistors. The LP87332D device also supports programmable start-up and shutdown delays and sequences including GPO signals synchronized to the enable signal. A second GPO signal is available with pin multiplexing of CLKIN pin, if external clock is not needed. During start-up and voltage change, the device controls the output slew rate to minimize output voltage overshoot and the in-rush current. Device Information PART NUMBER PACKAGE BODY SIZE (NOM) LP87332D VQFN (28) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DC-DC Efficiency vs Output Current

11.2 Receiving Notification of Documentation Updates 67

12 Mechanical, Packaging, and Orderable

4 Revision History

November 2017 * Initial release

VIN_LDO1 nINT CLKIN VIN_B1 VIN_B1 SW_B1 SW_B1 PGND_B1 PGND_B1 SCL SDA SGND PGND_B0 PGND_B0 VOUT_LDO1 EN VANA AGND FB_B1 FB_B0 VOUT_LDO0 SW_B0 SW_B0 VIN_B0 VIN_B0 GPO PGOOD VIN_LDO0 THERMAL PAD LP87332D www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin

5 Pin Configuration and Functions

28-Pin VQFN With Thermal Pad Top View Pin Functions PIN TYPE(1) DESCRIPTION NUMBER NAME 1 VOUT_LDO0 P/O LDO0 output. If LDO0 is not used, leave the pin floating.

2 FB_B0 A Output voltage feedback (positive) for Buck 0

3 FB_B1 A Output voltage feedback (positive) for Buck 1

4 AGND G Ground

5 VANA P/I Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx. 6 EN D/I Programmable enable signal for regulators and GPOs. If the pin is not used, leave the pin floating. 7 VOUT_LDO1 P/O LDO1 output. If LDO1 is not used, leave the pin floating. 8 VIN_LDO1 P/I Power input for LDO1. If LDO1 is not used, connect the pin to VANA. 9 nINT D/O Open-drain interrupt output. Active LOW. If the pin is not used, connect the pin to ground. 10 CLKIN D/I/O External clock input. Alternative function is general-purpose digital output (GPO2). If the pin is not used, leave the pin floating. 11, 12 VIN_B1 P/I Input for Buck 1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed. 13, 14 SW_B1 P/O Buck 1 switch node. If the Buck 1 is not used, leave the pin floating. 15, 16 PGND_B1 P/G Power ground for Buck 1 17 SCL D/I Serial interface clock input for I2C access. Connect a pullup resistor. If the I2C interface is not used, connect the pin to Ground. 18 SDA D/I/O Serial interface data input and output for I2C access. Connect a pullup resistor. If the I2C interface is not used, connect the pin to Ground.

19 SGND G Ground

20, 21 PGND_B0 P/G Power ground for Buck 0

SNVSAU6 – NOVEMBER 2017 www.ti.com Product Folder Links: LP87332D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NUMBER NAME 22, 23 SW_B0 P/O Buck 0 switch node. If the Buck 0 is not used, leave the pin floating. 24, 25 VIN_B0 P/I Input for Buck 0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed. 26 GPO D/O General-purpose digital output. If the pin is not used, leave the pin floating. 27 PGOOD D/O Power-good indication signal. If the pin is not used, leave the pin floating. 28 VIN_LDO0 P/I Power input for LDO0. If LDO0 is not used, connect the pin to VANA. Thermal Pad — — Connect to PCB ground plane using multiple vias for good thermal performance.

www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT VIN_Bx, VANA Voltage on power connections (must use the same input supply) –0.3 6 V VIN_LDOx Voltage on power connections –0.3 6 V SW_Bx Voltage on buck switch nodes –0.3 (VIN_Bx + 0.3 V) with 6-V maximum V FB_Bx Voltage on buck voltage sense nodes –0.3 (VANA + 0.3 V) with 6-V maximum V VOUT_LDOx Voltage on LDO output -0.3 (VIN_LDOx + 0.3 V) with 6-V maximum V SDA, SCL, nINT, EN Voltage on logic pins (input or output pins) –0.3 6 V PGOOD, GPO, CLKIN (GPO2) Voltage on logic pins (input or output pins) –0.3 (VANA + 0.3 V) with 6-V maximum V TJ-MAX Junction temperature −40 150 °CTstg Storage temperature –65 150 Maximum lead temperature (soldering, 10 seconds) 260

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM) ±2000 V Charged-device model (CDM) All pins ±500 Corner pins (1, 7, 8, 14, 15, 21, 22, 28) ±750

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT INPUT VOLTAGE VIN_Bx, VANA Voltage on power connections (must use the same input supply) 2.8 5.5 V VIN_LDOx Voltage on LDO inputs 2.5 5.5 V EN, nINT Voltage on logic pins (input or output pins) 0 5.5 V CLKIN Voltage on logic pins (input pin) 0 VANA with 5.5-V maximum V PGOOD, GPO, GPO2 Voltage on logic pins (output pins) 0 VANA V SCL, SDA Voltage on I2C interface, Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes 0 1.95 V Voltage on I2C interface, Standard (100 kHz), Fast (400 kHz), and Fast+ (1 MHz) Modes 0 VANA with 3.6-V maximum V TEMPERATURE TJ Junction temperature −40 140 °C TA Ambient temperature −40 125 °C

SNVSAU6 – NOVEMBER 2017 www.ti.com Product Folder Links: LP87332D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

6.4 Thermal Information

THERMAL METRIC(1) LP87332D UNITRHD (VQFN)

28 PINS

RθJA Junction-to-ambient thermal resistance 36.7 °C/W RθJCtop Junction-to-case (top) thermal resistance 26.6 °C/W RθJB Junction-to-board thermal resistance 8.9 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 8.8 °C/W RθJCbot Junction-to-case (bottom) thermal resistance 2.2 °C/W (1) All voltage values are with respect to network ground. (2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm. (3) The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V, unless otherwise noted.(1)(2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL COMPONENTS CIN_BUCK Input filtering capacitance for buck regulators Effective capacitance, connected from VIN_Bx to PGND_Bx 1.9 10 µF COUT_BUCK Output filtering capacitance for buck regulators Effective capacitance 10 22 500 µF CPOL_BUCK Point-of-load (POL) capacitance for buck regulators Optional POL capacitance 22 µF COUT- TOTAL_BUCK Buck output capacitance, total (local and POL) Total output capacitance 500 µF CIN_LDO Input filtering capacitance for LDO regulators Effective capacitance, connected from VIN_LDOx to AGND. CIN_LDO must be at least two times larger than COUT_LDO 0.6 2.2 µF COUT_LDO Output filtering capacitance for LDO regulators Effective capacitance 0.4 1 2.7 µF ESRC Input and output capacitor ESR [1-10] MHz 2 10 mΩ L Inductor Inductance of the inductor 0.47 µH –30% 30% DCRL Inductor DCR 25 mΩ BUCK REGULATORS V(VIN_Bx), V(VANA) Input voltage range VIN_Bx and VANA pins must be connected to the same supply line 2.8 3.7 5.5 V VOUT_Bx Output voltage Programmable voltage range 0.7 1 3.36 V Step size, 0.7 V ≤ VOUT < 0.73 V 10 mVStep size, 0.73 V ≤ VOUT < 1.4 V 5 Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20 IOUT_Bx Output current Output current 3(3) A

www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V, unless otherwise noted.(1)(2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. (5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and the inductor current level. Input and Output voltage difference Minimum voltage between V(VIN_Bx) and VOUT to fulfill the electrical characteristics 0.8 V VOUT_Bx_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature Force PWM mode, VOUT < 1 V –20 20 mV Force PWM mode, VOUT ≥ 1 V –2% 2% PFM mode, VOUT < 1 V, the average output voltage level is increased by max. 20 mV –20mV 40mV mV PFM mode, VOUT ≥ 1 V, the average output voltage level is increased by max. 20 mV –2% 2% + 20 mV Ripple voltage PWM mode, L = 0.47 µH 10 mVp-p PFM mode, L = 0.47 µH 25 DCLNR DC line regulation IOUT = 1 A ±0.05 %/V DCLDR DC load regulation in PWM mode VOUT_Bx = 1 V, IOUT from 0 to IOUT(max) 0.3% TLDSR Transient load step response IOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM mode ±55 mV TLNSR Transient line response V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±10 mV ILIM FWD Forward current limit for both bucks (peak for every switching cycle) Programmable range 1.5 4 A Step size 0.5 Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A –5% 7.5% 20% Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A –20% 7.5% 20% ILIM NEG Negative current limit 1.6 2.0 3.0 A RDS(ON) HS FET On-resistance, high-side FET Each phase, between VIN_Bx and SW_Bx pins (I = 1 A) 50 110 mΩ RDS(ON) LS FET On-resistance, low-side FET Each phase, between SW_Bx and PGND_Bx pins (I = 1 A) 45 90 mΩ ƒSW Switching frequency PWM mode 1.8 2 2.2 MHz Start-up time (soft start) From ENx to VOUT_Bx = 0.35 V (slew-rate control begins) 120 µs Output voltage slew- rate(4) SLEW_RATEx[2:0] = 010, COUT-TOTAL_BUCK < 80 µF –15% 15% mV/µs SLEW_RATEx[2:0] = 011, COUT-TOTAL_BUCK < 130 µF 7.5 SLEW_RATEx[2:0] = 100, COUT-TOTAL_BUCK < 250 µF 3.8 SLEW_RATEx[2:0] = 101, COUT-TOTAL_BUCK < 500 µF 1.9 SLEW_RATEx[2:0] = 110, COUT-TOTAL_BUCK < 500 µF 0.94 SLEW_RATEx[2:0] = 111, COUT-TOTAL_BUCK < 500 µF 0.47 IPFM-PWM PFM-to-PWM - current threshold(5) 550 mA IPWM-PFM PWM-to-PFM - current threshold(5) 290 mA RDIS_Bx Output pulldown resistance Regulator disabled 150 250 350 Ω

SNVSAU6 – NOVEMBER 2017 www.ti.com Product Folder Links: LP87332D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V, unless otherwise noted.(1)(2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage monitoring for PGOOD pin and for power-good Interrupt V(VIN_Bx) and V(VANA) fixed 3.7 V Overvoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC) 39 50 64 mV Undervoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC) –53 –40 –29 Deglitch time during operation and after voltage change 4 15 µs Gating time for PGOOD signal after regulator enable or voltage change PGOOD_MODE = 0 800 µs LDO REGULATORS VIN_LDOx Input voltage range for LDO power inputs VIN_LDOx can be higher or lower than V(VANA) 2.5 3.7 5.5 V VOUT_LDOx Output voltage Programmable voltage range 0.8 3.3 V Step size 0.1 IOUT_LDOx Output current 300 mA Dropout voltage V(VIN_LDOx) – V(VOUT_LDOx), IOUT = IOUT(max), Programmed output voltage is higher than V(VIN_LDOx) 200 mV VOUT_LDO_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process, temperature VOUT < 1 V –20 20 mV VOUT ≥ 1 V –2% 2% DCLNR DC line regulation IOUT = 1 mA 0.1 %/V DCLDR DC load regulation IOUT = 1 mA to IOUT(max) 0.8% TLDSR Transient load step response IOUT = 1 mA to 300 mA, TR = TF = 1 µs –50/+40 mV TLNSR Transient line response V(VIN_LDOx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±7 mV PSRR Power supply ripple rejection ƒ = 10 kHz, IOUT = IOUT(max) 53 dB Noise 10 Hz < F < 100 kHz, IOUT = IOUT(max) 82 µVrms ISHORT(LDOx) LDO current limit VOUT = 0 V 400 500 600 mA Start-up time From enable to valid output voltage 300 µs Slew rate during start-up 15 mV/µs RDIS_LDOx Output pulldown resistance Regulator disabled 150 250 350 Ω Output voltage monitoring for PGOOD pin and for power-good interrupt Overvoltage monitoring, voltage rising (compared to DC output voltage level, VOUT_LDO_DC) 106% 108% 110% Overvoltage monitoring, hysteresis 3% 3.5% 4% Undervoltage monitoring, voltage falling (compared to DC output voltage level, VOUT_LDO_DC) 90% 92% 94% Undervoltage monitoring, hysteresis 3% 3.5% 4% Deglitch time during operation and after voltage change 4 15 µs

www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V, unless otherwise noted.(1)(2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz. Gating time for PGOOD signal after regulator enable or voltage change PGOOD_MODE = 0 800 µs EXTERNAL CLOCK AND PLL fEXT_CLK External input clock(6) Nominal frequency 1 24 MHz Nominal frequency step size 1 Required accuracy from nominal frequency –30% 10% External clock detection Delay for missing clock detection 1.8 µs Delay and debounce for clock detection 20 Clock change delay (internal to external) Delay from valid clock detection to use of external clock 600 µs PLL output clock jitter Cycle to cycle 300 ps, p-p PROTECTION FUNCTIONS Thermal warning Temperature rising, TDIE_WARN_LEVEL = 0 115 125 135 °CTemperature rising, TDIE_WARN_LEVEL = 1 127 137 147 Hysteresis 20 Thermal shutdown Temperature rising 140 150 160 Hysteresis 20 VANAOVP VANA overvoltage Voltage rising 5.6 5.8 6.1 V Voltage falling 5.45 5.73 5.96 Hysteresis 40 mV VANAUVLO VANA undervoltage lockout Voltage rising 2.51 2.63 2.75 V Voltage falling 2.5 2.6 2.7 Buck short-circuit detection Threshold 280 360 440 mV LDO short-circuit detection Threshold 190 300 450 mV LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS Current measurement range Maximum code 10.22 A Resolution LSB 20 mA Measurement accuracy IOUT > 1 A <10% Measurement time PFM mode (automatically changing to PWM mode for the measurement) 45 µs PWM mode 4 CURRENT CONSUMPTION Standby current consumption, regulators disabled 9 µA Active current consumption, one buck regulator enabled in auto mode, internal RC oscillator, PGOOD monitoring enabled IOUT_Bx = 0 mA, not switching 58 µA

0.4 VVANA V

external pullup resistor, configured to open-drain VVANA V RPU External pullup resistor, configured to open-drain 10 kΩ ALL DIGITAL INPUTS ILEAK Input current All logic inputs over pin voltage range −1 1 µA

6.6 I2C Serial Bus Timing Parameters

These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V. See (1) and Figure 1. MIN MAX UNIT fSCL Serial clock frequency Standard mode 100 kHz Fast mode 400 Fast mode+ 1 MHzHigh-speed mode, Cb = 100 pF 3.4 High-speed mode, Cb = 400 pF 1.7 tLOW SCL low time Standard mode 4.7 µs Fast mode 1.3 Fast mode+ 0.5 High-speed mode, Cb = 100 pF 0.16 High-speed mode, Cb = 400 pF 0.32 tHIGH SCL high time Standard mode 4 µs Fast mode 0.6 Fast mode+ 0.26 High-speed mode, Cb = 100 pF 0.06 High-speed mode, Cb = 400 pF 0.12 tSU;DAT Data setup time Standard mode 250 ns Fast mode 100 Fast mode+ 50 High-speed mode 10 tHD;DAT Data hold time Standard mode 10 3450 ns Fast mode 10 900 Fast mode+ 10 High-speed mode, Cb = 100 pF 10 70 High-speed mode, Cb = 400 pF 10 150 tSU;STA Setup time for a start or a repeated start condition Standard mode 4.7 µs Fast mode 0.6 Fast mode+ 0.26 High-speed mode 0.16 tHD;STA Hold time for a start or a repeated start condition Standard mode 4 µs Fast mode 0.6 Fast mode+ 0.26 High-speed mode 0.16 tBUF Bus free time between a stop and start condition Standard mode 4.7 µsFast mode 1.3 Fast mode + 0.5 tSU;STO Setup time for a stop condition Standard mode 4 µs Fast mode 0.6 Fast mode+ 0.26 High-speed mode 0.16 trDA Rise time of SDA signal Standard mode 1000 ns Fast mode 20 300 Fast mode+ 120 High-speed mode, Cb = 100 pF 10 80 High-speed mode, Cb = 400 pF 20 160

These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V. See (1) and Figure 1. Figure 1. I2C Timing

6.7 Typical Characteristics

(TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF, CPOL_BUCK = 22 µF, and COUT_LDO = 1 µF. Figure 2. Standby Current Consumption vs Input Voltage Figure 3. Active State Current Consumption vs Input Figure 4. Active State Current Consumption vs Input Figure 5. Active State Current Consumption vs Input

7 Detailed Description

7.1 Overview

applications. Table 1 lists the output characteristics of the regulators. Table 1. Supply Specification frequency of the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.

Soft-start
Input voltage protection: – Undervoltage lockout – Overvoltage protection
Output voltage monitoring and protection: – Overvoltage monitoring – Undervoltage monitoring – Overload protection
Thermal warning
Thermal shutdown The LP87332D has one dedicated general purpose digital output (GPO) signal. CLKIN pin can be programmed as a second GPO signal (GPO2) if external clock is not needed. The output type (open-drain or push-pull) is programmable for the GPOs.

Disable, Delay Control Slew-Rate Control Interrupts nINT SDA SCL EN VANA OTP EPROM Thermal Monitor Oscillator Buck0 ILIM Det Pwrgood Det Overload and SC Det Buck1 LDO0 LDO1 ILIM Det Pwrgood Det Overload and SC Det ILIM Det Pwrgood Det Overload and SC Det ILIM Det Pwrgood Det Overload and SC Det Ref & Bias Iload ADC Iload ADC CLKIN (GPO2) PGOOD GPO Copyright © 2016, Texas Instruments Incorporated LP87332D www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 DC-DC Converters

7.3.1.1 Overview

The LP87332D includes two step-down DC-DC converter cores. The cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to optimize the regulator operation for each application. The LP87332D has the following features:

DVS support with programmable slew rate
Automatic mode control based on the loading (PFM or PWM mode)
Forced PWM mode option
Optional external clock input to minimize crosstalk
Optional spread-spectrum technique to reduce EMI
Phase control for optimized EMI
Synchronous rectification
Current mode loop with PI compensator
Soft start
Power Good flag with maskable interrupt
Power Good signal (PGOOD) with selectable sources

Average output current sensing (for PFM entry and load current measurement) The following parameters can be programmed via registers, the default values are set by OTP bits:
Output voltage
Forced PWM operation
Switch current limit
Output voltage slew rate
Enable and disable delays There are two modes of operation for the buck converter, depending on the output current required: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load current levels. A block diagram of a single core is shown in Figure 6.

Figure 6. Detailed Block Diagram Showing One Core

7.3.1.2 Transition Between PWM and PFM Modes

achieved over a wide output-load current range.

7.3.1.3 Buck Converter Load Current Measurement

measurement sequence is 50 µs long, maximum. mA, and maximum code value of the measurement corresponds to 10.22 A.

7.3.1.4 Spread-Spectrum Mode

register, and it affects both buck cores. spectrum architecture of the LP87332D spreads that energy over a large bandwidth. Figure 7. Spread-Spectrum Modulation

7.3.2 Sync Clock Functionality

limits (–30%/+10%) of the selected frequency for valid clock detection. and Buck regulator enable (standby-to-active transition) when EN_PLL is 1.

Figure 8. Clock and PLL Module Table 2. PLL Operation

7.3.3 Low-Dropout Linear Regulators (LDOs)

V(VANA) to minimize the power dissipation.

7.3.4 Power-Up

VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO). This initiates power-on-reset (POR), OTP reading, and enables the system I/O interface. The I2C host should allow at least 1.2 ms before writing or reading data to the LP87332D.
Device enters standby mode.
The host can change the default register setting by I2C if needed.
The regulators can be enabled/disabled and the GPO signals can be controlled by EN pin and by I2C interface. Transitions between the operating modes are shown in Modes of Operation.

7.3.5 Regulator Control

7.3.5.1 Enabling and Disabling Regulators

Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 0 in BUCKx_CTRL_1 register)
Using EN control pin (BUCKx_EN bit is 1 AND BUCKx_EN_PIN_CTRL bit is 1)

Using LDOx_EN bit in LDOx_CTRL register (LDOx_EN_PIN_CTRL bit is 0 in LDOx_CTRL register)
Using EN control pin (LDOx_EN bit is 1 AND LDOx_EN_PIN_CTRL bit is 1) If the EN control pin is used for enable and disable then the delay from the control signal rising edge to start-up is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_STARTUP_DELAY[3:0] bits in LDOx_DELAY register and the delay from control signal falling edge to shutdown is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_SHUTDOWN_DELAY[3:0] bits in LDOx_DELAY register. The delays are valid only for EN signal transitions and not for control with I2C writings to BUCKx_EN and LDOx_EN bits. The control of the regulator (with 0-ms delays) is shown in Table 3.

Table 3. Regulator Control

0 Don't Care Don't Care Disabled

Figure 9. Buck Regulator Enable and Disable output voltage, either undervoltage detection or undervoltage and overvoltage detection.

Figure 10. LDO Regulator Enable and Disable

7.3.5.2 Changing Output Voltage

load current, and the BUCKx_FPWM bit in BUCKx_CTRL_1 register. The voltage change and Power-Good interrupts are shown in Figure 11.

Figure 11. Regulator Output Voltage Change

7.3.6 Enable and Disable Sequences

BUCKx_EN = 1 in BUCKx_CTRL_1 register
BUCKx_EN_PIN_CTRL = 1 in BUCKx_CTRL_1 register
BUCKx_VSET[7:0] bits in BUCKx_VOUT register defines the voltage when EN pin is high
The delay from rising edge of EN pin to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and
The delay from falling edge of EN pin to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register.

LDOx_EN = 1 in LDOx_CTRL register
LDOx_EN_PIN_CTRL = 1 in LDOx_CTRL register
LDOx_VSET[4:0] bits in LDOx_VOUT register defines the voltage when EN pin is high
The delay from rising edge of EN pin to the regulator enable is set by LDOx_STARTUP_DELAY[3:0] bits in LDOx_DELAY register and
The delay from falling edge of EN pin to the regulator disable is set by LDOx_SHUTDOWN_DELAY[3:0] bits in LDOx_DELAY register. The GPO (and GPO2) digital output signals can be also controlled as a part of start-up and shutdown sequencing with the following settings:
GPOx_EN = 1 in GPO_CTRL register
GPOx_EN_PIN_CTRL = 1 in GPO_CTRL register
The delay from rising edge of EN pin to the rising edge of GPO/GPO2 signal is set by GPOx_STARTUP_DELAY[3:0] bits in GPOx_DELAY register and
The delay from falling edge of EN pin to the falling edge of GPO/GPO2 signal is set by GPOx_SHUTDOWN_DELAY[3:0] bits in GPOx_DELAY register. An example of the start-up and shutdown sequences for the buck regulators are shown in Figure 12. The start-up and shutdown delays for the Buck0 regulator are 1 ms and 4 ms; for the Buck1 regulator start-up and shutdown delays are 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN signal.

Figure 12. Start-Up and Shutdown Sequencing

7.3.7 Device Reset Scenarios

There are three reset methods implemented on the LP87332D:

Software reset with SW_RESET bit in RESET register
Undervoltage lockout (UVLO) reset from VANA supply An SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event disables all the regulators immediately, drives GPO and GPO2 signals low, resets all the register bits to the default values and OTP bits are loaded (see Figure 18). I2C interface is not reset during software reset. If VANA supply voltage falls below the UVLO threshold level then all the regulators are disabled immediately, GPO and GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA supply voltage transition above UVLO threshold level an internal POR occurs. OTP bits are loaded to the registers and a startup is initiated according to the register settings.

7.3.8 Diagnosis and Protection Features

The LP87332D is capable of providing four levels of protection features:

Information of valid regulator output voltage which sets interrupt or PGOOD signal;
Warnings for diagnosis which sets interrupt;
Protection events which are disabling the regulators; and
Faults which are causing the device to shutdown. The LP87332D sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared. When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded from OTP during reset sequence.

pin polarity, not Power Good and PGOOD_INT interrupt polarity. (2) Interrupt is generated during clock-detector operation and if clock is not available when clock detector is enabled. Table 4. Summary of Interrupt Signals

7.3.8.1 Power-Good Information (PGOOD pin)

Regulator output voltage,
Input supply overvoltage,
Thermal warning and
Thermal shutdown.

SNVSAU6 – NOVEMBER 2017 www.ti.com Product Folder Links: LP87332D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Regulator output voltage monitoring (not current limit monitoring) can be selected for PGOOD indication. This selection is individual for both buck regulators and both LDO regulators and is set by EN_PGOOD_BUCKx bits in PGOOD_CTRL_1 register and EN_PGOOD_LDOx bits in PGOOD_CTRL_1 register. When a regulator is disabled, the monitoring is automatically masked to prevent it forcing PGOOD inactive. A thermal warning can be also selected for PGOOD indication with EN_PGOOD_TWARN bit in PGOOD_CTRL_2 register. The monitoring from all the output rails, thermal warning (TDIE_WARN_STAT), input overvoltage interrupt (OVP_INT), and thermal shutdown interrupt (TDIE_SD_INT) are combined, and PGOOD pin is active only if all the selected sources shows a valid status. The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW_x bits in PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and overvoltage are monitored. The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD bits in the PGOOD_CTRL_1 register. PGOOD is only active or asserted when all enabled power resource output voltages are within specified tolerance for each requested/programmed output voltage. PGOOD is inactive or de-asserted if any enabled power resource output voltages is outside specified tolerance for each requested/programmed output voltage. The device OTP setting selects either gated (that is, unusual) or continuous (that is, invalid) mode of operation.

7.3.8.1.1 PGOOD Pin Gated mode

The gated (or unusual) mode of operation is selected by setting PGOOD_MODE bit to 0 in PGOOD_CTRL_2 register. For the gated mode of operation, PGOOD behaves as follows:

PGOOD is set to active or asserted state upon exiting OTP configuration as an initial default state.
PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status indication.
During normal power-up sequencing and requested voltage changes, PGOOD state is not changed during an 800-µs gated time period. It typically remains active or asserted for normal conditions.
During an abnormal power-up sequencing and requested voltage changes, PGOOD status could change to inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation range.
Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown sequence if the PGOOD signal is wired-OR with signal connected to EN input. This type of circuit configuration provides a smart PORz function for processor that eliminates the need for additional components to generate PORz upon start-up and to monitor voltage levels of key voltage domains. The fault sets corresponding fault bit 1 in PG_FAULT register. The detected fault must be cleared to continue the PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to the OVP_INT and TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the corresponding register bit in PG_FAULT register. The interrupts can be also cleared with VANA UVLO by toggling the input supply. An example of PGOOD pin operation in gated mode is shown in Figure 13.

Figure 13. PGOOD Pin Operation in Gated Mode

7.3.8.1.2 PGOOD Pin Continuous Mode

PGOOD is set to active or asserted state upon exiting OTP configuration.
PGOOD is set to inactive or de-asserted as soon as regulator is enabled.
PGOOD status begins indicating output voltage regulation status immediately and continuously.
During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or de- asserted while output voltages are outside of regulation ranges and active or asserted when inside of regulation ranges. The PG_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit. The PGOOD signal indicates also a thermal shutdown and input overvoltage interrupts, which are cleared by clearing the interrupt bits. When regulator voltage is transitioning from one target voltage to another, the PGOOD signal is set inactive. When the PGOOD signal becomes inactive, the source for the fault can be read from PG_FAULT register. If the invalid output voltage becomes valid again the PGOOD signal becomes active. Thus the PGOOD signal shows all the time if the monitored output voltages are valid. The block diagram for this operation is shown in Figure 14 and an example of operation is shown in Figure 15. The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs are valid but there are PG_FAULT_x bits in PG_FAULT register pending clearance. This type of operation is selected by setting PGFAULT_GATES_PGOOD bit to 1 in PGOOD_CTRL_2 register.

Figure 14. PGOOD Block Diagram (Continuous Mode)

Figure 15. PGOOD Pin Operation in Continuous Mode

7.3.8.2 Warnings for Diagnosis (Interrupt)

7.3.8.2.1 Output Power Limit

current limit is triggered, the regulator continues to regulate to the limit current level (peak current regulation). situation is shown in Figure 16.

Figure 16. Buck Regulator Overload Situation LDOx_ILIM_MASK bit in LDO_MASK register to 1. The LDO overload situation is shown in Figure 17.

Figure 17. LDO Regulator Overload Situation

7.3.8.2.2 Thermal Warning

TDIE_WARN_STAT bit in TOP_STAT register, and the interrupt is cleared by writing 1 to TDIE_WARN_INT bit. The thermal warning interrupt can be masked by setting TDIE_WARN_MASK bit in TOP_MASK_1 register to 1.

7.3.8.3 Protection (Regulator Disable)

active as long as VANA voltage is above approximately a 1.2-V level.

7.3.8.3.1 Short-Circuit and Overload Protection

output voltage is below the threshold level 1 ms after the regulator is enabled. V and 0.3 V and remains below the threshold level for 1 ms the regulator is disabled.

SNVSAU6 – NOVEMBER 2017 www.ti.com Product Folder Links: LP87332D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated In buck regulator short-circuit and overload situations the BUCKx_SC_INT bit in INT_BUCK register and the INT_BUCKx bit in INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to 0, and the nINT signal is pulled low. In LDO regulator short-circuit and overload situations the LDOx_SC_INT bit in INT_LDO register and the INT_LDOx bit in INT_TOP_1 register are set to 1, the LDOx_STAT bit in LDO_STAT register is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT or to the LDOx_SC_INT bit. Upon clearing the interrupt the regulator makes a new start-up attempt if the regulator is in an enabled state.

7.3.8.3.2 Overvoltage Protection

The LP87332D device monitors the input voltage from the VANA pin in standby and active operation modes. If the input voltage rises above VANAOVP voltage level, all the regulators are disabled immediately (without switching ramp, no shutdown delays), pulldown resistors discharge the output voltages if they are enabled (BUCKx_RDIS_EN = 1 in BUCKx_CTRL_1 register and LDOx_RDIS_EN = 1 in LDOx_CTRL register), GPOs are set to logic low level, nINT signal is pulled low, OVP_INT bit in INT_TOP_1 register is set to 1, and BUCKx_STAT bit in BUCK_STAT register and LDOx_STAT bit in LDO_STAT register are set to 0. The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above overvoltage detection level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit in TOP_STAT register. Regulators cannot be enabled as long as the input voltage is above overvoltage detection level or the overvoltage interrupt is pending.

7.3.8.3.3 Thermal Shutdown

The LP87332D has an overtemperature protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are disabled immediately (without switching ramp, no shutdown delays), the TDIE_SD_INT bit in INT_TOP_1 register is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT is cleared by writing 1 to the TDIE_SD_INT bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit in TOP_STAT register. Regulators cannot be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown interrupt is pending.

7.3.8.4 Fault (Power Down)

7.3.8.4.1 Undervoltage Lockout

When the input voltage falls below VANAUVLO at the VANA pin, the buck and LDO regulators are disabled immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the pulldown resistor, and the LP87332D device enters SHUTDOWN. When V(VANA) voltage is above VANAUVLO threshold level, the device powers up to STANDBY state. If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register) the RESET_REG_INT interrupt bit in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the RESET_REG_INT interrupt bit after detecting an nINT low signal, it knows that the input supply voltage has been below VANAUVLO level (or the host has requested reset with SW_RESET bit in RESET register), and the registers are reset to default values.

7.3.9 Operation of the GPO Signals

The LP87332D device supports up to 2 general purpose output signals, GPO and GPO2. The GPO2 signal is multiplexed with CLKIN signal. The selection between CLKIN and GPO2 pin function is set with CLKIN_PIN_SEL bit in CONFIG register. The GPO pins are configured with the following bits:

GPOx_OD bit in GPO_CTRL register defines the type of the output, either push-pull with V(VANA) level or open drain The logic level of the GPOx pin is set by EN_GPOx bit in GPO_CTRL register. The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence with EN pin is selected by GPOx_EN_PIN_CTRL bit in GPO_CTRL register. For start-up and shutdown sequence control see Enable and Disable Sequences.

(1) No glitch filtering, only synchronization.

7.3.10 Digital Signal Filtering

The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter. This results as an accuracy of one clock period for the debounce window. Table 5. Digital Signal Filtering

7.4 Device Functional Modes

7.4.1 Modes of Operation

circuitry of the LP87332D device are turned off. reference and bias circuitry of the LP87332D are enabled. The OTP bits are loaded to registers. registers can be read or written by the host processor via the system serial interface. The operating modes and transitions between the modes are shown in Figure 18. Figure 18. Device Operation Modes

7.5 Programming

7.5.1 I2C-Compatible Interface

kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).

7.5.1.1 Data Validity

state of the data line can only be changed when clock signal is LOW. Figure 19. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

always generates the START and STOP conditions. Figure 20. Start and Stop Sequences SDA and SCL signal timing for the I2C-compatible bus. See the Figure 1 for timing values.

Figure 21. I2C-Compatible Timing

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. acknowledge after each byte has been received. but the SDA line is not pulled down. master is disabled at that time. data to write to the selected register. Figure 22. Write Cycle (w = write; SDA = 0). Example Device Address = 0x60

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. Figure 23. Read Cycle (r = read; SDA = 1). Example Device Address = 0x60

7.5.1.4 I2C-Compatible Chip Address

The device address for the LP87332D is 0x60. After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W). selects the register address to which the data is written. The third byte contains the data for the selected register. Here in an example with device address of 1100000Bin = 60Hex. Figure 24. Device Address Example

7.5.1.5 Auto-Increment Feature

Table 6. Auto-Increment Example

7.6 Register Maps

7.6.1 Register Descriptions

The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state. Table 7. Summary of LP87332D Control Registers

Table 7. Summary of LP87332D Control Registers (continued)

7.6.1.1 DEV_REV

Address: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 DEVICE_ID[1:0] Reserved Bits Field Type Default Description 7:6 DEVICE_ID[1:0] R 0x2* Device specific ID code. 5:0 Reserved R 00 0010

7.6.1.2 OTP_REV

Address: 0x01 D7 D6 D5 D4 D3 D2 D1 D0 OTP_ID[7:0] Bits Field Type Default Description 7:0 OTP_ID[7:0] R 0x2D* Identification Code of the OTP EPROM Version.

7.6.1.3 BUCK0_CTRL_1

Address: 0x02 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK0_FPWM BUCK0_RDIS_ EN BUCK0_EN_PI N_CTRL BUCK0_EN Bits Field Type Default Description 7:4 Reserved R/W 0000

3 BUCK0_FPWM R/W 0 * Buck0 mode selection:

0 - Automatic transitions between PFM and PWM modes (AUTO mode) 1 - Forced to PWM operation.

2 BUCK0_RDIS_EN R/W 1 Enable output discharge resistor (RDIS_Bx) when Buck0 is disabled:

0 - Discharge resistor disabled 1 - Discharge resistor enabled.

1 BUCK0_EN_PIN

_CTRL R/W 1 * Enable control for Buck0: 0 - only BUCK0_EN bit controls Buck0 1 - BUCK0_EN bit AND EN pin control Buck0.

0 BUCK0_EN R/W 1 * Enable Buck0 regulator:

0 - Buck0 regulator is disabled 1 - Buck0 regulator is enabled.

7.6.1.4 BUCK0_CTRL_2

Address: 0x03 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK0_ILIM[2:0] BUCK0_SLEW_RATE[2:0]

www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Bits Field Type Default Description 7:6 Reserved R/W 00 5:3 BUCK0_ILIM[2:0] R/W 0x5* Sets the switch current limit of Buck0. Can be programmed at any time during operation: 0x0 - 1.5 A 0x1 - 2.0 A 0x2 - 2.5 A 0x3 - 3.0 A 0x4 - 3.5 A 0x5 - 4.0 A 0x6 - Reserved 0x7 - Reserved 2:0 BUCK0_SLEW_RA TE[2:0] R/W 0x2* Sets the output voltage slew rate for Buck0 regulator (rising and falling edges): 0x0 - Reserved 0x1 - Reserved 0x2 - 10 mV/µs 0x3 - 7.5 mV/µs 0x4 - 3.8 mV/µs 0x5 - 1.9 mV/µs 0x6 - 0.94 mV/µs 0x7 - 0.47 mV/µs

7.6.1.5 BUCK1_CTRL_1

Address: 0x04 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK1_FPWM BUCK1_RDIS_ EN BUCK1_EN_PI N_CTRL BUCK1_EN Bits Field Type Default Description 7:4 Reserved R/W 0000

3 BUCK1_FPWM R/W 0 * Buck1 mode selection:

0 - Automatic transitions between PFM and PWM modes (AUTO mode) 1 - Forced to PWM operation.

2 BUCK1_RDIS_EN R/W 1 Enable output discharge resistor (RDIS_Bx) when Buck1 is disabled:

0 - Discharge resistor disabled 1 - Discharge resistor enabled.

1 BUCK1_EN_PIN

_CTRL R/W 1 * Enable control for Buck1: 0 - only BUCK1_EN bit controls Buck1 1 - BUCK1_EN bit AND EN pin control Buck1.

0 BUCK1_EN R/W 1 * Enable Buck1 regulator:

0 - Buck1 regulator is disabled 1 - Buck1 regulator is enabled.

7.6.1.6 BUCK1_CTRL_2

Address: 0x05 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK1_ILIM[2:0] BUCK1_SLEW_RATE[2:0]

SNVSAU6 – NOVEMBER 2017 www.ti.com Product Folder Links: LP87332D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Bits Field Type Default Description 7:6 Reserved R/W 00 5:3 BUCK1_ILIM[2:0] R/W 0x5* Sets the switch current limit of Buck1. Can be programmed at any time during operation: 0x0 - 1.5 A 0x1 - 2.0 A 0x2 - 2.5 A 0x3 - 3.0 A 0x4 - 3.5 A 0x5 - 4.0 A 0x6 - Reserved 0x7 - Reserved 2:0 BUCK1_SLEW_RA TE[2:0] R/W 0x2* Sets the output voltage slew rate for Buck1 regulator (rising and falling edges): 0x0 - Reserved 0x1 - Reserved 0x2 - 10 mV/µs 0x3 - 7.5 mV/µs 0x4 - 3.8 mV/µs 0x5 - 1.9 mV/µs 0x6 - 0.94 mV/µs 0x7 - 0.47 mV/µs

7.6.1.7 BUCK0_VOUT

Address: 0x06 D7 D6 D5 D4 D3 D2 D1 D0 BUCK0_VSET[7:0] Bits Field Type Default Description 7:0 BUCK0_VSET[7:0] R/W 0x6B* Sets the output voltage of Buck0 regulator Reserved, DO NOT USE 0x00 ... 0x13 0.7 V - 0.73 V, 10 mV steps 0x14 - 0.7V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V

7.6.1.8 BUCK1_VOUT

Address: 0x07 D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_VSET[7:0]

www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Bits Field Type Default Description 7:0 BUCK1_VSET[7:0] R/W 0x59* Sets the output voltage of Buck0 regulator Reserved, DO NOT USE 0x00 ... 0x13 0.7 V - 0.73 V, 10 mV steps 0x14 - 0.7V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V

7.6.1.9 LDO0_CTRL

Address: 0x08 D7 D6 D5 D4 D3 D2 D1 D0 Reserved LDO0_RDIS_E N LDO0_EN_PIN _CTRL LDO0_EN Bits Field Type Default Description 7:3 Reserved R/W 0 0000

2 LDO0_RDIS_EN R/W 1 Enable output discharge resistor (RDIS_LDOx) when LDO0 is disabled:

0 - Discharge resistor disabled 1 - Discharge resistor enabled.

1 LDO0_EN_PIN

_CTRL R/W 1 * Enable control for LDO0: 0 - only LDO0_EN bit controls LDO0 1 - LDO0_EN bit AND EN pin control LDO0.

0 LDO0_EN R/W 1 * Enable LDO0 regulator:

0 - LDO0 regulator is disabled 1 - LDO0 regulator is enabled.

7.6.1.10 LDO1_CTRL

Address: 0x09 D7 D6 D5 D4 D3 D2 D1 D0 Reserved LDO1_RDIS_E N LDO1_EN_PIN _CTRL LDO1_EN Bits Field Type Default Description 7:3 Reserved R/W 0 0000

2 LDO1_RDIS_EN R/W 1 Enable output discharge resistor (RDIS_LDOx) when LDO1 is disabled:

0 - Discharge resistor disabled 1 - Discharge resistor enabled.

1 LDO1_EN_PIN

_CTRL R/W 1 * Enable control for LDO1: 0 - only LDO1_EN bit controls LDO1 1 - LDO1_EN bit AND EN pin control LDO1.

0 LDO1_EN R/W 1 * Enable LDO1 regulator:

0 - LDO1 regulator is disabled 1 - LDO1 regulator is enabled.

7.6.1.11 LDO0_VOUT

Address: 0x0A D7 D6 D5 D4 D3 D2 D1 D0 Reserved LDO0_VSET[4:0] Bits Field Type Default Description 7:5 Reserved R/W 000 4:0 LDO0_VSET[4:0] R/W 0x19* Sets the output voltage of LDO0 regulator 0.8 V - 3.3 V, 100 mV steps 0x00 - 0.8V ... 0x19 - 3.3 V Reserved, DO NOT USE 0x1A ... 0x1F

7.6.1.12 LDO1_VOUT

Address: 0x0B D7 D6 D5 D4 D3 D2 D1 D0 Reserved LDO1_VSET[4:0] Bits Field Type Default Description 7:5 Reserved R/W 000 4:0 LDO1_VSET[4:0] R/W 0x19* Sets the output voltage of LDO1 regulator 0.8 V - 3.3 V, 100 mV steps 0x00 - 0.8V ... 0x19 - 3.3 V Reserved, DO NOT USE 0x1A ... 0x1F

7.6.1.13 BUCK0_DELAY

Address: 0x0C D7 D6 D5 D4 D3 D2 D1 D0 BUCK0_SHUTDOWN_DELAY[3:0] BUCK0_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 BUCK0_ SHUTDOWN_ DELAY[3:0] R/W 0x2* Shutdown delay of Buck0 from falling edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) 3:0 BUCK0_ STARTUP_ DELAY[3:0] R/W 0x3* Startup delay of Buck0 from rising edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.14 BUCK1_DELAY

Address: 0x0D D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_SHUTDOWN_DELAY[3:0] BUCK1_STARTUP_DELAY[3:0]

www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Bits Field Type Default Description 7:4 BUCK1_ SHUTDOWN_ DELAY[3:0] R/W 0x2* Shutdown delay of Buck1 from falling edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) 3:0 BUCK1_ STARTUP_ DELAY[3:0] R/W 0x4* Startup delay of Buck1 from rising edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.15 LDO0_DELAY

Address: 0x0E D7 D6 D5 D4 D3 D2 D1 D0 LDO0_SHUTDOWN_DELAY[3:0] LDO0_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 LDO0_ SHUTDOWN_ DELAY[3:0] R/W 0x0* Shutdown delay of LDO0 from falling edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) 3:0 LDO0_ STARTUP_ DELAY[3:0] R/W 0x7* Startup delay of LDO0 from rising edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.16 LDO1_DELAY

Address: 0x0F D7 D6 D5 D4 D3 D2 D1 D0 LDO1_SHUTDOWN_DELAY[3:0] LDO1_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 LDO1_ SHUTDOWN_ DELAY[3:0] R/W 0x2* Shutdown delay of LDO1 from falling edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) 3:0 LDO1_ STARTUP_ DELAY[3:0] R/W 0x5* Startup delay of LDO1 from rising edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.17 GPO_DELAY

Address: 0x10 D7 D6 D5 D4 D3 D2 D1 D0 GPO_SHUTDOWN_DELAY[3:0] GPO_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 GPO_ SHUTDOWN_ DELAY[3:0] R/W 0x0* Delay for GPO falling edge from falling edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

SNVSAU6 – NOVEMBER 2017 www.ti.com Product Folder Links: LP87332D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Bits Field Type Default Description 3:0 GPO_ STARTUP_ DELAY[3:0] R/W 0x7* Delay for GPO rising edge from rising edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.18 GPO2_DELAY

Address: 0x11 D7 D6 D5 D4 D3 D2 D1 D0 GPO2_SHUTDOWN_DELAY[3:0] GPO2_STARTUP_DELAY[3:0] Bits Field Type Default Description 7:4 GPO2_ SHUTDOWN_ DELAY[3:0] R/W 0x0* Delay for GPO2 falling edge from falling edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register) 3:0 GPO2_ STARTUP_ DELAY[3:0] R/W 0xA* Delay for GPO2 rising edge from rising edge of EN signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register) ... 0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.19 GPO_CTRL

Address: 0x12 D7 D6 D5 D4 D3 D2 D1 D0 Reserved GPO2_OD GPO2_EN_PIN _CTRL GPO2_EN Reserved GPO_OD GPO_EN_PIN_ CTRL GPO_EN Bits Field Type Default Description

7 Reserved R 0

6 GP02_OD R/W 1 * GPO2 signal type when configured as General Purpose Output (CLKIN pin):

0 - Push-pull output (VANA level) 1 - Open-drain output

5 GPO2_EN_PIN_C

R/W 1 * Control for GPO2: 0 - Only GPO2_EN bit controls GPO2 1 - GPO2_EN bit AND EN pin control GPO2.

4 GPO2_EN R/W 1 * Output level of GPO2 signal (when configured as General Purpose Output):

3 Reserved R 0

2 GPO_OD R/W 1 * GPO signal type:

0 - Push-pull output (VANA level) 1 - Open-drain output

1 GPO_EN_PIN_CT

R/W 1 * Control for GPO: 0 - Only GPO_EN bit controls GPO 1 - GPO_EN bit AND EN pin control GPO.

0 GPO_EN R/W 1 * Output level of GPO signal:

7.6.1.20 CONFIG

Address: 0x13 D7 D6 D5 D4 D3 D2 D1 D0 Reserved STARTUP_DE LAY_SEL SHUTDOWN_ DELAY_SEL CLKIN_PIN_SE L CLKIN_PD EN2_PD TDIE_WARN_ LEVEL EN_SPREAD _SPEC Bits Field Type Default Description

7 Reserved R/W 0

6 STARTUP_DELAY

_SEL R/W 0 * Startup delay range from EN signals. 0 - 0 ms - 7.5 ms with 0.5 ms steps 1 - 0 ms - 15 ms with 1 ms steps

5 SHUTDOWN_DEL

AY_SEL R/W 0 * Shutdown delay range from EN signals. 0 - 0 ms - 7.5 ms with 0.5 ms steps 1 - 0 ms - 15 ms with 1 ms steps

4 CLKIN_PIN_SEL R/W 0 * CLKIN pin function:

3 CLKIN_PD R/W 0 * Selects the pull down resistor on the CLKIN input pin. (valid also when selected as GPO2) 0 - Pull-down resistor is disabled. 1 - Pull-down resistor is enabled. 2 EN_PD R/W 1 * Selects the pull down resistor on the EN input pin. 0 - Pull-down resistor is disabled. 1 - Pull-down resistor is enabled.

1 TDIE_WARN_

R/W 1 * Thermal warning threshold level. 0 - 125°C 1 - 137°C.

0 EN_SPREAD

_SPEC R/W 0 * Enable spread spectrum feature: 0 - Disabled 1 - Enabled

7.6.1.21 PLL_CTRL

Address: 0x14 D7 D6 D5 D4 D3 D2 D1 D0 Reserved EN_PLL Reserved EXT_CLK_FREQ[4:0] Bits Field Type Default Description

6 EN_PLL R/W 0 * Selection of external clock and PLL operation:

0 - Forced to internal RC oscillator. PLL disabled. 1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use when available, interrupt generated if external clock appears or disappears. 5 Reserved R/W 0 This bit must be set to '0'. 4:0 EXT_CLK_FREQ[4 :0] R/W 0x1* Frequency of the external clock (CLKIN): 0x00 - 1 MHz 0x01 - 2 MHz 0x02 - 3 MHz ... 0x16 - 23 MHz 0x17 - 24 MHz 0x18...0x1F - Reserved See electrical specification for input clock frequency tolerance.

7.6.1.22 PGOOD_CTRL_1

Address: 0x15 D7 D6 D5 D4 D3 D2 D1 D0 PGOOD_POL PGOOD_OD PGOOD_ WINDOW_LDO PGOOD_ WINDOW_BUC K EN_PGOOD_L DO1 EN_PGOOD_L DO0 EN_PGOOD_B UCK1 EN_PGOOD_B UCK0 Bits Field Type Default Description 7 PGOOD_POL R/W 0 * PGOOD signal polarity. 0 - PGOOD signal high when monitored outputs are valid 1 - PGOOD signal low when monitored outputs are valid

6 PGOOD_OD R/W 1 * PGOOD signal type:

0 - Push-pull output (VANA level) 1 - Open-drain output

5 PGOOD_

WINDOW_LDO R/W 1 * LDO Output voltage monitoring method for PGOOD signal: 0 - Only undervoltage monitoring 1 - Overvoltage and undervoltage monitoring.

4 PGOOD_

WINDOW_BUCK R/W 1 * Buck Output voltage monitoring method for PGOOD signal: 0 - Only undervoltage monitoring 1 - Overvoltage and undervoltage monitoring.

3 EN_PGOOD_LDO

R/W 0 * PGOOD signal source control from LDO1 0 - LDO1 is not monitored 1 - LDO1 Power-Good threshold voltage monitored

2 EN_PGOOD_LDO

R/W 0 * PGOOD signal source control from LDO0 0 - LDO0 is not monitored 1 - LDO0 Power-Good threshold voltage monitored

1 EN_PGOOD_BUC

R/W 1 * PGOOD signal source control from Buck1 0 - Buck1 is not monitored 1 - Buck1 Power-Good threshold voltage monitored

0 EN_PGOOD_BUC

R/W 1 * PGOOD signal source control from Buck0 0 - Buck0 is not monitored 1 - Buck0 Power-Good threshold voltage monitored

7.6.1.23 PGOOD_CTRL_2

Address: 0x16 D7 D6 D5 D4 D3 D2 D1 D0 Reserved EN_PGOOD_T WARN PG_FAULT_G ATES_PGOOD PGOOD_MOD E Bits Field Type Default Description 7:3 Reserved R/W 0 0000

2 EN_PGOOD_TWA

R/W 1 * Thermal warning control for PGOOD signal: 0 - Thermal warning not monitored 1 - PGOOD inactive if thermal warning flag is active.

1 PG_FAULT_GATE

S_PGOOD R/W 0 * Type of operation for PGOOD signal: 0 - Indicates live status of monitored voltage outputs. 1 - Indicates status of PG_FAULT register, inactive when at least one PG_FAULT_x bit is inactive.

0 PGOOD_MODE R/W 0 * Operating mode for PGOOD signal:

7.6.1.24 PG_FAULT

Address: 0x17 D7 D6 D5 D4 D3 D2 D1 D0 Reserved PG_FAULT_LD PG_FAULT_LD PG_FAULT_BU CK1 PG_FAULT_BU CK0

3 PG_FAULT_LDO1 R/W 0 Source for PGOOD inactive signal:

0 - LDO1 has not set PGOOD signal inactive. 1 - LDO1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit can be cleared by writing '1' to this bit when LDO1 output is valid.

2 PG_FAULT_LDO0 R/W 0 Source for PGOOD inactive signal:

0 - LDO0 has not set PGOOD signal inactive. 1 - LDO0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit can be cleared by writing '1' to this bit when LDO0 output is valid.

1 PG_FAULT_BUCK

R/W 0 Source for PGOOD inactive signal: 0 - Buck1 has not set PGOOD signal inactive. 1 - Buck1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit can be cleared by writing '1' to this bit when Buck1 output is valid.

0 PG_FAULT_BUCK

R/W 0 Source for PGOOD inactive signal: 0 - Buck0 has not set PGOOD signal inactive. 1 - Buck0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit can be cleared by writing '1' to this bit when Buck0 output is valid.

7.6.1.25 RESET

Address: 0x18 D7 D6 D5 D4 D3 D2 D1 D0 Reserved SW_RESET Bits Field Type Default Description 7:1 Reserved R/W 000 0000 0 SW_RESET R/W 0 Software commanded reset. When written to 1, the registers will be reset to default values, OTP memory is read, and the I2C interface is reset. The bit is automatically cleared.

7.6.1.26 INT_TOP_1

Address: 0x19 D7 D6 D5 D4 D3 D2 D1 D0 PGOOD_INT LDO_INT BUCK_INT SYNC_CLK_IN T TDIE_SD_INT TDIE_WARN_I NT OVP_INT I_MEAS_INT Bits Field Type Default Description 7 PGOOD_INT R/W 0 Latched status bit indicating that the PGOOD pin has changed from active to inactive. Write 1 to clear interrupt. 6 LDO_INT R 0 Interrupt indicating that LDO1 and/or LDO0 have a pending interrupt. The reason for the interrupt is indicated in INT_LDO register. This bit is cleared automatically when INT_LDO register is cleared to 0x00. 5 BUCK_INT R 0 Interrupt indicating that Buck1 and/or Buck0 have a pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. 4 SYNC_CLK_INT R/W 0 Latched status bit indicating that the external clock has appeared or disappeared. Write 1 to clear interrupt.

3 TDIE_SD_INT R/W 0 Latched status bit indicating that the die junction temperature has exceeded the

thermal shutdown level. The regulators have been disabled if they were enabled and GPO and GPO2 signals are driven low. The regulators cannot be enabled if this bit is active. The actual status of the thermal shutdown is indicated by TDIE_SD_STAT bit in TOP_STAT register. Write 1 to clear interrupt.

2 TDIE_WARN_INT R/W 0 Latched status bit indicating that the die junction temperature has exceeded the

thermal warning level. The actual status of the thermal warning is indicated by TDIE_WARN_STAT bit in TOP_STAT register. Write 1 to clear interrupt.

1 OVP_INT R/W 0 Latched status bit indicating that the input voltage has exceeded the over-voltage

detection level. The regulators have been disabled if they were enabled and GPO and GPO2 signals are driven low. The actual status of the over-voltage is indicated by OVP_STAT bit in TOP_STAT register. Write 1 to clear interrupt. 0 I_MEAS_INT R/W 0 Latched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers. Write 1 to clear interrupt.

7.6.1.27 INT_TOP_2

Address: 0x1A D7 D6 D5 D4 D3 D2 D1 D0 Reserved RESET_REG_I NT Bits Field Type Default Description 7:1 Reserved R/W 000 0000

0 RESET_REG_INT R/W 0 Latched status bit indicating that either VANA supply voltage has been below

undervoltage threshold level or the host has requested a reset using SW_RESET bit in RESET register. The regulators have been disabled, and registers are reset to default values and the normal startup procedure is done. Write 1 to clear interrupt.

7.6.1.28 INT_BUCK

Address: 0x1B D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK1_PG _INT BUCK1_SC _INT BUCK1_ILIM _INT Reserved BUCK0_PG _INT BUCK0_SC _INT BUCK0_ILIM _INT Bits Field Type Default Description 6 BUCK1_PG_INT R/W 0 Latched status bit indicating that Buck1 Power-Good event has been detected. Write 1 to clear. 5 BUCK1_SC_INT R/W 0 Latched status bit indicating that the Buck1 output voltage has been over 1 ms below short-circuit threshold level. Write 1 to clear. 4 BUCK1_ILIM_INT R/W 0 Latched status bit indicating that the Buck1 output current limit has been active. Write 1 to clear.

3 Reserved R/W 0

2 BUCK0_PG_INT R/W 0 Latched status bit indicating that Buck0 Power-Good event has been detected. Write 1 to clear. 1 BUCK0_SC_INT R/W 0 Latched status bit indicating that the Buck0 output voltage has been over 1 ms below short-circuit threshold level. Write 1 to clear. 0 BUCK0_ILIM_INT R/W 0 Latched status bit indicating that the Buck0 output current limit has been active. Write 1 to clear.

7.6.1.29 INT_LDO

Address: 0x1C D7 D6 D5 D4 D3 D2 D1 D0 Reserved LDO1_PG _INT LDO1_SC _INT LDO1_ILIM _INT Reserved LDO0_PG _INT LDO0_SC _INT LDO0_ILIM _INT

5 LDO1_SC_INT R/W 0 Latched status bit indicating that the LDO1 output voltage has been over 1 ms below

short-circuit threshold level. Write 1 to clear. 4 LDO1_ILIM_INT R/W 0 Latched status bit indicating that the LDO1 output current limit has been active. Write 1 to clear. 2 LDO0_PG_INT R/W 0 Latched status bit indicating that LDO0 Power-Good event has been detected. Write 1 to clear.

1 LDO0_SC_INT R/W 0 Latched status bit indicating that the LDO0 output voltage has been over 1 ms below

short-circuit threshold level. Write 1 to clear. 0 LDO0_ILIM_INT R/W 0 Latched status bit indicating that the LDO0 output current limit has been active. Write 1 to clear.

7.6.1.30 TOP_STAT

Address: 0x1D D7 D6 D5 D4 D3 D2 D1 D0 PGOOD_STAT Reserved SYNC_CLK _STAT TDIE_SD _STAT TDIE_WARN _STAT OVP_STAT Reserved Bits Field Type Default Description

7 PGOOD_STAT R 0 Status bit indicating the status of PGOOD pin:

6:5 Reserved R 00

4 SYNC_CLK_STAT R 0 Status bit indicating the status of external clock (CLKIN):

0 - External clock frequency is valid 1 - External clock frequency is not valid.

3 TDIE_SD_STAT R 0 Status bit indicating the status of thermal shutdown:

0 - Die temperature below thermal shutdown level 1 - Die temperature above thermal shutdown level.

2 TDIE_WARN

_STAT R 0 Status bit indicating the status of thermal warning: 0 - Die temperature below thermal warning level 1 - Die temperature above thermal warning level.

1 OVP_STAT R 0 Status bit indicating the status of input overvoltage monitoring:

0 - Input voltage below overvoltage threshold level 1 - Input voltage above overvoltage threshold level.

0 Reserved R 0

7.6.1.31 BUCK_STAT

Address: 0x1E D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_STAT BUCK1_PG _STAT Reserved BUCK1_ILIM _STAT BUCK0_STAT BUCK0_PG _STAT Reserved BUCK0_ILIM _STAT Bits Field Type Default Description

7 BUCK1_STAT R 0 Status bit indicating the enable/disable status of Buck1:

0 - Buck1 regulator is disabled 1 - Buck1 regulator is enabled.

6 BUCK1_PG_STAT R 0 Status bit indicating Buck1 output voltage validity (raw status)

0 - Buck1 output voltage is valid. 1 - Buck1 output voltage is invalid.

5 Reserved R 0

4 BUCK1_ILIM

_STAT R 0 Status bit indicating Buck1 current limit status (raw status) 0 - Buck1 output current is below current limit level 1 - Buck1 output current limit is active.

3 BUCK0_STAT R 0 Status bit indicating the enable/disable status of Buck0:

0 - Buck0 regulator is disabled 1 - Buck0 regulator is enabled.

2 BUCK0_PG_STAT R 0 Status bit indicating Buck0 output voltage validity (raw status)

0 - Buck0 output voltage is valid. 1 - Buck0 output voltage is invalid.

1 Reserved R 0

0 BUCK0_ILIM

_STAT R 0 Status bit indicating Buck0 current limit status (raw status) 0 - Buck0 output current is below current limit level 1 - Buck0 output current limit is active.

7.6.1.32 LDO_STAT

Address: 0x1F D7 D6 D5 D4 D3 D2 D1 D0 LDO1_STAT LDO1_PG _STAT Reserved LDO1_ILIM _STAT LDO0_STAT LDO0_PG _STAT Reserved LDO0_ILIM _STAT Bits Field Type Default Description

7 LDO1_STAT R 0 Status bit indicating the enable/disable status of LDO1:

0 - LDO1 regulator is disabled 1 - LDO1 regulator is enabled.

6 LDO1_PG_STAT R 0 Status bit indicating LDO1 output voltage validity (raw status)

0 - LDO1 output voltage is valid. 1 - LDO1 output voltage is invalid.

4 LDO1_ILIM

_STAT R 0 Status bit indicating LDO1 current limit status (raw status) 0 - LDO1 output current is below current limit level 1 - LDO1 output current limit is active.

3 LDO0_STAT R 0 Status bit indicating the enable/disable status of LDO0:

0 - LDO0 regulator is disabled 1 - LDO0 regulator is enabled.

2 LDO0_PG_STAT R 0 Status bit indicating LDO0 output voltage validity (raw status)

0 - LDO0 output voltage is valid. 1 - LDO0 output voltage is invalid.

0 LDO0_ILIM

_STAT R 0 Status bit indicating LDO0 current limit status (raw status) 0 - LDO0 output current is below current limit level 1 - LDO0 output current limit is active.

7.6.1.33 TOP_MASK_1

Address: 0x20 D7 D6 D5 D4 D3 D2 D1 D0 PGOOD_INT_ MASK Reserved SYNC_CLK _MASK Reserved TDIE_WARN _MASK Reserved I_LOAD_ READY_MASK Bits Field Type Default Description

7 PGOOD_INT

_MASK R/W 1 * Masking for Power-Good interrupt (PGOOD_INT in INT_TOP_1 register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect PGOOD_STAT status bit in TOP_STAT register. 6:5 Reserved R/W 00

4 SYNC_CLK

_MASK R/W 1 * Masking for external clock detection interrupt (SYNC_CLK_INT in INT_TOP_1 register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect SYNC_CLK_STAT status bit in TOP_STAT register. _MASK R/W 0 * Masking for thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register.

1 Reserved R/W 0

0 I_MEAS

_MASK R/W 0 * Masking for load current measurement ready interrupt (MEAS_INT in INT_TOP_1 register). 0 - Interrupt generated 1 - Interrupt not generated.

7.6.1.34 TOP_MASK_2

Address: 0x21 D7 D6 D5 D4 D3 D2 D1 D0 Reserved RESET_REG _MASK Bits Field Type Default Description 7:1 Reserved R/W 000 0000

0 RESET_REG

_MASK R/W 1 * Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register): 0 - Interrupt generated 1 - Interrupt not generated. This change of this bit by I2C writing has no effect because it will be read from OTP memory during reset.

7.6.1.35 BUCK_MASK

Address: 0x22 D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_PGF _MASK BUCK1_PGR _MASK Reserved BUCK1_ILIM _MASK BUCK0_PGF _MASK BUCK0_PGR _MASK Reserved BUCK0_ILIM _MASK Bits Field Type Default Description

7 BUCK1_PGF_MAS

K R/W 1 * Masking of Power Good invalid detection for Buck1 power good interrupt (BUCK1_PG_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.

6 BUCK1_PGR_MAS

K R/W 1 * Masking of Power Good valid detection for Buck1 Power Good interrupt (BUCK1_PG_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register. _MASK R/W 0 * Masking for Buck1 current limit detection interrupt (BUCK1_ILIM_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_STAT register.

3 BUCK0_PGF_MAS

K R/W 1 * Masking of Power Good invalid detection for Buck0 power good interrupt (BUCK0_PG_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.

2 BUCK0_PGR_MAS

K R/W 1 * Masking of Power Good valid detection for Buck0 power good interrupt (BUCK0_PG_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register. _MASK R/W 0 * Masking for Buck0 current limit detection interrupt (BUCK0_ILIM_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_STAT register.

7.6.1.36 LDO_MASK

Address: 0x23 D7 D6 D5 D4 D3 D2 D1 D0 LDO1_PGF _MASK LDO1_PGR _MASK Reserved LDO1_ILIM _MASK LDO0_PGF _MASK LDO0_PGR _MASK Reserved LDO0_ILIM _MASK Bits Field Type Default Description

7 LDO1_PGF_MASK R/W 1 * Masking of Power Good invalid detection for LDO1 power good interrupt

(LDO1_PG_INT in INT_LDO register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect LDO1_PG_STAT status bit in LDO_STAT register.

6 LDO1_PGR_MASK R/W 1 * Masking of Power Good valid detection for LDO1 power good interrupt

(LDO1_PG_INT in INT_LDO register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect LDO1_PG_STAT status bit in LDO_STAT register. _MASK R/W 0 * Masking for LDO1 current limit detection interrupt (LDO1_ILIM_INT in INT_LDO register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect LDO1_ILIM_STAT status bit in LDO_STAT register.

3 LDO0_PGF_MASK R/W 1 * Masking of Power Good invalid detection for LDO0 power good interrupt

(LDO0_PG_INT in INT_LDO register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect LDO0_PG_STAT status bit in LDO_STAT register.

2 LDO0_PGR_MASK R/W 1 * Masking of Power Good valid detection for LDO0 power good interrupt

(LDO0_PG_INT in INT_LDO register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect LDO0_PG_STAT status bit in LDO_STAT register. _MASK R/W 0 * Masking for LDO0 current limit detection interrupt (LDO0_ILIM_INT in INT_LDO register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect LDO0_ILIM_STAT status bit in LDO_STAT register.

7.6.1.37 SEL_I_LOAD

Address: 0x24 D7 D6 D5 D4 D3 D2 D1 D0 Reserved LOAD_CURRE NT_BUCK _SELECT

0 LOAD_CURRENT_

BUCK_SELECT R/W 0 Start the current measurement on the selected regulator: 0 - Buck0 1 - Buck1 The measurement is started when register is written.

7.6.1.38 I_LOAD_2

Address: 0x25 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK_LOAD_ CURRENT[8] Bits Field Type Default Description 7:1 Reserved R 000 0000

0 BUCK_LOAD_

CURRENT[8] R 0 This register describes the MSB bit of the average load current on selected regulator with a resolution of 20 mA per LSB and maximum 10.22-A current.

7.6.1.39 I_LOAD_1

Address: 0x26 D7 D6 D5 D4 D3 D2 D1 D0 BUCK_LOAD_CURRENT[7:0] Bits Field Type Default Description 7:0 BUCK_LOAD_ CURRENT[7:0] R 0000 0000 This register describes 8 LSB bits of the average load current on selected regulator with a resolution of 20 mA per LSB and maximum 10.22-A current.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

general-purpose digital output signals.

8.2 Typical Application

Figure 25. LP87332D Typical Application

8.2.1 Design Requirements

8.2.1.1 Inductor Selection

(1) Operating temperature range is up to 125°C including self temperature rise. Table 8. Recommended Inductors

8.2.1.2 Buck Input Capacitor Selection

ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI. Table 9. Recommended Buck Input Capacitor (X7R Dielectric)

8.2.1.3 Buck Output Capacitor Selection

10 μF per phase including the DC voltage rolloff, tolerances, aging, and temperature effects. selection process is at the switching frequency of the part. See Table 10.

Table 10. Recommended Buck Output Capacitors (X7R Dielectric)

8.2.1.4 LDO Input Capacitor Selection

ambient temperature range and aging. See Table 11. Table 11. Recommended LDO Input Capacitors (X7R Dielectric)

8.2.1.5 LDO Output Capacitor Selection

maximum input voltage including tolerances, ambient temperature range and aging. See Table 12. The output capacitance must be smaller than the input capacitance in order to ensure the stability of the LDO. capacitor at least 4.7-μF input capacitance. components from for VANA input supply filtering. Table 12. Recommended LDO Output Capacitors (X7R Dielectric) Table 13. Recommended Supply Filtering Components

8.2.2 Detailed Design Procedure

internally. Connect the VIN_Bx power connections together outside the package using power plane construction.

8.2.3 Application Curves

Figure 26. Buck Efficiency in PFM/PWM and Forced PWM Figure 27. Buck Efficiency in Forced PWM Mode Figure 28. Buck Efficiency in Forced PWM Mode Figure 29. Buck Output Voltage vs Load Current in Forced Figure 30. Buck Output Voltage vs Load Current in Figure 31. Buck Output Voltage vs Input Voltage in PWM

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. The VANA input and VIN_Bx buck inputs must be connected together, and they must use the same input supply. This input supply must be well regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the input current transient does not cause too high a drop in the LP87332D supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the LP87332D additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The VIN_LDOx LDO input supply voltage range is 2.5 V to 5.5 V and can be higher or lower than VANA supply voltage.

10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LP87332D make the choice of layout important. Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range. 1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and thick to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of LP87332D, as well as the trace between the negative node of the input capacitor and power PGND_Bx pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for proper device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. 2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the output capacitors of the LP87332D and the input capacitors of the load direct and wide to avoid losses due to the IR drop. 3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VANA pin.

www.ti.com SNVSAU6 – NOVEMBER 2017 Product Folder Links: LP87332D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Layout Guidelines (continued) 4. If remote voltage sensing can be used for the load, connect the LP87332D feedback pins FB_Bx to the respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. If series resistors are used for load current measurement, place them after connection of the voltage feedback. 5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx. 6. LDO performance (PSRR, noise and transient response) depend on the layout of the PCB. Best performance is achieved by placing CIN and COUT as close to the LP87332D device as practical. The ground connections for CIN and COUT must be back to the LP87332D AGND with as wide and as short of a copper trace as is practical and with multiple vias if routing is done on other layer. Avoid connections using long trace lengths, narrow trace widths, or connection through small via. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions. Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. TI strongly recommends performance of a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process by using a thermal modeling analysis software.

2 FB_B0

3 FB_B1

7 VOUT_LDO1

4 AGND

5 VANA

22 SW_B0

23 SW_B0

24 VIN_B0

28 VIN_LDO0

25 VIN_B0

26 GPO

27 PGOOD

10.2 Layout Example

Figure 55. LP87332D Board Layout

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-Dec-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LP87332DRHDR ACTIVE VQFN RHD 28 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LP8733 LP87332DRHDT ACTIVE VQFN RHD 28 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LP8733 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 23-Dec-2017 Addendum-Page 2 OTHER QUALIFIED VERSIONS OF LP87332D :

Automotive: LP87332D-Q1 NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP87332DRHDR VQFN RHD 28 3000 370.0 355.0 55.0 LP87332DRHDT VQFN RHD 28 250 220.0 205.0 50.0 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2017 Pack Materials-Page 2

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Product Information

LP87332DRHDT specifications and overview.

Summary

Dual High-Current Buck Converter and Dual Linear Regulator

Description

Dual High-Current Buck Converter and Dual Linear Regulator

Source title LP87332DRHDT Datasheet(PDF) - Texas Instruments

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