LP8728C-Q1 TI | Alldatasheet
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IOUT (A) EFFICIENCY (%) 100 D019 3.3V 2.65V 1.8V 1.2V LP8728 FB_B1 SW_B1 VOUT1 FB_B2 SW_B2 VOUT2 FB_B3 SW_B3 VOUT3 FB_B4 SW_B4 VOUT4 1.5 µH AGND GND_B1 GND_B2 GND_B3 GND_B4 EN_B1 EN_B2 EN_B3 EN_B4 PG_B1 PG_B2 PG_B3 PG_B4 Micro Controller DEFSEL AVDD BYP VIN VINVIN_B1 VINVIN_B2 VIN VIN VIN_B3 VIN_B4 VDDIO 1 µF 1 µF 10 µF 1.5 µH 1.5 µH 1.5 µH 10 µF 10 µF 10 µF 10 µF 10 µF 10 µF 10 µF Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LP8728C-Q1 SNVSA71 –FEBRUARY 2015 LP8728C-Q1Quad-OutputStep-DownDC-DCConverter
1 Features 3 Description
The LP8728C-Q1 is a quad-output Power 1• LP8728C-Q1 is an Automotive Grade Product that Management Unit (PMU), optimized for low-poweris AECQ-100 Grade 1 Qualified FPGAs, microprocessors, and DSPs for automotive• Four High Efficiency Step-Down DC-DC applications. This device integrates four highly Converters: efficient step-down DC-DC converters into one package. Each converter has high current capability– 93% Peak Efficiency (VIN = 5 V, VOUT = 3.3 V) and separate controls which allows flexibility to use– Max Output Current 1 A the device in multiple applications. All the converters– Forced PWM Operation operate above the AM band with a fixed 3.2-MHz – Soft-Start Control switching frequency. The high-side switch turn-on time of each converter is phase shifted to minimize– VOUT1 = 3.3 V input current spikes.– VOUT2 = 1.2 V Protection features include output short-circuit– VOUT3 = 1.8 V or 2.65 V (pin selectable) protection, switch current limits, input overvoltage– VOUT4 = 1.8 V protection, input undervoltage lockout, and thermal
- Separate Enable Inputs for each Converter shutdown functions. During start-up, the device controls the output slew rate to minimize outputControl voltage overshoot and the input inrush current.• Separate Power Good Outputs for each Converter
- Output Overcurrent and Input Overvoltage Device Information(1) Protection PART NUMBER PACKAGE BODY SIZE (NOM)
- Overtemperature Protection LP8728C-Q1 WQFN (28) 5.00 mm x 5.00 mm
- Undervoltage Lockout (UVLO) (1) For all available packages, see the orderable addendum at the end of the datasheet.
2 Applications space
- FPGA, DSP Core Power space• Processor Power for Mobile Devices space• Peripheral I/O Power space• Automotive Safety Cameras
- Automotive Infotainment space space Simplified Schematic Efficiency An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNVSA71 –FEBRUARY 2015 www.ti.com Table of Contents
4 Revision History
February 2015 * Initial release.
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FB_B1 PG_B4 EN_B4 PG_B2 EN_B2 PG_B1 FB_B4 FB_B2 DEFSEL EN_B1 AVDD BYP AGND FB_B3 GND_B3SW_B3VIN_B3 EN_B3 VIN_B4SW_B4GND_B4 GND_B2SW_B2VIN_B2 PG_B3 VIN_B1SW_B1GND_B1 TOP VIEW LP8728C-Q1 www.ti.com SNVSA71 –FEBRUARY 2015
5 Pin Configuration and Functions
WQFN (RSG) Package
28 Pins
TYPE(1) DESCRIPTION NUMBER NAME
1 EN_B1 D/I Enable Buck 1
2 VIN_B1 P Positive power supply input for Buck 1
3 SW_B1 P Switch node for Buck 1
4 GND_B1 G Power ground for Buck 1
5 GND_B2 G Power ground for Buck 2
6 SW_B2 P Switch node for Buck 2
7 VIN_B2 P Positive power supply input for Buck 2
8 FB_B2 A Feedback pin for Buck 2. Referenced against AGND.
9 EN_B2 D/I Enable Buck 2
10 PG_B2 D/O Open-drain Power Good output for Buck 2
11 DEFSEL D/I Buck 3 output voltage selection pin
12 PG_B3 D/O Open-drain Power Good output for Buck 3
13 EN_B3 D/I Enable Buck 3
14 FB_B3 A Feedback pin for Buck 3. Referenced against AGND.
15 VIN_B3 P Positive power supply input for Buck 3
16 SW_B3 P Switch node for Buck 3
17 GND_B3 G Power ground for Buck 3
18 GND_B4 G Power ground for Buck 4
19 SW_B4 P Switch node for Buck 4
(1) A: Analog Pin, G: Ground Pin, P: Power Pin, O: Output Pin, D/I: Digital Input, D/O: Digital Output. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LP8728C-Q1
SNVSA71 –FEBRUARY 2015 www.ti.com Pin Functions (continued) PIN TYPE(1) DESCRIPTION NUMBER NAME
20 VIN_B4 P Positive power supply input for Buck 4
21 EN_B4 D/I Enable Buck 4
22 FB_B4 A Feedback pin for Buck 4. Referenced against AGND.
23 PG_B4 D/O Open-drain Power Good output for Buck 4
24 AGND G Analog ground
25 BYP A Internal 1.8-V supply voltage capacitor pin. A ceramic low-ESR 1-μF capacitor should be connected from this pin to AGND. The BYP voltage is generated internally, do not supply or load this pin externally.
26 AVDD P Analog positive power supply pin (VIN level)
27 PG_B1 D/O Open-drain Power Good output for Buck 1
28 FB_B1 A Feedback pin for Buck 1. Referenced against AGND. Exposed die attachment pad should to be connected to GND plane with thermal viasDAP Die Attachment Pad to improve the thermal performance of the system.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VIN Voltage on power pins (AVDD, VIN_Bx) –0.3 6 V VFB Voltage on feedback pins (FB_Bx) –0.3 6 V VSW Voltage on buck converter switch pins (SW_Bx) (GND_Bx – 0.2 V) to (VIN_Bx + 0.2 V) with 6 V max V VDIG Voltage on digital pins (PG_Bx, EN_Bx, DEFSEL) (AGND – 0.2V) to (AVDD + 0.2 V) with 6 V max V VBYP Voltage on BYP pin –0.3 2 V TJ(MAX) Maximum operating junction temperature(2) 150 °C Maximum lead temperature (Soldering) See(3) Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typical) and disengages at TJ = 130°C (typical). (3) For detailed soldering specifications and information, please refer to Texas Instruments Application Note Leadless Leadframe Package (LLP) SNOA401.
6.2 ESD Ratings
Human-body model (HBM), per AEC Q100-002(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per AEC Q100-011 ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT VIN Input voltage on AVDD, VIN_B1, VIN_B2, VIN_B3 and VIN_B4 pins 4.5 5 5.5 V TA Operating ambient temperature(2) –40 125 °C Effective output capacitance during operation.COUT 5 10 12 µFMin value over TA –40°C to 125°C. Effective inductance during operationL 0.47 1.5 2 µFMin value over TA –40°C to 125°C. (1) All voltage values are with respect to network ground terminal. (2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA(max) = TJ(max) – (RθJA × PD(max)) Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LP8728C-Q1
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6.4 Thermal Information
THERMAL METRIC(1) WQFN (RSG) UNIT RθJA Junction-to-ambient thermal resistance(2) 37.7 RθJCtop Junction-to-case (top) thermal resistance 24.5 RθJB Junction-to-board thermal resistance 10.8 °C/W ΨJT Junction-to-top characterization parameter 0.3 ΨJB Junction-to-board characterization parameter 10.8 RθJCbot Junction-to-case (bottom) thermal resistance 2.7 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) Calculated using 4-layer standard JEDEC thermal test board with 5 thermal vias between the die attach pad in the first copper layer and second copper layer.
6.5 Electrical Characteristics(1)(2)
Unless otherwise noted, VIN = 5 V, typical values apply for TA = 25°C, and minimum/maximum limits apply over junction temperature range, TJ = –40°C to 125°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Shutdown supply current into powerISHDN EN_Bx = 0 V 1 6 μAconnections IOP Operating current All buck-converters active, IOUT = 0 mA 20 mA LOGIC INPUTS (EN_Bx, DEFSEL) VIL Input low level 0.4 V VIH Input high level 1.6 V EN_Bx and DEFSEL internalRPD_DI 300 520 820 kΩpulldown resistance TH_MIN Minimum EN_Bx high time 1 ms TL_MIN Minimum EN_Bx low time 10 µs LOGIC OUTPUTS (PG_Bx) VOL Output low level ISINK = 3 mA 0.4 V RPU Recommended pullup resistor 10 kΩ BUCK CONVERTERS VOUT1 Output voltage for Buck 1 Fixed voltage 3.3 V VOUT2 Output voltage for Buck 2 Fixed voltage 1.2 V DEFSEL = 1 2.65 VOUT3 Output voltage for Buck 3 V DEFSEL = 0 1.8 VOUT4 Output voltage for Buck 4 Fixed voltage 1.8 V VFB_Bx Output voltage accuracy –3% 3% Line regulation 4.5 V ≤ VIN_Bx ≤ 5.5 V, ILOAD = 10 mA 3 mV ΔVOUT Load regulation VIN = 5 V, 100 mA ≤ ILOAD ≤ 900 mA 3 mV DC loadIOUT Output current 1000 mATA = 25°C fSW Switching frequency 3.03 3.2 3.37 MHz GBW Gain bandwidth 300 kHz ILIMITP High-side switch current limit 1200 1500 1800 mA ILIMITN Low-side switch current limit Reverse current 500 mA RDSONP Pin-pin resistance for PFET IOUT = 200 mA 210 300 mΩ RDSONN Pin-pin resistance for NFET IOUT = 200 mA 140 240 mΩ (1) All voltage values are with respect to network ground terminal. (2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5 V and TJ = 25°C.
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www.ti.com SNVSA71 –FEBRUARY 2015 Electrical Characteristics(1)(2) (continued) Unless otherwise noted, VIN = 5 V, typical values apply for TA = 25°C, and minimum/maximum limits apply over junction temperature range, TJ = –40°C to 125°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ILK_SW Switch pin leakage current VOUT = 1.8V 1 µA Pulldown resistor from FB_Bx pin to Only active when converter disabled.RPD_FB 40 70 100 ΩGND All limits apply for TA = 25°C KRAMP Slew rate control DEFSEL from 0 to 1 10 mV/µs Time from first EN_Bx high to start ofTSTART Start-up time 420 µsswitching KSTART Soft-start VOUT slew rate 18 mV/µs VOLTAGE MONITORING Power good threshold for voltage rising 93.5% 96% 98% VPG Power good threshold voltage Power good threshold for voltage falling 91% 93% 95% Voltage monitored on AVDD Pin, V5.5 5.7 5.9Input overvoltage protection trigger voltage risingVOVP point Hysteresis 80 mV Voltage monitored on AVDD Pin, V2.7Input undervoltage lockout (UVLO) voltage fallingVUVLO threshold. Hysteresis 80 mV THERMAL SHUTDOWN AND MONITORING Threshold, temperature rising 150 TSD Thermal shutdown °C Hysteresis 20
6.6 System Characteristics(1)(2)(3)
Typical values apply for TA = 25°C. Unless otherwise noted, VIN = 5 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOUT 10% max load → 90% max load, 1- 70 mVµs load step Load transient response IOUT 90% max load → 10% max load, 1-ΔVOUT 70 mVµs load step VIN_Bx stepping 4.5 V ↔ 5.5 V, tRISE =Line transient response 20 mVtFALL = 10 µs, IOUT = 400 mA VRIPPLE Output voltage ripple COUT ESR = 10 mΩ, IOUT = 200 mA 10 mVPP VOUT = 3.3 V, IOUT = 300 mA 94% VOUT = 2.65 V, IOUT = 300 mA 92% η Efficiency VOUT = 1.8 V, IOUT = 300 mA 89% VOUT = 1.2 V, IOUT = 300 mA 85% (1) All voltage values are with respect to network ground terminal. (2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5 V and TJ = 25°C. (3) System Characteristics are highly dependent on external components and PCB layout. System Characteristics are verified using inductor type: TOKO MDT2520-CN1R5M, input and output capacitor type: MuRata GRM21BR71A106KE51L. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LP8728C-Q1
6.7 Typical Characteristics
Figure 2. Switching Frequency vs TemperatureFigure 1. Efficiency vs Output Current Figure 3. Buck1 Load Regulation Figure 4. Buck1 Line Regulation Figure 5. Buck2 Load Regulation Figure 6. Buck2 Line Regulation
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Figure 7. Shutdown Current Consumption Figure 8. Active Mode Current Consumption
EN_B1 Thermal Shutdown Oscillator Reference Voltage OTP UVLO DEFSEL PG_B1 VIN_B1 10 µF FB_B1 1.5 µHSW_B1 VIN VOUT2 VOUT1 PG_B2 PG_B3 PG_B4 EN_B2 EN_B3 EN_B4 VIN VIN VIN VOUT3 VOUT4 VIN LDO 10 µF Buck1 (Active Pulldown) Buck2 (Active Pulldown) VIN_B2 10 µF FB_B2 1.5 µHSW_B2 10 µF Buck3 (Active Pulldown) VIN_B3 10 µF FB_B3 1.5 µHSW_B3 10 µF Buck4 (Active Pulldown) VIN_B4 10 µF FB_B4 1.5 µHSW_B4 10 µF AGND AVDD BYP GND_B1 GND_B2 GND_B3 GND_B4 1 µF 1 µF LP8728C-Q1 SNVSA71 –FEBRUARY 2015 www.ti.com
7 Detailed Description
7.1 Overview
The LP8728C-Q1 has four integrated high-efficiency buck converters. Each buck converter has individual enable input and power good output pins. When the first enable pin is pulled high there is a 420-µs start-up delay when the device wakes up from the shutdown mode and all internal reference blocks are started up. Once reference blocks have settled, the corresponding buck converter turns on. Buck cores utilize the soft-start feature to limit the inrush current during start-up. Once a buck output reaches 96% (typical) of the desired output voltage, the power-good pin is pulled high (see Figure 9). When at least one buck core is active, the remaining buck converters will start up without any start-up delay. If the output voltage drops below 93% (typical) of desired voltage due to, for example, an overload condition, the corresponding power-good pin is pulled low. The power-good signal is always held low for at least 50 ms. When the enable pin is pulled low, the corresponding buck converter's power good signals are set low, and the buck converter is instantly shut down. An output capacitor is then discharged through an internal 70-Ω (typical) pulldown resistor. The pulldown resistor is connected between buck feedback pin and ground and is only active when the enable pin is set low. When all enable signals are pulled low, the LP8728C-Q1 enters a low current shutdown mode.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Buck Information
minimize the input current ripple (see Figure 20).
7.3.1.1 Features
- Synchronous rectification
- Current mode feedback loop with PI compensator
- Forced PWM operation
- Soft start
- Power-good output
- Overvoltage comparator In addition to the aforementioned features, Buck3 output voltage can be selected with the DEFSEL pin. If the DEFSEL pin is pulled low, VOUT3 is set to 1.8 V. If DEFSEL is pulled high, VOUT3 is set to 2.65 V.
Figure 9. Buck Converter Start-up And Shutdown
7.3.2 Thermal Shutdown (TSD)
Buck2 → Buck3 → Buck4 sequence. A 500-µs delay is included between each buck start-up. Figure 10. TSD Timing Diagram
7.3.3 Undervoltage Lockout (UVLO)
If input voltage drops below 2.7 V (typ.) the PG_Bx pins are pulled low and the buck converters are shut down. input voltage rises above UVLO level. pins are released high once corresponding output voltage has settled. Figure 11. UVLO Operation
7.3.4 Overvoltage Protection (OVP)
included between each buck start-up. 50 ms has elapsed and the corresponding output voltage has settled (Figure 12). Figure 12. OVP Duration Less Than 50 ms
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Figure 13. OVP Duration More Than 50 ms
7.4 Device Functional Modes
7.4.1 Shutdown Mode
regulators and all internal blocks are disabled.
7.4.2 Active Mode
down all internal reference blocks and enters Shutdown mode. (typical) of desired voltage power good pin is set back high. Power good signal is held low for at least 50 ms.
lasted for 5 ms all buck converters are shut down. In case of UVLO fault buck regulators are instantly shut down. safety delay before power-up sequence. Figure 14. Device Functional Modes
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
Figure 15. LP8728C-Q1 Typical Application Schematic
8.2.1 Design Requirements
8.2.2 Detailed Design Procedure
8.2.2.1 Inductor
and saturation current. The DC resistance of the inductor directly effects the efficiency of the converter. inductor should have a saturation current rating equal or higher than the high-side switch current limit (1500 mA). enough to withstand the high switching currents.
8.2.2.2 Input and Output Capacitors
VIN_Bx. The input capacitor capacitance can be increased without any limit for better input voltage filtering. possible. Routing from input capacitor to VIN_Bx pins should be done on top layer without using any vias. low ESR value have lowest output voltage ripple and are recommended. Table 1. Recommended External Components
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8.2.3 Application Performance Plots
Figure 16. Short-Circuit Waveforms Figure 17. Start-up Delay Figure 18. Load Transient Response Figure 19. Line Transient Response Figure 20. Switch Turn-on Phase Shifting
9 Power Supply Recommendations
from the device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
- AVDD and BYP pins must be bypassed to ground. 1-µF ceramic capacitor is recommended. Place the capacitors close to the AVDD, BYP, and AGND pins.
- AGND pin must be tied to the PCB ground plane. Use multiple vias to minimize the inductance.
- AVDD pin must be connected to PCB VIN plane. Use multiple vias to minimize the inductance.
- Place the buck converter input capacitors as close to the buck input voltage and buck ground pins as possible.
- Place the buck converter output capacitors and inductors so that the buck converter switching loops can be routed on top layer. Try to minimize the area of the switching loops.
- Keep the trace width from switch pin to inductor wide enough to withstand the switching currents. Avoid any excess copper on the switch node to minimize parasitic switch node capacitance.
- Connect the exposed thermal pad to ground plane with multiple thermal vias.
- Avoid routing digital signals directly under the switching loops to avoid interferences.
10.2 Layout Example
Figure 21. LP8728C-Q1 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Related Documentation
For related documentation see the following: Texas Instruments Application Note 1187 Leadless Leadframe Package (LLP) (SNOA401). See Using the LP8728EVM Evaluation Module (SNVU231) for more information about LP8728 evaluation module.
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LP8728C-Q1
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LP8728QSQX-C/NOPB Active Production WQFN (RSG) | 28 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 8728Q-C LP8728QSQX-C/NOPB.A Active Production WQFN (RSG) | 28 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 8728Q-C LP8728QSQX-C/NOPB.B Active Production WQFN (RSG) | 28 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 8728Q-C (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8728QSQX-C/NOPB WQFN RSG 28 4500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2015 Pack Materials-Page 2
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