LP8727TMX/NOPB

LP8727 TI1 | Alldatasheet

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www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 Micro/MiniUSBInterfacewithIntegrated28VCharger Check forSamples: LP8727 1FEATURES APPLICATIONS 2• USB MultiplexingSwitches • GSM, GPRS, EDGE, CDMA & WCDMA handsets– High-Speed USB on USB and UART Inputs

PortableMedia Players/MP3 Players– NegativeVoltageRailon Audio Inputs – InternalLDO forID Detectionand MIC Bias DESCRIPTION– Compatible withUSB Charging The LP8727 is designed to provide automaticSpecificationRev. 1.1 multiplexingswitches between Micro/MiniUSB – DSS InputforDefaultSwitch Connection connector and USB, UART and Audio paths in cellularphone applications.Italsocontainsa single-– Low-Power MIC Standby Mode input Li-Ionbatterycharger and an overvoltage-• LinearCharge withSingleInput protectedLDO. Programming ishandledviaan I2C- – 28 OVP on VBUS Input compatible Serial Interfaceallowing control of charger,multiplexingswitches,and readingstatus– High-CurrentMode forProductionTest informationofthedevice.– Thermal Regulation The multiplexingswitcheson USB and UART support• Over-VoltageProtectedLDO forUSB high-speedUSB, and Audio inputscan be driventoTransceiversand PMU Wakeup negativevoltagerail.The LP8727 iscompatiblewith• UVLO (UndervoltageLock Out) USB chargingspecificationsrev1.1fromUSB IF.
InterruptRequest toReduce SW Polling The Li-Ionchargerrequiresfew externalcomponents– USB /ID Detection and integratesthepower FET. Chargingisthermally – SEND /END Button Detection regulatedtoobtainthemost efficientchargingratefor a given ambient temperature.It has Overvoltage– Mic Removal Protection(OVP) circuitatthechargerinputprotects– OVLO /UVLO on VBUS thePMU from inputvoltagesup to+28V, eliminating – Charger Status theneed forany externalprotectioncircuitry.
Thermal Shutdown Protection An overvoltage-protectedLDO which can supplyup
I2C-compatibleSerialInterface to 50 mA isdesignedforpoweringup a low-voltage USB transceiveror waking up a PMU (Power• 25-Bump 0.4mm PitchThin DSBGA Package Management Unit)when an externalpower source (eitherUSB VBUS or walladapter)isconnectedto theUSB connector. The LP8727 PMU isavailablein 25-bump 0.4 mm pitchthinDSBGA package (2.015mm x 2.015mm). Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

(2.3V/2.6V) ID/Ear Jack Detection USB Charger Detection USB Detection Micro/Mini USB Connector USB 2.0 High Speed UART AUDIO Serial Interface and Control BB 28V Charger - + GND LP8727 VBAT DN DP AUD1 AUD2 MIC VBUS SCL SDA INT\\ ID CAP RES GND 2.2 k: 3.5V F 620: 200 k: 800 k:100 k: 100 k: USB Xcvr or PMU DSS 300 k: F 1.5 k: I/O Supply 10 k: 100: 100: 1.5 k: USB LDO 28V OVP 50 mA @ 4.85V EXPDET F Default Switch Status UVLO OSC EPROM Voltage Reference Charge Pump Thermal Shutdown C1COMP 1.8V VCC Supply 100 k: ADC VCC 200 k: LP8727 SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com TypicalApplicationDiagram

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INT\\ RES GND CAP A B C D E GND GND VBATEXPDET LP8727 www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 Connection Diagram Figure1. 25-Bump (0.4mm Pitch)DSBGA Package LP8727 PIN DESCRIPTIONS (1) PIN NAME PIN # TYPE DESCRIPTION AUD1 B1 AI StereoAudioinput(Left). AUD2 C1 AI StereoAudioinput(Right). CAP D2 A InternalLDO output.Connecta 1.0µF ceramiccapacitortoGND. D- E3 DI/O Common dataI/O.ConnecttoD- on Mini/MicroUSB connector. D+ E2 DI/O Common dataI/O.ConnecttoD+ on Mini/MicroUSB connector. DN A2 DI/O USB differentialdataI/O(-). DP A3 DI/O USB differentialdataI/O(+). Defaultswitchstatusinput.Internallypulleddown witha 300 kΩ resistor.DSS D3 A LogichighforUART startupand logiclowforUSB startup. OvervoltageprotectedLDO outputforlow-voltageUSB system.Connecta 1.0EXPDET B5 P µF ceramiccapacitortoGND. GND C2, C3, C4, D4 G Ground. ID E1 DI USB ID Input.ConnecttoID on Mini/MicroUSB connector. Open-drainoutputforinterrupt,activelow.Typ.10 kΩ pull-upresistorisINT\\ B2 DO required. MIC A1 AO Microphoneoutput. BiasoutputforID detectionand Microphone.Connecta 2.2kΩ resistortoIDRES D1 A pin. SCL B4 DI Serialinterfaceclockinput.Connecta 1.5kΩ pullupresistor. SDA B3 DI/O Serialinterfacedatainput/output.Connecta 1.5kΩ pullupresistor. U1 A5 DI/O UART dataRx /USB differentialdataI/O(-). U2 A4 DI/O UART dataTx /USB differentialdataI/O(+). Main batteryconnection.VBAT C5, D5 P Requires10 µF ceramiccapacitorwhen a batteryisnotconnected. VBUS E4,E5 P USB VBUS input. (1) A:AnalogPin,D: DigitalPin,I:InputPin,DI/ODigitalInput/OutputPin,G: Ground,O: OutputPin,I/O:Input/OutputPin,P:Power Connection Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LP8727

SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2)(3)(4) INPUT VOLTAGE VBUS toGND −0.3Vto+28V VBAT, EXPDET, CAP [wrt.GND] −0.3Vto+6.0V SCL, SDA, INT\\,DSS [wrt.GND] −0.3Vto(VVBAT +0.3V) CP_EN = 1 D+, D −,AUD1, AUD2 −2.1Vto(VSWPOS) + 0.3V) DP, DN, U1, U2, ID,MIC, RES −0.3Vto(VSWPOS) + 0.3V) CP_EN = 0 D+, D −,DP, DN, AUD1, RES −0.3Vto(VCC + 0.3V) AUD2, U1, U2, ID,MIC TEMPERATURE JunctionTemperature(TJ-MAX ) 150°C StorageTemperatureRange −65 to150°C Maximum Lead 260°CTemperature(Soldering,10 sec.) (1) AbsoluteMaximum Ratingsarelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsareconditionsunderwhich operationofthedeviceisensured.OperatingRatingsdo notimplyensuredperformancelimits.Forensuredperformancelimitsand associatedtestconditions,see theElectricalCharacteristicstables. (2) AllvoltagesarewithrespecttothepotentialattheGND pin. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (4) Internalthermalshutdowncircuitryprotectsthedevicefropermanentdamage. Thermalshutdownengages atTJ = 150°C (typ.)and disengagesatTJ = 130°C. Alsoengages at160°C and disengages115°C. OperatingRatings(1)(2) INPUT VOLTAGE VBAT 2.5Vto5.5V VBUS 3.5Vto7V TEMPERATURE JunctionTemperature(TJ)Range −40°C to125°C AmbientTemperature(TA)Range (3) −40°C to85°C (1) AbsoluteMaximum Ratingsarelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsareconditionsunderwhich operationofthedeviceisensured.OperatingRatingsdo notimplyensuredperformancelimits.Forensuredperformancelimitsand associatedtestconditions,see theElectricalCharacteristicstables. (2) AllvoltagesarewithrespecttothepotentialattheGND pin. (3) Inapplicationswhere highpower dissipationand/orpoorpackage resistanceispresent,themaximum ambienttemperaturemay have to be de-rated.Maximum ambienttemperature(TA-MAX) isdependenton themaximum operatingjunctiontemperature(TJ-MAX),The maximum power dissipationofthedeviceintheapplication(PD-MAX) and thejunctiontoambientthermalresistanceofthepackage (θJA)intheapplication,as givenby thefollowingequation:TA-MAX = TJ-MAX (θJA x PD-MAX). Due tothepulsednatureoftestingthe part,thetemp intheElectricalCharacteristictableisspecifiedas TA = TJ.

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www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 ESD Rating(1) VBUS, VBAT, D+ D −,ID IEC61000-4-2In-module ±8kV ContactDischarge Testing@ USB Connector ±15kV AirDischarge Human Body ±2 kV Machine Model ±150V (1) The human-body model is100 pF dischargedthrough1.5kΩ.The machine model isa 200 pF capacitordischargeddirectlyintoeach pin,MIL-STD-883 3015.7. Thermal Properties Junction-to-AmbientThermalResistance(θJA)(1) 46°CThinDSBGA-25 (1) Junction-to-ambientthermalresistanceishighlyapplicationand boardlayoutdependent.Inapplicationswhere highpower dissipation exists,specialcaremust be giventothermaldissipationissuesinboarddesign. ElectricalCharacteristics(1)(2) LimitsinstandardtypefaceareforTJ = 25°C. Limitsinboldfacetypeapplyovertheoperatingambienttemperaturerange (−40°C ≤ TJ ≤ +125°C).Unlessotherwisenoted,specificationsapplytotheTypicalApplicationCircuitwithVVBAT = 3.7V, VVBUS = 5V. Symbol Parameter Conditions Typ Min Max Units VVBAT VBAT VoltageRange 2.5 5.5 V VVBUS VBUS VoltageRange 3.5 7 VVBUS = 5V 4.2 VCC InternalSupplyVoltage VVBUS = 0V VVBAT V UNDERVOLTAGE LOCKOUT V QUIESCENT CURRENTS CP_EN = ADC_EN = SEMREM = 0IVBAT (STBY) VBAT StandbyIq 3.8 20USB_DET_DIS = 1 RegisterDefault@ VVBAT = 3.7VIVBAT (SUP1) VBAT SupplyCurrent1 42 90VVBUS = 0V RegisterDefault@ VVBAT = 3.7V IVBAT (SUP2) VBAT SupplyCurrent2 ADC_EN = SEMREM = 1,VVBUS = 60 120 µA0V CP_EN = ADC_EN = SEMREM = 0 IVBUS (STBY) VBUS StandbyIq USB_DET_DIS = CHG_OFF = 1, 90 200 EXPDET_EN = 0 RegisterDefault@V VBUS = 5V,NoIVBUS (SUP) VBUS SupplyCurrent 250 400loadon VBAT (No battery) LOGIC AND CONTROL INPUTS SDA, SCL 0.4 VIL InputLow Level V DSS 0.4 SDA, SCL 1.4 VIH InputHighLevel V DSS 1.4 AlllogicinputsILEAK InputCurrent -5 +5 µAOver pinVoltagerange DSS IN InputResistance(2) DSS PulldownResistortoGND 300 kΩ (1) AllvoltagesarewithrespecttothepotentialattheGND pin. (2) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotensured,butdo representthemost likely norm. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LP8727

SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com ElectricalCharacteristics(1)(2)(continued) LimitsinstandardtypefaceareforTJ = 25°C. Limitsinboldfacetypeapplyovertheoperatingambienttemperaturerange (−40°C ≤ TJ ≤ +125°C).Unlessotherwisenoted,specificationsapplytotheTypicalApplicationCircuitwithVVBAT = 3.7V, VVBUS = 5V. Symbol Parameter Conditions Typ Min Max Units LOGIC AND CONTROL OUTPUTS INT\\,IOUT = 2mA 0.4 VOL OutputLow Level V SDA, ISINK = 3mA 0.4 ID DETECTION LDO IOUT = 500 µA,VOUT = 2.3VVOUT OutputVoltageAccuracy -3 +3 %IOUT = 500 µA,VOUT = 2.6V IOUT OutputCurrentRating 1 mA

10 Hz ≤ f≤ 100 kHzeN OutputNoiseVoltage 15 µVRMSC OUT = 1µF(2)

f= 10 kHz,C OUT = 1µFPower SupplyRipplePSRR 75 dBRejectionRatio IOUT = 20 mA (2) ExternalOutputCapacitanceC OUT See (2) 1.0 0.6 20 µFforStability EXPDET LDO IOUT = 1mA, VOUT = 4.85V@ VVBUSVOUT OutputVoltageAccuracy -5 +3 %= 5V VDO DropoutVoltage IOUT = 50 mA @ VVBUS = 5V 330 mV IOUT(MAX) OutputCurrentRating 50 mA ISC ShortCircuitCurrentLimit VOUT = 0V 330 mA ExternalOutputCapacitanceC OUT See (3) 1.0 0.6 20 µFforStability (3) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotensured,butdo representthemost likely norm. MultiplexerSwitches ElectricalCharacteristics Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Unlessotherwisenoted,VVBAT = 3.7V,VBUS is disconnected.Limitsappearinginboldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ = −40°C to +125°C.(1) Symbol Parameter Conditions Typ Min Max Units CP_EN = 0 0 VCC VDP,DN AnalogSignalRange V CP_EN = 1 0 VSWPOS R SWONUSB On Resistance 2.5 6 On ResistanceMatchΔR SWONUSB 0V < VD+ orVD-< 1V 0.5 ΩBetween Channels R FLATUSB On ResistanceFlatness 0.5 ILEAKUSB(OFF) OffLeakage Current(2) −360 360 0V < VD+ orVD-< 3.3V,CP_EN = 1 nA ILEAKUSB(ON) On Leakage Current(2) −360 360 UART ANALOG SWITCHES (U1,U2) CP_EN = 0 0 VCC VU1, U2 AnalogSignalRange V CP_EN = 1 0 VSWPOS R SWONART On Resistance 2.5 6 On ResistanceMatchΔR SWONART 0V < VD+ orVD-< 1V 0.5 ΩBetween Channels R FLATURT On ResistanceFlatness 0.5 (1) Junction-to-ambientthermalresistanceishighlyapplicationand boardlayoutdependent.Inapplicationswhere highpower dissipation exists,specialcaremust be giventothermaldissipationissuesinboarddesign. (2) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotensured,butdo representthemost likely norm.

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www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 MultiplexerSwitches ElectricalCharacteristics(continued) Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Unlessotherwisenoted,VVBAT = 3.7V,VBUS is disconnected.Limitsappearinginboldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ = −40°C to +125°C.(1) Symbol Parameter Conditions Typ Min Max Units ILEAKUART(OFF) OffLeakage Current(2) −360 360 0V < VD+ orVD-< 3.3V,CP_EN = 1 nA ILEAKUART(ON) On Leakage Current(2) −360 360 AUDIO ANALOG SWITCHES (AUD1, AUD2) CP_EN = 0 0 VCC VAUD1, AUD2 AnalogSignalRange V CP_EN = 1 VSWNEG VSWPOS R SWONAUD On Resistance 1.6 3.6 On ResistanceMatchΔR SWONAUD −1.8V< VD+ orVD-< 1.8V 0.2 ΩBetween Channels R FLATAUD On ResistanceFlatness 0.5 ILEAKUAUD(OFF) OffLeakage Current(2) −360 360−1.8V< VD+ orVD-< 1.8V, nACP_EN = 1ILEAKUAUD(ON) On Leakage Current(2) −360 360 R SHUNT ShuntResistor ISHUNT = 10 mA 100 30 180 Ω MIC ANALOG SWITCHES (MIC) CP_EN = 0 0 VCC VMIC AnalogSignalRange V CP_EN = 1 VSWNEG VSWPOS R SWONMIC On Resistance 3 10 Ω R FLATMIC On ResistanceFlatness 0.8 0V < VID< 1.6V ILEAKMIC(OFF) OffLeakage Current(2) −360 360 nA ILEAKMIC(ON) On Leakage Current(2) −360 360 DYNAMIC TCP_EN Charge Pump StartupTime 1 ms MIC Low-Power DetectionTMICLPDP 117 50 175 µsPulseTime MIC_LP = 1,SEMREM = 1 MIC Low-Power DetectionTMICLPD 100 45 155Period msTDEB ComparatorDebounce Time 60 30 100 TONSW AnalogSwitchTurn-onTime 1 TOFFSW AnalogSwitchTurn-offTime RL = 50Ω(3)(4) 10 µs TBBM Break-Before-Make 0 VISO Off-Isolation(5) −108R L = 50Ω,C L = 5pF,f=20 kHz dBVD+ orVD-= 1VRMS (6)(4) VCT Crosstalk −107 f= 20 Hz to20 kHz,V VD+ orVD-=TotalHarmonicDistortion 0.25VRMS ,R L = 30Ω,DC Bias= 0V, 0.05PlusNoiseAUD1, AUD2 T = 25°C THD+N AUD % f= 20 Hz to20 kHz,V VD+ orVD-=TotalHarmonicDistortion 0.4VRMS ,R L = 1kΩ,DC Bias= 0.8V, 0.05PlusNoiseMIC T = 25°C (3) Alltimingismeasured using10% and 90% levels. (4) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotensured,butdo representthemost likely norm. (5) Off-isolation= 20log[VD+/D− /(VNO1/2orVNC1/2),VD+/D− = output,VNO1/2 orVNC1/2 = inputtooffswitch. (6) Crosstalkismeasured between any two switches. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LP8727

SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com Charger ElectricalCharacteristics Typicalvaluesand limitsinstandardtypefaceareforTJ = 25°C. Limitsinboldfacetypeapplyovertheentirejunction temperaturerange(−40°C to+125°C).(1)(2)(3) Symbol Parameter Conditions Typ Min Max Units Over VoltageProtection ChargerinputisturnedoffifvoltageisVOV 6.9 6.7 7.2 VThreshold above thisthreshold Over VoltageProtectionVOV_HYS 170 120 220 mVThresholdHysteresis VVBUS VBUS OperatingRange 4.45 6 V VVBUS -VVBAT (Rising) 250 VOK_CHG VBUS OK TripPoint mV VVBUS -VVBAT (Falling) 40 VTERM = 4.2V,ICHG = 50 mA −0.35 +0.35 VTERM TerminationVoltage VTERM ismeasured at10% ofthe % −1 +1programmed ICHG current Chargerpass transistorONR DSON_CHG ICHG = 400 mA 250 400 m Ωresistance 4.45V≤ VVBUS ≤ 6VVBUS Programmable Full- VVBAT < VVBUS -VOK_VBUS 90 1100 mARate ChargingCurrent VFULL_RATE < VVBAT < VTERM (4) ICHG Full-ratechargingcurrent ICHG = 400 mA −5 +5 %tolerance 2.2V< VVBAT < VFULL_RATEIPRECHG Pre-chargecurrent 80 60 100 mA80 mA optionselected IVBUS(MAX) Maximum InputCurrent VVBUS -VVBAT ≤ 0.8V 2.3 A Full-rateQualification VVBAT Rising,TransitionfromPre-VFULL_RATE 2.6 2.5 2.7 VThreshold chargetoFull-rateCharging End-of-chargeCurrent,%IEOC 0.1C optionselected 10 %ofFull-rateCurrent RegulatedJunctionTREG 115°C optionselected(5) 115 °CTemperature DETECTION AND TIMING (5) VVBUSDET VBUS DetectionThreshold 3.5 3 4 V TPOK Power OK Debounce Time VVBUS > VVBAT + VOK_CHG 30 Debounce Time fromPre- msPre-chargetofull-ratechargingTPRE_FULL Charge toFull-rate 55transitionTransition Debounce Time fromCV toTEOC 400 msEnd-of-ChargeTransition TCHG Charge SafetyTimer Pre-chargeMode 45 minutes (1) Junction-to-ambientthermalresistanceishighlyapplicationand boardlayoutdependent.Inapplicationswhere highpower dissipation exists,specialcaremust be giventothermaldissipationissuesinboarddesign. (2) Dropoutvoltageisthevoltagedifferencebetween theinputand theoutputatwhichtheoutputvoltagedropsto100 mV belowits nominalvalue. (3) The parametersintheelectricalcharacteristictablearetestedunderopen loopconditionsatVbat= 3.7unlessotherwisespecified.For performanceovertheinputvoltagerangeand closedloopcondition,refertothedatasheetcurves. (4) The minimum inputvoltageequalsVOUT (nom)+ 0.5Vor2.5V,whicheverisgreater. (5) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotensured,butdo representthemost likely norm.

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www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 LP8727 ControlRegisters I2C-CompatibleSlaveAddress: 7'h27(6) PORADDR REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0DEFAULT 0x00 DEVICE ID 0011xxxx VENDOR ID CHIP_REV 0x01 CONTROL1 x0000001 RESV'D ID_2P2 ID_620 ID_200 VLDO SEMREN ADC_EN CP_EN USB_DET_0x02 CONTROL2 0000xx01 INTPOL INT_EN MIC_LP CP_AUD RESV'D RESV'D CHG_TYP DIS SW0x03 x0000000 RESV'D MIC_ON DP2 DM1CONTROL MR_ SEND/E0x04 INT_STAT1 00000000 CHGDET VBUS IDNOCOMP ND 0x05 INT_STAT2 00000000 CHG TSHD TMP OVLO UVLO RESV'D RESV'D RESV'D 0x06 STATUS1 00000000 DCPORT CHPORT CHG_STAT RESV'D RESV'D RESV'D C1COMP 0x07 STATUS2 00000000 TMP_STAT RESV'D RESV'D RESV'D RESV'D RESV'D CHARGER EXPDET0x08 010010xx CHG_EN PTM CHG_OFF IPRECHG RESV'D RESV'DCONTROL1 _EN CHARGER0x09 0010x001 CHG_SET RESV'D IMIN_SETCONTROL2 (6) (Bolded locationsareRead-OnlyBits.) Resv'd = Reserved Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LP8727

SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com DETAILED REGISTER DESCRIPTIONS (1) REGISTERADDR BIT NAME BIT POR DEFAULT DESCRIPTIONNAME CHIP_REV [3:0] xxxx Chiprevision. 0x00 DEVICE ID VENDOR ID [7:4] 0011 Texas InstrumentsvendorID. Enablechargepump foranalogswitchoperation. When CP_EN = 0,inputsignalstotheanalogswitches shouldnotgo belowGND.CP_EN 0 1 0:Disable 1:Enable EnableID detectionLDO and internalADC. ADC_EN 1 0 0:Disable 1:Enable EnableID detectionLDO and SEND/END & MR comparators. SEMREN 2 0 0:Disable 1:Enable ID detectionLDO voltagesetting. VLDO 3 0 0:2.3V 0x01 CONTROL1 1:2.6V ConnectID detectionLDO toID pinthroughan internal 200 kΩ resistor. ID_200 4 0 0:Disable 1:Enable ConnectID detectionLDO toID pinthroughan internal 620Ω resistor. ID_620 5 0 0:Disable 1:Enable ConnectID detectionLDO toRES outputfor microphonebiasing.A 2.2kΩ externalresistoris requiredbetween RES and ID pins.ID_2P2 6 0 0:Disable 1:Enable RESERVED 7 x Not used. (1) Bolded entriesareread-only.

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www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 REGISTERADDR BIT NAME BIT POR DEFAULT DESCRIPTIONNAME DisableUSB chargerdetection. USB_DET_DIS 0 1 0:Enable 1:Disable Enablechargertypedetection.CHG_TYP willbe automaticallysetto0 attheend ofdetectionsequence. CHG_TYP 1 0 0:Disable 1:Enable RESERVED [3:2] xx Not used. Enableinternal100Ω pull-downresistorson AUD1 and AUD2. CP_AUD 4 0 0:Disable 0x02 CONTROL2 1:Enable Enablemicrophonelow-powermode. MIC_LP 5 0 0:Disable 1:Enable Enableinterruptoutput.When disabled,INT\\outputwill be masked and pendinginterruptswillnotbe cleared. INT_EN 6 0 0:Disable 1:Enable Interruptpolaritysetting. INTPOL 7 0 0:Activelow 1:Activehigh SettheswitchconnectiontoD- pin. 000:D- pinisconnectedtoDN pin. 001:D- pinisconnectedtoU1 pin. DM1 [2:0] 000 010:D- pinisconnectedtoAUD1 pin. 011:D- pinisconnectedtoC1COMP. 100:D- pinisconnectedtoDN pinregardlessofVBUS 101 to111:Hi-Z SettheswitchconnectiontoD+ pin. 000:D+ pinisconnectedtoDP pin. 0x03 SW CONTROL 001:D+ pinisconnectedtoU2 pin. DP2 [5:3] 000 010:D+ pinisconnectedtoAUD2 pin. 011:Hi-Z 100:D+ pinisconnectedtoDP pinregardlessofVBUS 101 to111:Hi-Z ConnectMIC pintoID pin. MIC_ON 6 0 0:Disable 1:Enable RESERVED 7 x Not used. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LP8727

SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com REGISTERADDR BIT NAME BIT POR DEFAULT DESCRIPTIONNAME ADC outputwith200 kΩ /2.2kΩ /620Ω ofpullup resistor(Activatedonlywhen ADC_EN = '1').Change of IDNO [3:0] 0000 IDNO statewilltriggerassertionofINT\\output. (RefertoTable1) VBUS comparatoroutput.Change ofVBUS statewill triggerassertionofINT output. VBUS 4 0 0:VVBUS < VVBUSDET 1:VVBUS > VVBUSDET SE comparatoroutput(Activatedonlywhen SEMREN = '1).Change ofSEND/END statewilltriggerassertionof INT\\output.SEND/END 5 0 0x04 INT_STAT1 0:VMIC > VSEND/END 1:VMIC < VSEND/END MR comparatoroutput(Activatedonlywhen SEMREN = '1').Change ofMR_COMP statewilltriggerassertionof INT\\output.MR_COMP 6 0 0:VMIC < VMR_COMP 1:VMIC > VMR_COMP Chargerdetectioniscompleted.Change ofCHG_DET statewilltriggerassertionofINT\\output. CHG_DET 7 0 0:VBUS isnotpresentorno chargerisdetected. 1:Chargerisdetected. RESERVED [2:0] 000 Not used. 0:VVBUS > UVLO USB UVLO 3 0 1:VVBUS < UVLO USB 0:VVBUS < VOV OVLO 4 0 1:VVBUS > VOV 0x05 INT_STAT2 0:TMP_STAT stateisnotchanged. TMP 5 0 1:TMP_STAT stateischanged. 0:Thermalshutdownisnottriggered. TSHD 6 0 1:Thermalshutdownistriggered. 0:CHG_STAT stateisnotchanged. CHG 7 0 1:CHG_STAT stateischanged. C1COMP output. C1COMP 0 0 0:VD-< VD-DET 1:VD-> VD-DET RESERVED [3:1] 000 Not used. Chargerstatus. 00:Pre-charge 0x06 STATUS1 CHG_STAT [5:4] 00 01:CC 10:CV 11:EOC 0:High-currentUSB Host/Hubisnotdetected. CHPORT 6 0 1:High-currentUSB Host/Hubisdetected. 0:Dedicatedchargerisnotdetected. DCPORT 7 0 1:Dedicatedchargerisdetected.

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www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 REGISTERADDR BIT NAME BIT POR DEFAULT DESCRIPTIONNAME RESERVED [4:0] 00000 Not used. Dietemperature. 000:75°C 001:95°C 010:115°C 0x07 STATUS2 TMP_STAT [7:5] 000 011:135°C 100:Reserved 101:Reserved 110:Reserved 111:Reserved RESERVED [1:0] xx Not used. Pre-chargecurrentsetting. 00:40 mA IPRECHG [3:2] 10 01:60 mA 10:80 mA 11:100 mA Chargerblockdisable. CHG_OFF 4 0 0:Enable 1:DisableCHARGER0x08 CONTROL1 EnablePTM (ProductionTestMode). PTM 5 0 0:Disable 1:Enable EnableEXPDET LDO. EXPDET_EN 6 1 0:Disable 1:Enable Chargerstop/startcontrol. CHG_EN 7 0 0:Stopcharging(ForceEOC). 1:Startcharging(Restart). EOC levelsetting. 000:5% 001:10% 010:16% IMIN_SET [2:0] 001 011:20% 100:25% 101:33% 110:50% RESERVED 3 x Not used. Chargingcurrentsetting.CHARGER0x09 CONTROL2 0000:90 mA 0001:100 mA 0010:400 mA 0011:450 mA CHG_SET [7:4] 0010 0100:500 mA 0101:600 mA 0110:700 mA 0111:800 mA 1000:900 mA 1001:1000 mA Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LP8727

/END MIC ZIN = 2.2k: R SPK L SPK LP8727 SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com OperationDescription MULTIPLEXING SWITCHES The LP8727 supportsUSB High-speed,UART and stereoaudio & microphone by providingautomatic multiplexingswitchesbetween Micro/MiniUSB connectorand USB, UART and Audio pathsincellularphone applications.The LP8727 detectstheexternaldeviceswhichcan be connectedtoMicro/MiniUSB connectorand informsthe processorthe detectionresultby generatingan interrupt.But,the LP8727 does not automatically change thestateofswitchmux when theexternaldeviceisdetected.The processorisresponsibletochange the stateofswitchmux viaI2C. Figure2. StereoAudio & MIC Connection DEFAULT SWITCH STATUS The LP8727 can configuredefaultswitchconnectionatstartuptoeitherUSB or UART by theDSS input.The DSS inputhas a 300 kΩ ofinternalpulldownresistor.When DSS islogiclow (connectedtoGND orleftfloating), thedefaultswitchconnectionissettoUSB. For UART startup,theDSS shouldbe pulledhightoVBAT through an external300 kΩ pull-upresistor.The statusofDSS inputismonitoredfromthestartupofdeviceand willbe latchedatthefirstrisingedge ofSCL input.The statusofDSS inputismonitoredand latchedatthe1strising edge ofsCL input. HIGH-IMPEDANCE MODE IftheLP8727 ispowered from VBAT (VBUS isnotpresent),thedefaultswitchconnectionsforD+, D- and ID shouldbe Hi-ZregardlessofDSS statusuntilUSB & ID detectionisdone.The high-impedancemode should alsobe controlledviaI2C. LOW-POWER MODE The LP8727 isdesignedtosupportlow-powermodes by CP_EN, ADC_EN and SEMREN bitson CONTROL1 register.The ID detectionLDO iscontrolledby eitherADC_EN orSEMREN bits.

CP_EN: When CP_EN bitissetto‘1’,thechargepump isenabledand thisallowstheaudiosignalinputs (AUD1 and AUD2) tobe driventonegativevoltagerail.
ADC_EN: When ADC_EN bitis set to ‘1’, ID detectionLDO and the internalADC are enabled.When ADC_EN is‘0’,IDNO bits(ADC output)willbe 4’h0000 and INT\\willnotbe asserted.Any pendinginterrupts due toa change intheADC outputwillnotbe clearedand must be clearedmanuallyby readingINT_STATx registers.
SEMREN: When SEMREN bitissetto‘1’,ID detectionLDO and theinternalcomparatorsforSEND/END and microphoneremovaldetectionsareenabled.When SEMREN is‘0’,theSEND/END and MR_COMP registers willbe setto‘0’and INT\\willnotbe asserted.Any pendinginterruptsdue toa change intheSEND/END or MR_COMP comparatorswillnotbe clearedand must be clearedmanuallyby readingINT_STATx registers.

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/END MIC 200 k: 2.2 k: PULSE GENERATOR LDO (2.3V/2/6V) 800 k:100 k: 100 k: MR_COMP SEND/END LP8727 www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 SEND/END BUTTON AND MICROPHONE REMOVAL DETECTION The LP8727 supportsSEND/END buttonand microphoneremovaldetectionfeaturesby monitoringvoltageon ID pin.When themicrophoneisconnectedtoID pin,itisbiasedby RES outputthroughan external2.2kΩ resistor. In the eventof removalof the microphone,the voltageon ID pinwillgo as highas the biasvoltagewhich is typically2.3V,and thiseventwillbe detectedby a comparator.The thresholdformicrophoneremovaldetection willbe setto90% ofthebiasvoltage. Headset accessorieshave a push buttonswitch(SEND/END) between the ID pin and GND. In case that SEND/END buttonispressed,thevoltageon ID pinwilldropdown toGND potential,and an internalcomparator isused to detectthisevent.The typicalthresholdof SEND/END buttondetectionisset to 10% of the bias voltage. Bothcaseswillgenerateinterruptstothehostprocessor. MICROPHONE LOW-POWER MODE When themicrophoneisconnected,itispowered fromRES outputthroughan external2.2kΩ (typ.)resistor.In case thatthemicrophoneisconnectedbutnotactive,theLP8727 allowsreducingthepower dissipationatthe microphone,whileitisstillsupportingSEND/END buttonand microphoneremovaldetection. Duringthemicrophonelow-powermode, theinternal200 kΩ resistorwillbe turnedon forimmediatemicrophone removaldetection,and RES outputwillcyclingON and OFF witha shortperiodoftimeforSEND/END detection. The microphonelow-powermode isenabledby MIC_LP bit,and interruptswillbe generatedby SEND/END and MR_COMP events. Figure3. MIC Low-Power Operation EXPDET LDO The EXPDET isovervoltageprotectedLDO outputforlow-voltageUSB transceiveron theprocessor,oritcan be used as a startuptriggersignalforthePMU. The EXPDET LDO isdirectlypowered fromVBUS and can withstandup to28V. The typicaloutputvoltageisset to4.85V and itisdesignedtosupplyup to50 mA. For stableoperation,a 1μF ceramiccapacitorisrequiredat theoutput. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LP8727

SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com INTERRUPT STATUS The LP8727 has 2 interruptstatusregisters,INT_STAT1 and INT_STAT2. These interruptconditionsare generatedfrom VBUS comparator,D+/D− & ID detection,changes of SEND/END & MR_COMP statesand chargerevents.When any oftheseinterruptconditionsoccur,thentheopen drainoutput(INT\\)willbe brought low.Thissignalsto the BB processorthatan interrupthas occurred.The BB processorwillthen read alltwo INT_STAT1 and INT_STAT2 registerssequentiallythroughtheserialinterfacetodeterminewhichbitcaused the interrupt.Once thestatusregisterindicatestheactualinterruptconditionstartstobe read,theINT\\outputwillbe broughthighimmediately.However,INT_STAT1 and INT_STAT2 registerswillnotbe clearedafterbeingreadby theBB processorand willalwaysrepresentthecurrentstatus. INT\\OUTPUT A serialinterfacereadofeach oftheinterruptstatusregistersimmediatelypullsup INT\\output.Ifan interruptis capturedduringa readsequence,theINT\\willnotgo lowuntilatleast24 serialclocks(SCL)have occurred.Any pendinginterruptswillbe clearedonce theLP8727 goes intoSHUTDOWN mode. DEVICE STATUS The LP8727 has 2 devicestatusregisters,STATUS1 and STATUS2. These registerscan be readviatheserial interfaceinmuch thesame way as theinterruptstatusregisters. These registerswillnotbe clearedon a readand willalwaysrepresentthecurrentstate. Device Identification The LP8727 can recognizevariousaccessoriesattachedtoMicro/MiniUSB connectorby detectingVBUS, D+, D − and ID pins.The detectioncomparatorshave a 60 ms ofdebounce timer.The deviceidentificationflowis shown inFigure4.

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ADC = 0000? START REFER TO DEVICE ID INDEX SWITCH to 2.2k: PULL-UP ADC = 0000? EAR JACK DETECTED ADC = 0000? SWITCH to 620: PULL-UP YES YES YES NO NO USB OTG DETECTED RETURN ADC = 1011? NO USB DETECTION DCPORT = 1? CHPORT = 1? DEDICATED CHARGER DETECTED USB HOST/HUB CHARGER DETECTED YES YES NO NO YES ID DETECTION (200k: PULL-UP) NO ADC = 0010? PRODUCTION TEST MODE (USB) NO ADC = 0100? PRODUCTION TEST MODE (UART) YES YES NO LP8727 www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 Figure4. Device IdentificationDiagram ID DETECTION When the externaldeviceisconnectedto Micro/MiniUSB connector,the LP8727 reads the voltageof ID pin usingan ADC whiletheID pinispulledup totheoutputofID DETECTION LDO (typ.2.3V)throughtheinternal 200 kΩ resistor.IfADC valuecode is4’h0000,theLP8727 willchange thepullupresistorfrom200 kΩ to2.2kΩ and eventuallyto620Ω step-by-stepfordetectingmicrophoneand USB OTG. Incase thatthefirstADC reading gives4’h1011, then the LP8727 willstartUSB detectionaccordingto USB BatteryCharging Specification Revision1.1. Table1. Device IndentificationIndex ID RESISTORADC VALUE ADC VOLTAGE D+ CONDITION D −CONDITION VBUS [V] FUNCTION[kΩ] DETECTION VALUES with200 kΩ PULL-UP RESISTOR 1011 100% OPEN 15 kΩ toGND 15 kΩ toGND 5 USB Cable 1011 100% OPEN ShortedtoD − ShortedtoD+ 5.6 TA Charger 1010 81.90% 910 Reserved Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LP8727

SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com Table1. Device IndentificationIndex(continued) ID RESISTORADC VALUE ADC VOLTAGE D+ CONDITION D −CONDITION VBUS [V] FUNCTION[kΩ] 1001 75.60% 620 Reserved 1000 68.20% 430 Reserved 0111 62.20% 330 Reserved 0110 54.50% 240 Reserved TA forNorth0101 47.40% 180 5 America 0100 39.40% 130 TX RX 5 UART (Factory) 0011 33.30% 100 Reserved 0010 21.90% 56 D+ D- 5 USB (Factory) 0001 12.50% 28.7 VZW 0000 0% MIC Speaker Speaker Microphone 0000 0% GND D+ D- USB OTG DETECTION VALUES with2.2kΩ PULL-UP RESISTOR 1011 to1000 100% to68.2% Reserved 0111 to0100 62.2% to39.4% TypicalMicrophone 001 to0001 33.3% to12.5% Reserved 0000 0% GND D+ D- USB OTG DETECTION VALUES with620Ω PULL-UP RESISTOR 1011 to0001 100% to12.5% Reserved 0000 0% GND D+ D − USB OTG USB DETECTION The LP8727 can detectdedicatedcharger,standarddownstream portand chargingdownstream portbased on USB BatteryChargingSpecificationRevision1.1.In orderto avoidfalsedetectionbeforedata (D+ and D −) connection,theLP8727 supports‘Data ContactDetect’feature.

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20 10050 200 500 1k 2k 5k 10k 20k (Hz) 0.1 0.01 0.001 0.0001 (%) 10 100 1k -100 -80 -60 -40 -20 dB MHz On Loss Off Isolation Crosstalk 10 100 1k -100 -80 -60 -40 -20 dB MHz On Loss Off Isolation Crosstalk 10 100 1k -100 -80 -60 -40 -20 dB MHz On Loss Off Isolation Crosstalk LP8727 www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 OperatingCharacteristics USB Eye Diagram (480MHz) UART Eye Diagram (480MHz) Figure5. Figure6. USB Frequency Response (10MHz -1GHz) UART Frequency Response (10MHz -1GHz) Figure7. Figure8. Audio Frequency Response (10MHz -1GHz) AUD1 THD+N (RL = 30Ω) Figure9. Figure10. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LP8727

20 10050 200 500 1k 2k 5k 10k 20k (Hz) 0.1 0.01 0.001 0.0001 (%) LP8727 SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com OperatingCharacteristics(continued) AUD2 THD+N (RL = 30Ω) Figure11.

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www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 SINGLE INPUT LINEAR CHARGER The LP8727 has a built-inLi-Ion/Li-Polybatterymanagement system.Itsmain featuresare:

Single-inputlinearcharger
Wide arrayofbatterychargingcurrentoptions
Flexiblechargingcyclecontrol
Thermalregulation
SafetytimerinPre-chargemode BATTERY CHARGER FUNCTION A chargemanagement system allowingsafechargeand maintenanceofa Li-Ionbatteryisimplementedon the LP8727. Followingthe correctdetectionof a voltageat the chargerinput,the chargerenterspre-chargemode. In this mode thebatteryischargedwitha smallconstantcurrent.Pre-chargesettingsareavailableinregister0x08,and thesevaluesareremembered as longas theLP8727 ison.IPRECHG bitsselectthebatterycurrentinpre-charge mode. Ifbatteryreaches the levelset by VFULLRATE , then the chargerwillmove on to fullchargingmode. TPRECHARGE setsthemaximum pre-chargetime,afterwhichthebatterywillbe isolated,protectingitfromfurther charging. Infullchargingmode full-rateconstantcurrentisappliedtothebattery,toraisethevoltagetothetermination level.The chargingcurrentis programmable via CHG_SET bits.When terminationvoltageis reached,the chargerisinconstantvoltagemode, and a constantvoltageismaintained.Afterreachingthe end-of-charge condition,thechargemanagement isolatesthebatteryand entersthemaintenancemode. Maintenancemode enablesthebatteryvoltagetobe maintainedatthecorrectlevel.Ifrestartconditionshave been met,thenthechargecycleisre-initiatedtore-establishtheterminationvoltagelevel. END-OF-CHARGE AND RESTART When EOC conditionis met, the LP8727 willgeneratean interruptto the processorand the processoris responsibletocontrolthechargeroperation(top-offormaintenancemode) viaI2C. Once thechargergoes intomaintenancemode (stopcharging),theprocessorisalsoresponsibleformonitoring thebatteryvoltageand restartingthechargerwhen thebatteryvoltagedropstorestartvoltage. PRODUCTION TEST MODE (PTM) When PTM bitisset,thenthechargerentersspecialhigh-loadmode. Inthismode thechargershouldbe ableto supplyup to2.3A. OVER-VOLTAGE PROTECTION A built-inover-voltageprotection(OVP) ensuresthatthe chargercan withstandhighvoltages(up to 28V) on VBUS input.When VBUS voltageexceeds theOVP threshold(typ.6.9V),thechargeroperationisdisabledin ordertoprotectthechargerfrombreakdown.When VBUS voltagedropsbelow theOVP threshold,thecharger automaticallyresumes itschargingfunction. THERMAL REGULATION When the die temperatureof the chargerreaches the thermalregulationthreshold(typ.115°C), the thermal regulationloopdynamicallyreducesthechargingcurrenttopreventthechargerfrom beingoverheated.As the die temperaturedrops below the thermalregulationthreshold,the chargingcurrentwillbe automatically increasedback totheprogrammed chargingcurrentsetting. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LP8727

[CC MODE] (Max. IBATT = IPRECHG ) Charger Input In-Range (VIN_OV > VBUS > VIN_LV) AND Wait 40 ms for Charger Services MAINTENANCE (IBATT = 0) Charger Input Out-of-Range (VBUS > VIN_OV ) OR (VBUS < VIN_LV) CHARGER OFF (IBATT = 0) Restart Condition FULL-RATE CHARGE [CV MODE] (VBATT = VTERM ) VBATT > VFULLRATE Pre-charge Timeout VBATT < VFULLRATE EOC Condition OR Fullrate Charge Timeout BAD BATTERY (IBATT = 0) Charger Settings: - IPRECHG : 80 mA - VFULLRATE : 2.6V - VTERM : 4.2V - ICHG : 400 mA - IEOC : 10% of ICHG Safety Timer: - Pre-charge: 45 min FULL-RATE CHARGE [CC MODE] (Max. IBATT = ICHG ) VBATT = VTERM VTERM IPRECHG VFULLRATE BATTERY VOLTAGE Pre-Charge to Full-Rate Charge Transition Transition to Constant Voltage-mode Charging Current End-of-Charge Full-Rate Current Battery Voltage Maintenance Mode CHARGING CURRENT TIME Restart VRESTART IEOC Constant Current Mode Pre-Charge Mode Constant Voltage Mode LP8727 SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com Figure12. Li-IonCharging Profile Figure13. Charger OperationDiagram UVLO Operation UVLO measures system voltageson VBUS and VBAT inputsand compares ittoselectedvoltages.The function uses 2 comparators.These comparatorsare combined intoUVLO_N state,which can affectstartup,cause shutdownorgenerateinterrupt.UVLO_N statecan change on followingconditions:

IfsystemvoltageislowerthanUVLO and OPVM, thenUVLO_N stateissetto'0';and

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IfsystemvoltageishigherthanUVLO and OPVM, thenUVLO_N stateissetto'1'. Using differentvaluesforUVLO and OPVM providesa window forvoltagedrops under high-loadworking conditions. UVLO_N state'0'indicatesthatthevoltageisbelow normalworkingrange,so thesystem isnotallowedtostart up.Thisstatecan alsocause thesystemtoshutdown. UVLO_N state'1'indicatesthatthevoltageisinnormalworkingrange,so thesystem isallowedtostartup and operate. Statetransition'1'→ '0'causesan UVLO interrupt,whichcan be senttoINT\\output. Support Functions REFERENCE The LP8727 has internalreferenceblockcreatingallnecessaryreferencesand biasingforallblocks. OSCILLATOR Thereisinternaloscillatorgivingclocktothelogiccontrol. VVBAT = 3.7V PARAMETER TYP MIN MAX UNIT OscillatorFrequency 31 29 33 kHz THERMAL SHUTDOWN The thermalshutdown (TSHD) functionmonitorsthe chiptemperatureto protectthe chipfrom temperature damage caused by excessivepower dissipation.When the chiptemperatureexceeds 160°C, “1” iswrittento TSHD biton INT_STAT2 registerand INT\\ispulledtolow and thentheLP8727 willinitiatesSHUTDOWN. The STARTUP operationafterTSHD triggercan be initiatedonlyafterthe chiphas cooleddown to the +115°C threshold. PARAMETER TYP UNIT TSDH (1) 160 TSDH Hysteresis(1) 45 (1) specifiedby design. CHIP TEMPERATURE MONITOR The LP8727 supportsthe chip temperaturemonitoringfeature.When the chip temperaturereaches each temperaturethreshold,TMP biton INT_STAT2 willbe set to “1”, and itwillpullINT\\ outputlow.The chip temperaturecan be obtainedby readingTMP_STAT bitson STATUS2 register. TMP_STAT 000 001 010 011 TEMPERATURE 75°C 95°C 115°C 125°C I2C-CompatibleSerialBus Interface INTERFACE BUS OVERVIEW The I2C-compatiblesynchronousserialinterfaceprovidesaccesstotheprogrammablefunctionsand registerson thedevice. Thisprotocoluses a two-wireinterfaceforbi-directionalcommunicationsbetween theICs connectedtothebus. The two interfacelinesare theSerialData Line(SDA),and theSerialClockLine(SCL).These linesshouldbe connectedtoa positivesupply,viaa pull-upresistorof1.5kΩ and remainHIGH even when thebus isidle. Every deviceon the bus isassigneda uniqueaddressand actsas eithera Master or a Slave dependingon whetheritgeneratesorreceivestheSCL. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LP8727

START CONDITION STOP CONDITION Data Line Stable: Data Valid Change of Data Allowed SDA SCL LP8727 SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com DATA TRANSACTIONS One data bitis transferredduringeach clockpulse.Data is sampled duringthe high stateof the SCL. Consequently,throughouttheclock’s highperiod,thedatashouldremainstable.Any changes on theSDA line duringthe highstateof the SCL and inthe middleof a transaction,abortsthe currenttransaction.New data should be sent during the low SCL state.This protocolpermitsa singledata lineto transferboth command/controlinformationand datausingthesynchronousserialclock. Figure14. BitTransfer Each datatransactioniscomposed ofa StartCondition,a number ofbytetransfers(setby thesoftware)and a Stop Conditionto terminatethe transaction.Every byte writtento the SDA bus must be 8 bitslong and is transferredwiththemost significantbitfirst.Aftereach byte,an Acknowledge signalmust follow.The following sectionsprovidefurtherdetailsofthisprocess. START AND STOP The Master deviceon the bus always generatesthe Start-and-StopConditions(controlcodes).Aftera Start Conditionisgenerated,the bus isconsideredbusy,and itretainsthisstatusuntila certaintimeaftera Stop Conditionisgenerated.A high-to-lowtransitionofthedataline(SDA) whiletheclock(SCL) ishighindicatesa StartCondition.A low-to-hightransitionoftheSDA linewhiletheSCL ishighindicatesa StopCondition. Figure15. Start-and-StopConditions InadditiontothefirstStartCondition,a repeatedStartConditioncan be generatedinthemiddleofa transaction. Thisallowsanotherdevicetobe accessed,ora registerreadcycle. ACKNOWLEDGE CYCLE The Acknowledge Cycleconsistsoftwo signals:theacknowledgeclockpulsethemastersends witheach byte transferred,and theacknowledgesignalsentby thereceivingdevice.The mastergeneratestheacknowledge clockpulseon theninthclockpulseofthebytetransfer.The transmitterreleasestheSDA line(permitsittogo high)toallowthereceivertosend theacknowledgesignal.The receivermust pulldown theSDA lineduringthe acknowledge clockpulseand ensure thatSDA remains low duringthe high periodof the clockpulse,thus signalingthecorrectreceptionofthelastdatabyteand itsreadinesstoreceivethenextbyte.

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S Data Output By Receiver 1 2 73 - 6 8 9 Acknowledgement Signal from Receiver Transmitter Stays Off the Bus During the Acknowledgement Clock LP8727 www.ti.com SNVS898A –OCTOBER 2012–REVISED MAY 2013 Figure16. Bus Acknowledge Cycle ”ACKNOWLEDGE AFTER EVERY BYTE ” RULE The mastergeneratesan acknowledgeclockpulseaftereach bytetransfer.The receiversends an acknowledge signalaftereverybytereceived. Thereisone exceptiontothe“acknowledgeaftereverybyte”rule. When the master is the receiver,itmust indicateto the transmitteran end of data by not-acknowledging (“negativeacknowledge”) the lastbyteclockedout of the slave.This“negativeacknowledge” stillincludesthe acknowledgeclockpulse(generatedby themaster),buttheSDA lineisnotpulleddown. ADDRESSING TRANSFER FORMATS Each deviceon thebus has a uniqueslaveaddress.The slaveaddressoftheLP8727 is7’h27 (0100111). Beforeany dataistransmitted,themastertransmitstheaddressoftheslavebeingaddressed.The slavedevice shouldsend an acknowledgesignalon theSDA line,once itrecognizesitsaddress. The slaveaddressisthefirstseven bitsaftera StartCondition.The directionofthedatatransfer(R/W) depends on the bitsentafterthe slaveaddress— the eighthbit.When the slaveaddressissent,each deviceinthe system compares thisslaveaddresswithitsown. Ifthereisa match,thedeviceconsidersitselfaddressedand sends an acknowledgesignal.Depending upon thestateoftheR/W bit(1:Read, 0:Write),thedeviceactsas a transmitterora receiver. CONTROL REGISTER WRITE CYCLE

Masterdevicegeneratesstartcondition.
Masterdevicesends slaveaddress(7bits)and thedatadirectionbit(r/w= '0').
Slavedevicesends acknowledgesignaliftheslaveaddressiscorrect.
Mastersends controlregisteraddress(8bits).
Slavesends acknowledgesignal.
Mastersends databytetobe writtentotheaddressedregister.
Slavesends acknowledgesignal.
Ifmaster willsend furtherdata bytes the controlregisteraddress willbe incrementedby one after acknowledgesignal.
Writecycleends when themastercreatesstopcondition. CONTROL REGISTER READ CYCLE
Masterdevicegeneratesa startcondition.
Masterdevicesends slaveaddress(7bits)and thedatadirectionbit(r/w= '0').
Slavedevicesends acknowledgesignaliftheslaveaddressiscorrect.
Mastersends controlregisteraddress(8bits).
Slavesends acknowledgesignal.
Masterdevicegeneratesrepeatedstartcondition.

(7 bits) '0' A A Control Register Add. (8 bits) From Slave to Master From Master to Slave Slave Address (7 bits) ASr '1' R/W Data transferred, byte + Ack/NAck Register Data (8 bits) P A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION NA - ACKNOWLEDGE (SDA High) Sr - REPEATED START CONDITION Direction of the transfer will change at this point NA R/W S Slave Address (7 bits) '0' A A A PControl Register Add. (8 bits) (8 bits) Register Data Data transferred, byte + Ack A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION From Slave to Master From Master to Slave LP8727 SNVS898A –OCTOBER 2012–REVISED MAY 2013 www.ti.com

Slavesends acknowledgesignaliftheslaveaddressiscorrect.
Slavesends databytefromaddressedregister.
Ifthemasterdevicesends acknowledgesignal,thecontrolregisteraddresswillbe incrementedby one.Slave devicesends databytefromaddressedregister.
Read cycleends when themasterdoes notgenerateacknowledgesignalafterdatabyteand generatesstop condition. AddressMode Data Read <StartCondition> <SlaveAddress><r/w= ‘0’>[Ack] <RegisterAddr.>[Ack] <Repeated StartCondition> <SlaveAddress><r/w= ‘1’>[Ack] [RegisterData]<Ack orNAck > … additionalreadsfromsubsequentregisteraddresspossible <StopCondition> Data Write <StartCondition> <SlaveAddress><r/w= ‘0’>[Ack] <RegisterAddr.>[Ack] <RegisterData>[Ack] … additionalwritestosubsequentregisteraddresspossible <StopCondition> < > Data frommaster []Data fromslave REGISTER READ AND WRITE DETAIL Figure17. RegisterWriteFormat Figure18. RegisterRead Format

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REVISION HISTORY

www.ti.com 3-May-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LP8727TME-B/NOPB ACTIVE DSBGA YFQ 25 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 27-B LP8727TME/NOPB ACTIVE DSBGA YFQ 25 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 8727 LP8727TMX-B/NOPB ACTIVE DSBGA YFQ 25 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 27-B LP8727TMX/NOPB ACTIVE DSBGA YFQ 25 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 8727 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 3-May-2013 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8727TME-B/NOPB DSBGA YFQ 25 250 210.0 185.0 35.0 LP8727TME/NOPB DSBGA YFQ 25 250 210.0 185.0 35.0 LP8727TMX-B/NOPB DSBGA YFQ 25 3000 210.0 185.0 35.0 LP8727TMX/NOPB DSBGA YFQ 25 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2013 Pack Materials-Page 2

www.ti.com TMD25XXX (Rev C) A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. NOTES: 4215084/A 12/12 D 0.600 ±0.075 E D: Max = E: Max = 2.04 mm, Min = 2.04 mm, Min = 1.98 mm 1.98 mm

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Summary

Micro/Mini USB Interface with Integrated 28V Charger

Description

Micro/Mini USB Interface with Integrated 28V Charger

Source title LP8727TMX/NOPB Datasheet(PDF) - Texas Instruments

Read LP8727TMX/NOPB online.

LP8727 TI1 | Alldatasheet

Document overview

Technical content

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10 Hz ≤ f≤ 100 kHzeN OutputNoiseVoltage 15 µVRMSC OUT = 1µF(2)

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REVISION HISTORY

LP8727TMX/NOPB specifications and overview.

More parts from the same family.