LP8725TLE-D/NOPB

LP8725 TI1 | Alldatasheet

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 LP8725PowerManagementUnitforApplicationor MultimediaProcessorsandSubsystems Check forSamples: LP8725 1FEATURES KEY SPECIFICATIONS 2• Two High-EfficiencyStep-Down DC-DC • 190 mV typ.Dropout Voltageon digitalLDOs Converters,IOUT = 600 mA, With a 4-MHz @ 300 mA SwitchingFrequency Using Small 1-µH • 2% typ.Output VoltageAccuracy on digital Inductors,With Options up to800 mA and analog LDOs

Three DigitalLDOs forup to300-mA Load • 10 μVrms Output Noise on analog LDOs CurrentEach • ±2% typ.Output VoltageBucks up to93%
Two Low-Noise Analog 300-mA LDOs efficiency
Two Low-InputLow-Output Regulators, • 30-bump DSBGA package (0.5mm pitch) IOUT = 300 mA
I2C-CompatibleInterfaceforControlofInternal DESCRIPTION Registers Thisdeviceisa multi-functionprogrammable Power Management Unit (PMU), optimizedforsub block• AdjustableStartupSequence Through Serial power solutions.This device integratestwo highlyInterfaceor Configuration efficient600-mA step-down DC-DC converters• Thermal Shutdown Protection configurableup to800-mA loadwithDynamic Voltage Scaling(DVS) viathe serialinterface,two low-noise APPLICATIONS analog LDOs, threedigitalLDOs forup to 300 mA loadcurrenteach,two Low-InputLow-Output(LILO)• MultimediaProcessors regulators,and an I2C-compatibleserialinterfaceto• PortableHandheld Products allowa hostcontrolleraccess to the internalcontrol registers.The device also featuresprogrammable power-on sequencing.LDO regulatorsprovidehigh PSRR and low noise ideallysuitedfor supplying power tobothanalogand digitalloads. The devicecan be configuredeitheras a Sub_PMU for modules (forexample, camera or multimedia modules)or as a stand-alonePMU thatpowers the processoritself. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

1 µF 1.2V to 3.3V @ 300 mA VIN3 VIN2 1 µF 1.2V to 3.3V @ 300 mA 1.2V to 3.3V @ 300 mA 1 µF LDO3 1 µF 1.2V to 3.3V @ 300 mA LDO4 LDO5 1 µF 1.2V to 3.3V @ 300 mA LDO 2 D LDO 1 D LDO3 D LDO4 A LDO5 A 2.2 PF2.2 PF LP8725 Voltage Reference Thermal Shutdown 2.2 PF LDO2 0.8V to 3.0V @ 800 mA Buck 1 4.7 µF 1 PH SW1 FB1 GNDB1 VINB1 4.7 µF SDA SCL EN Serial Interface and Control GND Buck 2 SW2 FB2 GNDB2 VINB2 4.7 µF 1 µF 0.8V to 3.3V @300 mA LILO1 LILO2 0.8V to 3.3V @300 \`mA LILO 1 D LILO 2 D UVLO VIN1

2.2 PF VINLILO2

2.2 PF DEFSEL VINB1 VINB2 VIN3 VIN2 VIN1 LDO3_EN B2_EN RESET_N DVS CONFIG VINLILO1 10k 1.5k 1.5k VSI 0.8V to 3.0V @ 800 mA 4.7 µF 1 PH 1 µF LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com TYPICAL APPLICATION (SUB-PMU)

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1 µF 1.2V to 3.3V @ 300 mA VIN3 VIN2 1µF 1.2V to 3.3V @ 300 mA 1.2V to 3.3V @ 300 mA 1 µF LDO3 1 µF 1.2V to 3.3V @ 300 mA LDO4 LDO5 1 µF 1.2V to 3.3V @ 300 mA LDO 2 D LDO 1 D LDO3 D LDO4 A LDO5 A 2.2 µF2.2 µF LP8725 Voltage Reference Thermal Shutdown 2.2 µF LDO2 0.8V to 3.0V @ 800 mA Buck 1 4.7 µF 1 µH SW1 FB1 GNDB1 VINB1 4.7 PF SDA SCL PWR_ON Serial Interface Control GND Buck 2 SW2 FB2 GNDB2 VINB2 4.7 µF 1 µF 0.8V to 3.3V @ 300 mA LILO1 LILO2 0.8V to 3.3V @ 300 mA LILO 1 D LILO 2 D UVLO VIN1 2.2 µF VINLILO2 2.2 µF DEFSEL VINB1 VINB2 VIN3 VIN2 VIN1 LDO3_EN PS_HOLD RESET_N DVS CONFIG VINLILO1 10k 1.5k 1.5k VSI VIN1 0.8V to 3.0V @ 800 mA 4.7 µF 1 µH 1 µF LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 TYPICAL APPLICATION (PMU) Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LP8725

PWR_ ON CON FIGVIN1 LDO2 VIN2 LDO4 DEF SEL RESET_N VIN LILO2 VINB1 LDO1 SCL B2_EN/ PS_HOLD DVS LDO3_ EN LDO3 GNDB1 VIN LILO1 SW1 FB1 VINB2 SDA FB2 VIN3 LILO2 GNDB2 GND LDO5 SW2 FEDCBA LILO2 B2_EN/ PS_HOLD LDO3_ ENVIN3 LDO5 LDO3 LDO1 DVS GND VIN LILO1 VINB2 LDO4 SDA EN/ PWR_ ON DEF SEL CON FIG VIN2 GNDB2 VIN LILO2 SW2 FB2 VINB1 SCL FB1 VIN1 LILO1 GNDB1 RESET_N LDO2 SW1 Bottom View Top View LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com CONNECTION DIAGRAMS

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 PIN DESCRIPTIONS Name Pin No. Description CONFIG=0: B2_EN istheenableforBUCK2 outputifthispinishighand ifBUCK2_EN registerbitissetto B2_EN/PS_HOLD B3 0.(B2_EN and theregisterbitarelogicalOR.) Internal500 KΩ pull-downresistorinthisconfigurationonly. CONFIG=1: PS_HOLD isa power supplyholdinputfroman externalprocessor. CONFIG E2 ConnecttoGND forSUB_PMU orconnecttoVIN1 forPMU. Controlinputthatsetsdefaultvoltagesand start-upsequence.Must be hardwiredtoVIN1 orGND for specificapplication.DEFSEL D2 When DEFSEL=VIN1 thensetup1 isused fordefaultvoltagesand startupsequences. When DEFSEL=GND thensetup2 isused fordefaultvoltagesand startupsequences. Dynamic VoltageScaling(operationalwhen REG 0x00<2> is'0'). DVS=1 thenBUCK voltagesetBUCK1_V1 isinuse.DVS C2 DVS=0 thenBUCK voltagesetBUCK1_V2 isinuse. Thispinmust be driventoitslogichighorlowwhenever theBUCK1 orBUCK2 outputsareenabled. CONFIG=0: EN=1 turnson outputsorstandbymode ifEN=0. EN/PWR_ON E3 CONFIG=1: PWR_ON=1 startspower up sequence after30 ms ofde-bouncetime.Internal500K pull- down resistor. FB1 E4 BUCK1 Feedback.Activepull-downwhen BUCK1 turnsoff. FB2 B4 BUCK2 Feedback.Activepull-downwhen BUCK2 turnsoff. GND D3 IC Ground GNDB1 F5 BUCK1 Ground. GNDB2 A5 BUCK2 Ground. LDO1 F1 LDO1 output. LDO2 E1 LDO2 output. LDO3 C1 LDO3 output. LDO3_EN B2 EnableforLDO3 outputifthispinishighand ifLDO3_EN registerbitissetto0.(LDO3_EN and the registerbitarelogicalOR.) Internal500 KΩ pull-downresistor. LDO4 A1 LDO4 output. LDO5 B1 LDO5 output LILO1 F3 LILO1 output. LILO2 A3 LILO2 output. CONFIG=0: Goes hightyp.30 ms afterEN=1 and goes lowwhen EN=0. RESET_N C3 CONFIG=1: Goes hightyp.60 ms afterPWR_ON=1 and goes low30 ms afterPS_HOLD=0. Externalpull-upresistorisneeded,typical10 kΩ. SCL D4 SerialInterfaceClockInput.Externalpull-upresistorisneeded,typical1.5kΩ. SDA C4 SerialInterfaceData Input/Output.Open Drainoutput,externalpull-upresistorisneeded,typical1.5kΩ. SW1 E5 BUCK1 Switchnode ofDC-DC converterBUCK1. SW2 B5 BUCK2 Switchnode ofDC-DC converterBUCK2. VIN1 F2 InputforLDO1. VINB1 D5 InputforBUCK1. VIN2 D1 InputforLDO2 and LDO3. VINB2 C5 InputforBUCK2. VIN3 A2 InputforLDO4 and LDO5. VINLILO1 F4 InputforLILO1. VINLILO2 A4 InputforLILO2. This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com DEVICE DESCRIPTION OperationModes POWER-ON-RESET: InSUB_PMU configuration-AfterVIN1 goes above UVLO highthreshold,thenallinternal registersofLP8725 areresettothedefaultvaluesfromtheDEFSEL setting,afterwhichLP8725 goes to STANDBY mode. InPMU configuration-When PWR_ON goes highwhileVIN1 isabove theUVLO high threshold,allinternalregistersofLP8725 areresettothedefaultvaluesfromtheDEFSEL setting.This processdurationmax istypically500 µs. STANDBY: InSTANDBY mode onlyserialinterfaceisworkingand allotherPMU functionsaredisabled– PMU isinlow-powercondition.InSTANDBY mode LP8725 can be (re)configuredviaSerialInterface.The LP8725 onlyentersSTANDBY mode automaticallyinSUB_PMU configuration. STARTUP: STARTUP sequence isdefinedby registerscontents.STARTUP sequence starts: 1)Ifrisingedge on EN-pininSUB_PMU configuration. 2)Aftercoolingdown fromthermalshutdowneventifEN=1 inSUB_PMU configuration. 3)IfPWR_ON isstillhighafter30 ms (typicalde-bouncetime)inPMU configuration.Itisnot recommended towritetoLP8725 registersduringSTARTUP. Ifdoingso thencurrentSTARTUP sequence may become undefined. InSUB_PMU configurationRESET_N isde-asserted30 ms (typical)afterEN=1. InPMU configuration RESET_N isde-asserteda further30 ms (typical)afterPWR_ON de-bouncetimehas ended. Itisnotrecommended towritetoLP8725 registersduringstartup.Ifdoingso thencurrentSTARTUP sequence may become undefined. IDLE: The LP8725 willenterintoIDLE mode (normaloperatingmode) afterend ofstartupsequence.InIDLE mode allLDOs and BUCK can be enabled/disabledviaSerialInterface.AlsoinIDLE mode theLP8725 can be (re)configuredviaSerialInterface. SHUTDOWN: SHUTDOWN sequence followsthereverseorderofthestartupsequence definedby registers contents: 1)Iffallingedge on EN-pininSUB_PMU configuration. 2)IfPS_HOLD and PWR_ON bothgo lowfortypically30 ms inPMU configuration.Deviceimmediately shutsdown ifthetemperatureexceedsthermalshutdownthresholdTSD +160°C. RESET_N isassertedwhen thedevicestartstoshutdown. Itisnotrecommended towritetoLP8725 registersduringSHUT DOWN. Ifdoingso thencurrent SHUTDOWN sequence may become undefined. InSUB_PMU configurationthedeviceshutsdown toSTANDBY mode. InPMU configurationthedeviceshutsdown completely(soregisterswillbe reseton nextPWR_ON high). SLEEP: The loadcurrentforeach oftheLDO outputsshouldbe no greaterthan5mA when thedeviceisputinto SLEEP mode. InSleepmode Ground currentisminimized.SLEEP mode iscontrolledby theserial interface,Register0x00 bit1. SLEEP Mode iscontrolledby theSerialInterface. Table1.ApplicationConfiguration(1)(2) DEFSEL = 1 DEFSEL = 0 GND SUB_PMU B2_EN EN 7h'78 7h'7A VIN1 PMU PS_HOLD PWR_ON 7h'79 7h'7B (1) The LP8725 and LP8725-A arebothconfiguredas eitherSUB_PMU orPMU by thewiringoftheCONFIG pinon theapplicationof power tothedevice. (2) These aredependenton whetherDEFSEL isconnectedtoVIN1 orGND when PWR_ON/EN=1.

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UVLO=1 (POR) EN=1 STARTUP SEQ EN=0 SHUTDOWN SEQ SLEEP_MODE=0 SLEEP_MODE=1 IDLE PS_HOLD=1 SLEEP OFF UVLO=1 AND PWR_ON=1 (POR AND STARTUP SEQ) PS_HOLD=0 (SHUTDOWN SEQ) SLEEP_MODE=0 SLEEP_MODE=1 LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Figure1.SUB-PMU Mode, CONFIG = 0 Figure2.PMU Mode, CONFIG = 1 AdditionalFunctions DVS: Dynamic VoltageScalingallowsusing2 setvoltagesforBUCKs. ThisiscontrolledviaSerialInterface. BUCK1 can alsobe controlledby theexternalDVS pin. FAULT DETECTION IfBUCK1/BUCK2 and LDO1 arenotmasked thenifone oftheoutputsispulleddown -e.g., shortcircuit,thenRESET_N isasserted(low).. Table2.DefaultStart-UpEnable Sequence (1) PartNo. DEFSEL Start-UpSequence Shut Down Sequence LP8725 VIN1 (setup1) BUCK1 then BUCK2 and LILO2 then LDO1, LDO2, LDO4 Inreverseorderofstart-up and LDO5 then LDO3 and LILO1 sequence. LP8725 GND (setup2) BUCK1 and LILO2 then BUCK2, LDO1, LDO2, LDO5 and Inreverseorderofstart-up LILO1 then LDO3 and LDO4. sequence. LP8725-A VIN1 (setup1) LDO1, LDO2, LDO5 and LILO1 then LDO4 and LILO2 Inreverseorderofstart-up sequence. LP8725-A GND (setup2) BUCK1 and BUCK2 then LDO2 and LDO3 then LDO1, Inreverseorderofstart-up LDO4 and LDO5 then LILO1 and LILO2 sequence. LP8725-B VIN1 orGND BUCK1 then BUCK2 then LDO1 then LILO2 Inreverseorderofstart-up sequence. LP8725-C VIN1 orGND BUCK1 then BUCK2 and LDO5 then LDO1 and LDO2 and Inreverseorderofstart-up LILO 1and LILO 2 then LDO3 and LDO4 sequence. LP8725-D VIN1 orGND BUCK1 then BUCK2, LDO3, LILO1 and LILO2 Inreverseorderofstart-up sequence. (1) These aredependenton whetherDEFSEL isconnectedtoVIN1 orGND when PWR_ON/EN=1. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LP8725

PWR_ON PS_HOLD DVS Control 30 ms (note 2) 30 ms BUCK (note 1) 30 msRESET_N LDO (note 1) PWR_ON PS_HOLD BUCK (note 1) RESET_N LDO (note 1) EN DVS Control BUCK (note 1) RESET_N LDO (note 1) BUCK (note 1) RESET_N LDO (note 1) EN 30 ms LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Power On and Power OffSequences Figure3. SimplifiedstartupSequence ifCONFIG=GND (SUB_PMU) Alltimingistypical. Note 1 See detailedon/offsequence diagramsforthedifferentDEFSEL options. Note 2 PS_HOLD needs tobe heldlowfor>30 ms beforeRESET_N isassertedlow.PMU shouldthenstart shutdownsequence oppositeofstartupsequence. Figure4. SimplifiedStartupSequence ifCONFIG=VIN1 (PMU)

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PWR_ON Buck 1 0 1 2 3 Buck 2 tON tS Timing Code Timing Code START UP sequence SHUT DOWN sequence is in reverse order of START UP sequence Buck 1 0123 Buck 2 LDO1 LDO1 LDO3 LDO3 START UP tS tS tS tS tS tS tS tS tS tS tS SHUT DOWNIDLE Note 4 LDO4 LDO4 LDO5 LDO5 LILO 2 LILO 2 LILO 1 LILO 1 4 5 6 6 5 4 LDO2 LDO2 PWR_ON PS_HOLDPS_HOLD tOFF LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Figure5. LP8725 Startupand Shutdown Sequence ifCONFIG=VIN1 Note 1,Note 2 Alltimingistypical. tON/OFF 30 ms typ.de-bouncetimes tS Programmable timesteps.(Typically64 µs/step.)Time stepaccuracyisdefinedby OSC frequencyaccuracy. Note 1 STARTUP and SHUTDOWN sequencesaredefinedby registers.Sequences givenherearevalidiftherethe registersarenotrewrittenviaSerialInterface. Note 2 The timingshowed heredefinetimepointswhen LDOs and BUCK areenabled/disabled.Enabling/disabling processdurationdepends on voltagesand loadingconditions.Buck startupdurationistypically170 µs.LDO startup durationistypically35 µs.Fordetailspleasesee LDOs and BUCK ElectricalSpecifications. Note 4 AtthistimepointregistersareresettoPOR defaultvalues. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LP8725

is in reverse order of START UP sequence Timing Code EN Buck 1 0123 Buck 2 LDO1 LDO1 LDO3 LDO3 STANDBY START UP tS tS tS tS tS tS tS tS tS tS tS SHUT DOWN STANDBYIDLE Note 4 LDO4 LDO4 LDO5 LDO5 LILO 2 LILO 2 LILO 1 LILO 1 4 5 6 6 5 4 LDO2 LDO2 LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Figure6. LP8725 Startupand Shutdown Sequence ifCONFIG=GND, DEFSEL=GND Note 1,Note 2 Alltimingistypical. tBON 75 µs -Referenceand biasturnON. ts Programmable timesteps.(Typically64 µs/step.)Time stepaccuracyisdefinedby OSC frequencyaccuracy. Note 1 STARTUP and SHUTDOWN sequencesaredefinedby registers.Sequences givenherearevalidiftherethe registersarenotrewrittenviaSerialInterface. Note 2 The timingshowed heredefinetimepointswhen LDOs and BUCK areenabled/disabled.Enabling/disabling processdurationdepends on voltagesand loadingconditions.Buck startupdurationistypically170 µs.LDO startup durationistypically35 µs.Fordetailspleasesee LDOs and BUCK ElectricalSpecifications. Note 4 AtthistimepointregistersareresettoPOR defaultvalues.

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START UP sequence SHUT DOWN sequence is in reverse order of START UP sequence EN Buck 1 0123 Buck 2 LDO1 LDO1 LDO3 LDO3 STANDBY START UP tS tS tS tS tS tS tS tS tS tS tS SHUT DOWN STANDBYIDLE Note 3 Note 4 LDO4 LDO4 LDO5 LDO5 LILO 2 LILO 2 LILO 1 LILO 1 4 5 6 6 5 4 LDO2 LDO2 Note 5 Note 5 LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Figure7. LP8725-A Startupand Shutdown Sequence ifCONFIG=GND, DEFSEL=VIN1 Note 1,Note 2 Alltimingistypical. tBON 75 µs -Referenceand biasturnON. tS Programmable timesteps.(Typically64 µs/step.)Time stepaccuracyisdefinedby OSC frequencyaccuracy. Note 1 STARTUP and SHUTDOWN sequencesaredefinedby registers.Sequences givenherearevalidiftherethe registersarenotrewrittenviaSerialInterface. Note 2 The timingshowed heredefinetimepointswhen LDOs and BUCK areenabled/disabled.Enabling/disabling processdurationdepends on voltagesand loadingconditions.Buck startupdurationistypically170 µs.LDO startup durationistypically35 µs.Fordetailspleasesee LDOs and BUCK ElectricalSpecifications. Note 3 BUCK1 isdisabled.IfitisenabledviaSerialInterfaceand thestartupsequence isnotchanged,thenitwillbe disabled,withno delay,fromfallingedge ofEN-pin. Note 4 AtthistimepointregistersareresettoPOR defaultvalues. Note 5 BUCK2 and LDO3 areenabledby B2_EN and LDO3_EN respectively(orviaserialinterface).Iftheseinputs arehighwhen EN goes highthentheseoutputsturnon afterts= 6. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LP8725

START UP sequence SHUT DOWN sequence is in reverse order of START UP sequence EN Buck 1 0123 Buck 2 LDO1 LDO1 LDO3 LDO3 STANDBY START UP tS tS tS tS tS tS tS tS tS tS tS SHUT DOWN STANDBYIDLE Note 4 LDO4 LDO4 LDO5 LDO5 LILO 2 LILO 2 LILO 1 LILO 1 4 5 6 6 5 4 LDO2 LDO2 LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Figure8. LP8725-A Startupand Shutdown Sequence ifCONFIG=GND, DEFSEL=GND Note 1,Note 2 Alltimingistypical. tBON 75 µs -Referenceand biasturnON. tS Programmable timesteps.(Typically64 µs/step.)Time stepaccuracyisdefinedby OSC frequencyaccuracy. Note 1 STARTUP and SHUTDOWN sequencesaredefinedby registers.Sequences givenherearevalidiftherethe registersarenotrewrittenviaSerialInterface. Note 2 The timingshowed heredefinetimepointswhen LDOs and BUCK areenabled/disabled.Enabling/disabling processdurationdepends on voltagesand loadingconditions.Buck startupdurationistypically170 µs.LDO startup durationistypically35 µs.Fordetailspleasesee LDOs and BUCK ElectricalSpecifications. Note 4 AtthistimepointregistersareresettoPOR defaultvalues.

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PWR_ON Buck 1 0 1 2 3 Buck 2 tON tS Timing Code Timing Code START UP sequence SHUT DOWN sequence is in reverse order of START UP sequence Buck 1 0123 Buck 2 LDO1 LDO1 LDO3 LDO3 START UP tS tS tS tS tS tS tS tS tS tS tS SHUT DOWNIDLE Note 4 LDO4 LDO4 LDO5 LDO5 LILO 2 LILO 2 LILO 1 LILO 1 4 5 6 6 5 4 LDO2 LDO2 PWR_ON PS_HOLDPS_HOLD tOFF Note 3 Note 3 Note 5 Note 3 Note 3 LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Figure9. LP8725-B Startupand Shutdown Sequence ifCONFIG=VIN1, DEFSEL=VIN1 orDEFSEL=GND Note 1,Note 2 Alltimingistypical. tON/OFF 30 ms typ.de-bouncetimes. tS Programmable timesteps.(Typically64 µs/step.)Time stepaccuracyisdefinedby OSC frequencyaccuracy. Note 1 STARTUP and SHUTDOWN sequencesaredefinedby registers.Sequences givenherearevalidiftherethe registersarenotrewrittenviaSerialInterface. Note 2 The timingshowed heredefinetimepointswhen LDOs and BUCK areenabled/disabled.Enabling/disabling processdurationdepends on voltagesand loadingconditions.Buck startupdurationistypically170 µs.LDO startup durationistypically35 µs.Fordetailspleasesee LDOs and BUCK ElectricalSpecifications. Note 3 LDO2, 4,5 and LILO1 aredisabled.IftheyareenabledviaSerialInterfaceand thestartupsequence isnot changed,thentheywillbe disabled,withno delay,fromfallingedge ofEN-pin. Note 4 AtthistimepointregistersareresettoPOR defaultvalues. Note 5 LDO3 isenabledby LDO3_EN (orviaserialinterface).Ifthisinputishighwhen PWR_ON goes highthenthis outputturnson afterts= 6. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LP8725

is in reverse order of START UP sequence Timing Code Buck 1 0123 Buck 2 LDO1 LDO1 LDO3 LDO3 START UP tS tS tS tS tS tS tS tS tS tS tS SHUT DOWNIDLE Note 4 LDO4 LDO4 LDO5 LDO5 LILO 2 LILO 2 LILO 1 LILO 1 4 5 6 6 5 4 LDO2 LDO2 EN Note 3 Note 3 Note 5 Note 3 Note 3 STANDBY STANDBY LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Figure10. LP8725-B Startupand Shutdown Sequence ifCONFIG=GND, DEFSEL=VIN1 orDEFSEL=GND Note 1,Note 2 Alltimingistypical. tBON 75 µs -Referenceand biasturnON. tS Programmable timesteps.(Typically64 µs/step.)Time stepaccuracyisdefinedby OSC frequencyaccuracy. Note 1 STARTUP and SHUT DOWN sequencesaredefinedby registers.Sequences givenherearevalidiftherethe registersarenotrewrittenviaSerialInterface. Note 2 The timingshowed heredefinetimepointswhen LDOs and BUCK areenabled/disabled.Enabling/disabling processdurationdepends on voltagesand loadingconditions.Buck startupdurationistypically170 µs.LDO startup durationistypically35 µs.Fordetailspleasesee LDOs and BUCK ElectricalSpecifications. Note 3 LDO2, 4,5 and LILO1 aredisabled.IftheyareenabledviaSerialInterfaceand thestartupsequence isnot changed,thentheywillbe disabled,withno delay,fromfallingedge ofEN-pin. Note 4 AtthistimepointregistersareresettoPOR defaultvalues. Note 5 LDO3 isenabledby LDO3_EN (orviaserialinterface).Ifthisinputishighwhen PWR_ON goes highthenthis outputturnson afterts= 6.

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PWR_ON Buck 1 0 1 2 3 Buck 2 tON tS Timing Code Timing Code START UP sequence SHUT DOWN sequence is in reverse order of START UP sequence Buck 1 0123 Buck 2 LDO1 LDO1 LDO3 LDO3 START UP tS tS tS tS tS tS tS tS tS tS tS SHUT DOWNIDLE Note 4 LDO4 LDO4 LDO5 LDO5 LILO 2 LILO 2 LILO 1 LILO 1 4 5 6 6 5 4 LDO2 LDO2 PWR_ON PS_HOLDPS_HOLD tOFF LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Figure11. LP8725-C Startupand Shutdown Sequence ifCONFIG=VIN1, DEFSEL=VIN1 orDEFSEL=GND Note 1,Note 2 Alltimingistypical. tON/OFF 30 ms typ.de-bouncetimes. tS Programmable timesteps.(Typically64 µs/step.)Time stepaccuracyisdefinedby OSC frequencyaccuracy. Note 1 STARTUP and SHUTDOWN sequencesaredefinedby registers.Sequences givenherearevalidiftherethe registersarenotrewrittenviaSerialInterface. Note 2 The timingshowed heredefinetimepointswhen LDOs and BUCK areenabled/disabled.Enabling/disabling processdurationdepends on voltagesand loadingconditions.Buck startupdurationistypically170 µs.LDO startup durationistypically35 µs.Fordetailspleasesee LDOs and BUCK ElectricalSpecifications. Note 4 AtthistimepointregistersareresettoPOR defaultvalues. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LP8725

PWR_ON Buck 1 0 1 2 3 Buck 2 tON tS Timing Code Timing Code START UP sequence SHUT DOWN sequence is in reverse order of START UP sequence Buck 1 0123 Buck 2 LDO1 LDO1 LDO3 LDO3 START UP tS tS tS tS tS tS tS tS tS tS tS SHUT DOWNIDLE Note 4 LDO4 LDO4 LDO5 LDO5 LILO 2 LILO 2 LILO 1 LILO 1 4 5 6 6 5 4 LDO2 LDO2 PWR_ON PS_HOLDPS_HOLD tOFF Note 3 Note 3 Note 3 Note 3 LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Figure12. LP8725-D Startupand Shutdown Sequence ifCONFIG=VIN1, DEFSEL=VIN1 orDEFSEL=GND Note 1,Note 2 Alltimingistypical. tON/OFF 30 ms typ.de-bouncetimes. tS Programmable timesteps.(Typically64 µs/step.)Time stepaccuracyisdefinedby OSC frequencyaccuracy. Note 1 STARTUP and SHUTDOWN sequencesaredefinedby registers.Sequences givenherearevalidiftherethe registersarenotrewrittenviaSerialInterface. Note 2 The timingshowed heredefinetimepointswhen LDOs and BUCK areenabled/disabled.Enabling/disabling processdurationdepends on voltagesand loadingconditions.Buck startupdurationistypically170 µs.LDO startup durationistypically35 µs.Fordetailspleasesee LDOs and BUCK ElectricalSpecifications. Note 3 LDO1, 2,4,5 aredisabled.IftheyareenabledviaSerialInterfaceand thestartupsequence isnotchanged, thentheywillbe disabled,withno delay,fromfallingedge ofEN-pin. Note 4 AtthistimepointregistersareresettoPOR defaultvalues. Note 5 LDO3 isenabledby LDO3_EN (orviaserialinterface).Ifthisinputishighwhen PWR_ON goes highthenthis outputturnson afterts= 6.

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Table3.DefaultOutput Voltages(1)(2) Output Max Current(mA) VoltageRange (V) DefaultoutputVoltage[V]and defaultON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND LDO1 300 1.2to3.3 2.8ON 2.6ON LDO2 300 1.2to3.3 1.8ON 2.8ON LDO3 300 1.2to3.3 3.3ON 2.8ON LDO4 300 1.2to3.3 3.3ON 2.8ON LDO5 300 1.2to3.3 2.8ON 2.8ON LILO1 300 0.8to3.3 1.2ON 3.3ON LILO2 300 0.8to3.3 1.2ON 1.2ON (1) These aredependenton whetherDEFSEL isconnectedtoVIN1 orGND when PWR_ON/EN=1. (2) BUCK1 voltagesaresetto*BUCK1_V1 and **BUCK1_V2 as selectedby DVS1_V and theDVS pin. BUCK2 voltagesaresetto*BUCK2_V1 and BUCK2_V2 as selectedby DVS2_V. Table4.LP8725-A AlternativePart's DefaultOutput Voltages(1)(2) Output Max Current(mA) VoltageRange (V) DefaultoutputVoltage[V]and defaultON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND LDO1 300 1.2to3.3 2.6ON 2.8ON LDO2 300 1.2to3.3 3.0ON 2.8ON LDO3 300 1.2to3.3 3.3OFF** 2.8ON LDO4 300 1.2to3.3 3.0ON 2.8ON LDO5 300 1.2to3.3 2.8ON 2.8ON LILO1 300 0.8to3.3 1.8ON 1.8ON LILO2 300 0.8to3.3 1.0ON 1.8ON (1) These aredependenton whetherDEFSEL isconnectedtoVIN1 orGND when PWR_ON/EN=1. (2) BUCK1 voltagesaresetto*BUCK1_V1 and **BUCK1_V2 as selectedby DVS1_V and theDVS pin. BUCK2 voltagesaresetto*BUCK2_V1 and BUCK2_V2 as selectedby DVS2_V. *OnlyifpinB2_EN=0 ifinSUB_PMU configuration Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Table5.LP8725-B AlternativePart's DefaultOutput Voltages(1)(2) Output Max Current(mA) VoltageRange (V) DefaultoutputVoltage[V]and defaultON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND LDO1 300 1.2to3.3 2.6ON 1.8ON LDO2 300 1.2to3.3 2.8OFF 2.8OFF LDO3 300 1.2to3.3 2.8OFF* 2.8OFF* LDO4 300 1.2to3.3 1.2OFF 1.2OFF LDO5 300 1.2to3.3 1.2OFF 1.2OFF LILO1 300 0.8to3.3 2.5OFF 2.5OFF LILO2 300 0.8to3.3 3.3ON 3.3ON (1) These aredependenton whetherDEFSEL isconnectedtoVIN1 orGND when PWR_ON/EN=1. (2) BUCK1 voltagesaresetto*BUCK1_V1 and **BUCK1_V2 as selectedby DVS1_V and theDVS pin. BUCK2 voltagesaresetto*BUCK2_V1 and BUCK2_V2 as selectedby DVS2_V. *OnlyifpinLDO3_EN=0 Table6.LP8725-C AlternativePart's DefaultOutput Voltages(1) Output Max Current(mA) VoltageRange (V) DefaultoutputVoltage[V]and defaultON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND BUCK1 800 0.8to3.0 1.2ON 1.2ON BUCK2 600 0.8to3.0 1.8ON 1.8ON LDO1 300 1.2to3.3 2.6ON 2.6ON LDO2 300 1.2to3.3 2.8ON 2.8ON LDO3 300 1.2to3.3 2.8ON 2.8ON LDO4 300 1.2to3.3 2.5ON 2.5ON LDO5 300 1.2to3.3 3.3ON 3.3ON LILO1 300 0.8to3.3 1.2ON 1.2ON LILO2 300 0.8to3.3 1.2ON 1.2ON (1) These aredependenton whetherDEFSEL isconnectedtoVIN1 orGND when PWR_ON/EN=1.

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Table7.LP8725-D AlternativePart's DefaultOutput Voltages(1)(2) Output Max Current(mA) VoltageRange (V) DefaultoutputVoltage[V]and defaultON/OFF (PWR_ON/EN=1) DEFSEL = VIN1 DEFSEL = GND LDO1 300 1.2to3.3 2.8OFF 2.8OFF LDO2 300 1.2to3.3 1.8OFF 1.8OFF LDO3 300 1.2to3.3 1.8ON 1.8ON LDO4 300 1.2to3.3 3.0OFF 3.0OFF LDO5 300 1.2to3.3 1.8OFF 1.2OFF LILO1 300 0.8to3.3 3.0ON 3.0ON LILO2 300 0.8to3.3 3.0ON 3.0ON (1) These aredependenton whetherDEFSEL isconnectedtoVIN1 orGND when PWR_ON/EN=1. (2) BUCK1 voltagesaresetto*BUCK1_V1 and **BUCK1_V2 as selectedby DVS1_V and theDVS pin. BUCK2 voltagesaresetto*BUCK2_V1 and **BUCK2_V2 as selectedby DVS2_V. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) VIN1 -0.3Vto+6V VIN2,VIN3,VINLILO1,VINLILO2,VINB1,VINB2 -0.3VtoVIN1+0.3V and <6.0V Logicand controlpins:VoltagetoGND -0.3VtoVIN1+0.3V and <6.0V ContinuousPower Dissipation(3) InternallyLimited JunctionTemperature(TJ-MAX ) 150°C StorageTemperatureRange -65to150°C ESD Rating(4) Human Body Model 2kV Machine Model 200V (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagesarewithrespecttothepotentialattheGND pin. (3) Internalthermalshutdowncircuitryprotectsthedevicefropermanentdamage. Thermalshutdownengages atTJ = 150°C (typ.)and disengagesatTJ = 130°C. (4) The human-body model is100 pF dischargedthrough1.5kΩ.The machine model isa 200 pF capacitordischargeddirectlyintoeach pin,MIL-STD-883 3015.7. OPERATING RATINGS (1)(2) VIN1 2.6to4.5V VIN2,VIN3,VINB1,VINB2 2.6VtoVIN1 VINLILO1,VINLILO2 1.8VtoVIN1 Allinput-onlypins 0V toVIN1 JunctionTemperature(TJ) -40to125°C AmbientTemperature(TA) (3) -40to85°C Maximum Power Dissipation(TA = 70°C) 1.3W (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagesarewithrespecttothepotentialattheGND pin. (3) Inapplicationswhere highpower dissipationand/orpoorpackage resistanceispresent,themaximum ambienttemperaturemay have to be de-rated.Maximum ambienttemperature(TA-MAX )isdependenton themaximum operatingjunctiontemperature(TJ-MAX ),The maximum power dissipationofthedeviceintheapplication(PD-MAX )and thejunctiontoambientthermalresistanceofthepackage (θJA) intheapplication,as givenby thefollowingequation:TA-MAX = TJ-MAX (θJA x PD-MAX ).Due tothepulsednatureoftestingthepart,the temp intheElectricalCharacteristictableisspecifiedas TA = TJ. THERMAL PROPERTIES Junction-to-AmbientThermalResistance(θJA)(1),θJA 4–LayerJEDEC Board(2) 41°C/W (1) Inapplicationswhere highpower dissipationand/orpoorpackage resistanceispresent,themaximum ambienttemperaturemay have to be de-rated.Maximum ambienttemperature(TA-MAX )isdependenton themaximum operatingjunctiontemperature(TJ-MAX ),The maximum power dissipationofthedeviceintheapplication(PD-MAX )and thejunctiontoambientthermalresistanceofthepackage (θJA) intheapplication,as givenby thefollowingequation:TA-MAX = TJ-MAX (θJA x PD-MAX ).Due tothepulsednatureoftestingthepart,the temp intheElectricalCharacteristictableisspecifiedas TA = TJ. (2) Junction-to-ambientthermalresistanceishighlyapplicationand boardlayoutdependent.Inapplicationswhere highpower dissipation exists,specialcaremust be giventothermaldissipationissuesinboarddesign.

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 CURRENT CONSUMPTION Unlessotherwisenoted,VIN1=VIN2=VIN3=VINB1=VINB2=VINLILO1=VINLILO2=3.6V;C LDOX =1µF;C BUCKOUT =C BUCKIN =4.7µF; C VIN1–3=C VINLILO1=C VINLILO2=2.2µF.Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Limitsappearingin boldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ= -40to+125°C. (1) Symbol Parameter Conditions Min Typ Max Unit IQ(STANDBY) StandbyCurrent AlloutputsdisabledEN = 0 3.3 8 IQ(SLEEP) CurrentinSLEEP Mode at Outputsdisabledviacontrolregisters 50 80 no load OnlyBuck1 and LDO1 enabled 95 Alloutputsenabled 205 280 µA IQ(IDLE) Currentatno load Outputsdisabledviacontrolregisters 145 210 OnlyBuck1 and LDO1 enabled 205 Alloutputsenabled 420 600 (1) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotverified,butdo representthemost likely norm. THERMAL SHUTDOWN The ThermalShutdown (TSD) functionmonitorsthechiptemperature(TJ)toprotectthechipfromtemperaturedamage caused,e.g.,by excessivepower dissipation.(1) Symbol Parameter Conditions Min Typ Max Unit TSD 160 °C TSD Hysteresis 20 °C (1) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotverified,butdo representthemost likely norm. UNDER-VOLTAGE LOCK OUT Thisdevicehas Under-VoltageLock Out (UVLO) thatchecksVIN1-pinvoltagebeforestartingPower On sequence.UVLO is alsocheckedduringPower On sequence.IftheVDD voltageislessthanUVLO thresholdthePMU willnotPower On. After thePMU successfullypassed Power On sequence UVLO isnotmonitored.(1) Symbol Parameter Conditions Min Typ Max Unit CONFIG = 0 2.3UVLO Threshold VVIN1 rising CONFIG = 1 2.825 3.0 3.185 VUVLO CONFIG = 0 400 Hysteresis mV CONFIG = 1 800 (1) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotverified,butdo representthemost likely norm. LOGIC AND CONTROL Unlessotherwisenoted,VIN1=VIN2=VIN3=VINB1 =VINB2=VINLILO1=VINLILO2=3.6V;C LODX =1µF;C BUCKOUT =C BUCKIN =4.7µF, C VIN1–3=C VINLILO1C VINLILO2=2.2µF.Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Limitsappearingin boldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ= -40to+125°C. (1) Symbol Parameter Conditions Min Typ Max Unit Logic and ControlInputs VIL InputLow Level EN, SCL, SDA, DVS, PS_HOLD, 0.4 VPWR_ON BUCK2_EN, LDO3_EN VIH InputHighLevel EN, SCL, SDA, DVS, PS_HOLD 1.2 VPWR_ON, BUCK2_EN, LDO3_EN IIL InputLow LevelCurrent EN, SCL, SDA, DVS, PS_HOLD PWR_ON, DVS, DEFSEL, CONFIG, 0 2 µABUCK2_EN, LDO3_EN VIL= 0V (1) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotverified,butdo representthemost likely norm. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com LOGIC AND CONTROL (continued) Unlessotherwisenoted,VIN1=VIN2=VIN3=VINB1 =VINB2=VINLILO1=VINLILO2=3.6V;C LODX =1µF;C BUCKOUT =C BUCKIN =4.7µF, C VIN1–3=C VINLILO1C VINLILO2=2.2µF.Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Limitsappearingin boldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ= -40to+125°C. (1) Symbol Parameter Conditions Min Typ Max Unit IIH InputHighLevelCurrent PS_HOLD, DEFSEL, CONFIG, DVS 0 2VIH = VIN1 R PD PullDown Resistance From EN, PWR_ON, B2_EN, and 500 kΩLDO3_EN Logic and ControlOutputs VOL OutputLow Level SDA, RESET_N 0.14 0.3 VIOUT = 2mA IOH OutputHighLevel SDA, RESET_N have Open drain outputs 0 2 µA VOH = VIN1 BUCK CONVERTERS Unlessotherwisenoted,VIN1=VIN2=VIN3=VINB1 =VINB2=VINLILO1=VINLILO2=3.6V;C LODX =1µF;C BUCKOUT =C BUCKIN =4.7µF, C VIN1–3=C VINLILO1C VINLILO2=2.2µF.Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Limitsappearingin boldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ= -40to+125°C. (1)(2) Symbol Parameter Conditions Min Typ Max Unit BUCK1 Feedback Voltage -2 +2 VFB VOUT = 1.8V % BUCK2 Feedback Voltage -3 +3 R DSON(P) Pin-PinresistanceforPFET IOUT = 200 mA 265 m Ω R DSON(N) Pin-PinresistanceforNFET IOUT = −200 mA 150 m Ω Open-loop,programmable: 460250 mA max IOUT typ 780450 mA max IOUT typILIM SwitchPeak CurrentLimit mA600 mA max IOUT typ 750 1050 1500800 mA max IOUT typ 1370 tSTUP StartupTime IOUT = 0mA to100 mA 170 µs fSW SwitchingFrequency 3.6 4.1 4.4 MHz (1) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotverified,butdo representthemost likely norm. (2) The parametersintheelectricalcharacteristictablearetestedunderopen loopconditionsatVIN = 3.6Vunlessotherwisespecified.For performanceovertheinputvoltagerangeand closedloopcondition,refertothedatasheetcurves. DIGITAL LDOs (1,2,3) Unlessotherwisenoted,VIN1=VIN2=VIN3=VINB1=VINB2=VINLILO1=VINLILO2=3.6V;C LODX =1µF;C BUCKOUT =C BUCKIN =4.7µF, C VIN1–3=C VINLILO1C VINLILO2=2.2µF.Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Limitsappearingin boldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ= -40to+125°C. (1) Symbol Parameter Conditions Min Typ Max Unit −1.5 +1.5LDO1 OutputVoltage Accuracy −2 +2 VOUT IOUT = 1mA, VOUT = 2.8V % −2 +2LDOs 2 & 3 OutputVoltage Accuracy −2.5 +2.5 VOUT + 0.5V≤ VIN2 ≤ 4.5VLineRegulation 2 mVIOUT = 1mA (2) ΔVOUT Load Regulation 1 < IOUT < 300 mA 2 (1) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotverified,butdo representthemost likely norm. (2) The minimum inputvoltageequalsVOUT (nom)+ 0.5Vor2.5V,whicheverisgreater.

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 DIGITAL LDOs (1,2,3)(continued) Unlessotherwisenoted,VIN1=VIN2=VIN3=VINB1=VINB2=VINLILO1=VINLILO2=3.6V;C LODX =1µF;C BUCKOUT =C BUCKIN =4.7µF, C VIN1–3=C VINLILO1C VINLILO2=2.2µF.Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Limitsappearingin boldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ= -40to+125°C. (1) Symbol Parameter Conditions Min Typ Max Unit VDO DropoutVoltage IOUT = 300 mA 190 270 mVNominalVOUT = 2.8V (3) IOUT OutputCurrent 0 300 mA ISLEEP Max OutputCurrentin 1 mA SleepMode ISC OutputCurrentLimit VOUT = 0V 650 mA eN OutputVoltageNoise 10 Hz ≤ f≤ 100 KHz 35 µVRMS IOUT = 300 mA PSRR Power SupplyRejection f≤ 10 KHz, IOUT = 20 mA 65 dB Ratio tSTUP StartupTime IOUT = 0 mA to300 mA inIdlemode. 20 µs VOS Start-upOvershoot IOUT = 300 mA (4) 30 mV C OUT ExternalOutput (4) 0.5 1 20 µFCapacitanceforStability (3) Dropoutvoltageisthevoltagedifferencebetween theinputand theoutputatwhichtheoutputvoltagedropsto100 mV belowits nominalvalue. (4) Thisspecificationisguaranteedby design. LOW-NOISE ANALOG LDOs (4,5) Unlessotherwisenoted,VIN1=VIN2=VIN3=VINB1=VINB2=VINLILO1=VINLILO2=3.6V;C LODX =1µF;C BUCKOUT =C BUCKIN =4.7µF, C VIN1–3=C VINLILO1C VINLILO2=2.2µF.Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Limitsappearingin boldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ= -40to+125°C. (1) Symbol Parameter Conditions Min Typ Max Unit −2 +2 VOUT OutputVoltageAccuracy IOUT = 1mA, VOUT = 2.8V % −2.5 +2.5 LineRegulation VOUT + 0.5V≤ VIN3 ≤ 4.5V 1IOUT = 1mA (2) ΔVOUT mV Load Regulation 1 < IOUT < 300 mA 1 VDO DropoutVoltage IOUT = 300 mA NominalVOUT = 2.8V 220 310 mV (3) IOUT OutputCurrent 0 300 mA ISLEEP Max OutputCurrentin 1 mA SleepMode ISC OutputCurrentLimit VOUT = 0V 625 mA eN OutputVoltageNoise 10 Hz ≤ f≤ 100 KHz 10 10 µVRMSIOUT = 300 mA PSRR Power SupplyRejection f≤ 10 KHz, IOUT = 20 mA 75 dBRatio tSTUP StartupTime IOUT = 0 mA to300 mA inIdlemode. 35 µs VOS Start-upOvershoot IOUT = 300 mA (4) 30 mV C OUT ExternalOutput (4) 0.5 1 20 µFCapacitanceforStability (1) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotverified,butdo representthemost likely norm. (2) The minimum inputvoltageequalsVOUT (nom)+ 0.5Vor2.5V,whicheverisgreater. (3) Dropoutvoltageisthevoltagedifferencebetween theinputand theoutputatwhichtheoutputvoltagedropsto100 mV belowits nominalvalue. (4) Thisspecificationisguaranteedby design. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com LOW-INPUT LOW-OUTPUT LDO (LILO1,LILO2) Unlessotherwisenoted,VIN1=VIN2=VIN3=VINB1=VINB2=VINLILO1=VINLILO2=3.6V;C LODX =1µF;C BUCKOUT =C BUCKIN =4.7µF, C VIN1–3=C VINLILO1C VINLILO2=2.2µF.Typicalvaluesand limitsappearinginnormaltypeapplyforTJ=25°C. Limitsappearingin boldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,TJ= -40to+125°C. (1) Symbol Parameter Conditions Min Typ Max Unit −2 +2LILO1 OutputVoltage Accuracy −3 +3 VOUT IOUT = 1mA, VOUT = 1.8V % −3 +3LILO2 OutputVoltage Accuracy −4 +4 LineRegulation VOUT + 0.5V≤ VLILO ≤ 4.5V 1IOUT = 1mAΔVOUT mV Load Regulation 1 < IOUT < 300 mA 5 VDO DropoutVoltage IOUT = 300 mA 230 310 mVNominalVOUT = 1.8V (2) IOUT OutputCurrent 0 300 mA ISLEEP Max OutputCurrentin mA1SleepMode ISC OutputCurrentLimit VOUT = 0V 670 mA eN OutputVoltageNoise 10 Hz ≤ f≤ 100 KHz 80 µVRMS IOUT = 300 mA PSRR Power SupplyRejection f≤ 10 KHz, IOUT = 20 mA 60 dB Ratio tSTUP StartupTime IOUT = 0 mA to300 mA inIdlemode. 65 µs VOS Start-upOvershoot (3) 30 mV C OUT ExternalOutput (3) 0.5 1 20 µFCapacitanceforStability (1) Min and Max limitsarespecifiedby design,testorstatisticalanalysis.Typicalnumbers arenotverified,butdo representthemost likely norm. (2) Dropoutvoltageisthevoltagedifferencebetween theinputand theoutputatwhichtheoutputvoltagedropsto100 mV belowits nominalvalue. (3) Thisspecificationisguaranteedby design.

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 LP8725 CONTROL REGISTERS Table8.ControlRegisters RegisterADDR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0Name SHORT_ BUCK2_ SLEEP_ BUCK1_0x00 GENERAL TIMESTEP 0 DVS2_V DVS1_VTIMESTEP EN MODE EN LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO10x01 LDO1 T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LDO2 LDO2 LDO2 LDO2 LDO2 LDO2 LDO2 LDO20x02 LDO2 T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LDO3 LDO3 LDO3 LDO3 LDO3 LDO3 LDO3 LDO30x03 LDO3 T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LDO4 LDO4 LDO4 LDO4 LDO4 LDO4 LDO4 LDO40x04 LDO4 T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LDO5 LDO5 LDO5 LDO5 LDO5 LDO5 LDO5 LDO50x05 LDO5 T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LILO1_ LILO1_ LILO1_ LILO1_ LILO1 LILO1_ LILO1_ LILO1_0x06 LILO1 T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LILO2_ LILO2_ LILO2_ LILO2_ LILO2_ LILO2_ LILO2_ LILO2_0x07 LILO2 T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_0x08 BUCK1 V1 T[2] T[1] T[0] V1[4] V1[3] V1[2] V1[1] V1[0] BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_0x09 BUCK1 V2 0CL[1] CL[0] V2[4] V2[3] V2[2] V2[1] V2[0] BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_0x0A BUCK2 V1 T[2] T[1] T[0] V1[4] V1[3] V1[2] V1[1] V1[0] BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_0x0B BUCK2 V2 0CL[1] CL[0] V2[4] V2[3] V2[2] V2[1] V2[0] BUCK BK2_ BK1_ PWM_ PDN_ PWM_ PDN_0x0C 0 0CONTROL FLAG MASK FLAG MASK BUCK2 BUCK2 BUCK1 BUCK1 LDO LDO1_ LILO2_ LILO1_ LDO5_ LDO4_ LDO3_ LDO2_ LDO1_0x0D CONTROL FLAG MASK EN EN EN EN EN EN EN PULL APU_ PDN PDN PDN PDN PDN PDN PDN0x0E DOWN TSD LILO2 LILO1 LDO5 LDO4 LDO3 LDO2 LDO1BITS STATUS LDO1_ B2_ B1_0x0F REVISION[3] REVISION[2] REVISION[1] REVISION[0] TSDBITS OKN OKN OKN Table9.ControlRegisterDefaults LP8725 Defaults:DEFSEL state LP8725-A Defaults:DEFSEL state LP8725-B Defaults:DEFSEL state ADDR VIN1 GND VIN1 GND VIN1 GND 0x00 0101 1001 0101 1001 0000 0000 0101 0001 1101 1101 1101 1101 0x01 1001 1001 0011 0101 0001 0101 1001 1001 1011 0101 1010 1100 0x02 1000 1100 0011 1001 0001 1101 0111 1001 1111 1001 1111 1001 0x03 1011 1111 0101 1001 1111 1111 0111 1001 1111 1001 1111 1001 0x04 1001 1111 0101 1001 0011 1101 1001 1001 1110 0000 1110 0000 0x05 1001 1001 0011 1001 0001 1001 1001 1001 1110 0000 1110 0000 0x06 1010 1000 0011 1111 0001 0000 1011 0000 1111 0111 1111 0111 0x07 0100 1000 0000 1000 0010 0100 1011 0000 1101 1111 1101 1111 0x08 0000 0100 0000 1000 1110 0110 0000 1010 0000 1000 0000 1000 0x09 1100 1000 1100 0100 1100 0100 1100 1000 1100 1000 1100 1000 0x0A 0101 0001 0011 0001 1110 0110 0000 1010 1001 0001 1001 0001 0x0B 1001 0001 1001 0001 1000 0100 1000 1000 1001 0001 1001 0001 0x0C 0111 1111 0001 0001 1101 0001 1101 0001 0001 0001 0001 0001 Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Table9.ControlRegisterDefaults(continued) LP8725 Defaults:DEFSEL state LP8725-A Defaults:DEFSEL state LP8725-B Defaults:DEFSEL state ADDR VIN1 GND VIN1 GND VIN1 GND 0x0D 0111 1111 0111 1111 1111 1011 1111 1111 0100 0001 0100 0001 0x0E 0111 1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 1111 0x0F 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 LP8725-C Defaults:DEFSEL state LP8725-D Defaults:DEFSEL state ADDR VIN1 GND VIN1 GND 0x00 1101 1101 1101 1101 1001 1101 1001 1101 0x01 1001 0101 1001 0101 1111 1001 1111 1001 0x02 1001 1001 1001 1001 1110 1100 1110 1100 0x03 1011 1001 1011 1001 0100 1100 0100 1100 0x04 1011 0100 1011 0100 1111 1101 1111 1101 0x05 0101 1111 0101 1111 1110 0000 1110 1100 0x06 1000 1000 1000 1000 0101 1101 0101 1101 0x07 1000 1000 1000 1000 0101 1101 0101 1101 0x08 0000 1000 0000 1000 0000 1010 0000 1010 0x09 1100 1000 1100 1000 1100 1010 1100 1010 0x0A 0101 0001 0101 0001 0101 0001 0101 0001 0x0B 1001 0001 1001 0001 1101 0001 1101 0001 0x0C 0001 0001 0001 0001 0001 0001 0001 0001 0x0D 0111 1111 0111 1111 0110 0100 0110 0100 0x0E 0111 1111 0111 1111 0111 1111 0111 1111 0x0F 0000 0000 0000 0000 0000 0000 0000 0000 Table10.Register0X00 Addr Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x00 GENERAL TIMESTEP SHORT_ BUCK2_E DVS2_V DVS1_V SLEEP_MO BUCK1_EN TIMESTEP N DE BUCK1_EN BUCK1, BUCK2 enablecontrol BUCK2_EN InSTANDBY mode InIDLE mode thebithas immediateeffect. 1:DuringnextSTARTUP sequence willbe enabled. 1:Enable 0:DuringnextSTARTUP sequence willbe NOT 0:Disable enabled Forproperoperationoutputtiminghaving“111 -NO startup”shouldhave correspondingenablebit0 (disable) SLEEP_MODE LDO SleepControl 1:SLEEP mode 0:normal DVS1_V 1:drivebuck voltagetovaluestoredinBUCK1_V1[4:0] 0:Buck outputvoltagecontrolledby externalDVS pin. DVS2_V 1:drivebuck voltagetovaluestoredinBUCK2_V1[4:0] 0:Buck outputvoltagetovaluestoredinBUCK2_V2[4:0] SHORT_TIMESTEP TIMESTEP = 0 TIMESTEP = 1 TIMESTEP SHORT_TIMESTEP = 0 — timestepts = 32 µs SHORT_TIMESTEP = 0 — timestepts = 128 µs SHORT_TIMESTEP = 1 — timestepts = 64 µs SHORT_TIMESTEP = 1— timestepts = 256 µs

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Table11.Registers0x01-0x05,0x06-0x07,0x08-0x0B Addr Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x01 LDO1 O/P LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 0x02 LDO2 O/P LDO2 LDO2 LDO2 LDO2 LDO2 LDO2 LDO2 LDO2 0x03 LDO3 O/P LDO3 LDO3 LDO3 LDO3 LDO3 LDO3 LDO3 LDO3 0x04 LDO4 O/P LDO4 LDO4 LDO4 LDO4 LDO4 LDO4 LDO4 LDO4 0x05 LDO5 O/P LDO5 LDO5 LDO5 LDO5 LDO5 LDO5 LDO5 LDO5 0x06 LILO1 O/P LILO1_ LILO1_ LILO1_ LILO1_ LILO1_ LILO1_ LILO1_ LILO1_ 0x07 LILO2 O/P LILO2_ LILO2_ LILO2_ LILO2_ LILO2_ LILO2_ LILO2_ LILO2_ 0x08 BUCK1 O/P1 BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ 0x09 BUCK1 O/P2 BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ BUCK1_ 0x0A BUCK2 O/P1 BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ 0x0B BUCK2 O/P2 BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ BUCK2_ Registers0x01 -0x05 Output VoltageSelection LDO1_V[4:0] 00000 1.20V 01000 1.60V 10000 2.10V 11000 2.75V LDO2_V[4:0] 00001 1.25V 01001 1.65V 10001 2.20V 11001 2.80V LDO3_V[4:0] 00010 1.30V 01010 1.70V 10010 2.30V 11010 2.85V LDO4_V[4:0] 00011 1.35V 01011 1.75V 10011 2.40V 11011 2.90V LDO5_V[4:0] 00100 1.40V 01100 1.80V 10100 2.50V 11100 2.95V 00101 1.45V 01101 1.85V 10101 2.60V 11101 3.00V 00110 1.50V 01110 1.90V 10110 2.65V 11110 3.10V 00111 1.55V 01111 2.00V 10111 2.70V 11111 3.30V Registers0x06 -0x07 Output VoltageSelection LILO1_V[4:0] 00000 0.80V 01000 1.20V 10000 1.80V 11000 2.60V LILO2_V[4:0] 00001 0.85V 01001 1.25V 10001 1.90V 11001 2.70V 00010 0.90V 01010 1.30V 10010 2.00V 11010 2.80V 00011 0.95V 01011 1.35V 10011 2.10V 11011 2.85V 00100 1.00V 01100 1.40V 10100 2.20V 11100 2.90V 00101 1.05V 01101 1.50V 10101 2.30V 11101 3.00V 00110 1.10V 01110 1.60V 10110 2.40V 11110 3.10V 00111 1.15V 01111 1.70V 10111 2.50V 11111 3.30V Registers0x08 -0x0B Output VoltageSelection BUCK1_V[4:0] 00000 0.80V 01000 1.20V 10000 1.75V 11000 2.40V BUCK2_V[4:0] 00001 0.85V 01001 1.25V 10001 1.80V 11001 2.50V 00010 0.90V 01010 1.30V 10010 1.85V 11010 2.60V 00011 0.95V 01011 1.35V 10011 1.90V 11011 2.70V 00100 1.00V 01100 1.40V 10100 2.00V 11100 2.80V 00101 1.05V 01101 1.50V 10101 2.10V 11101 2.85V 00110 1.10V 01110 1.60V 10110 2.20V 11110 2.90V 00111 1.15V 01111 1.70V 10111 2.30V 11111 3.00V Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Registers0x01 -0x08,0x0A StartupDelay Selection LDO1_T[2:0] 000 -startupdelay0 LDO2_T[2:0] 001 -startupdelay= 1 *timestepts LDO3_T[2:0] 010 -startupdelay= 2 *timestepts LDO4_T[2:0] 011 -startupdelay= 3 *timestepts LDO5_T[2:0] 100 -startupdelay= 4 *timestepts LILO1_T[2:0] 101 -startupdelay= 5 *timestepts LILO2_T[2:0] 110 -startupdelay= 6 *timestepts BUCK1_T[2:0] 111 -NO startup BUCK2_T[2:0] Forproperstartupoperation“NO startup”<111> shouldhave thecorresponding enablebitinregisters0x00 & 0x0D setto0 (disable) Registers0x09,0x0B Buck CurrentLimitSelection BUCK1_CL[1:0] 00 -460 mA peak (250mA max IOUT ) BUCK2_CL[1:0] 01 -780 mA peak (450mA max IOUT ) 10 -1050 mA peak (600mA max IOUT ) 11 -1370 mA peak (800mA max IOUT ) Register0x0C PDN_BUCK1 Pull-downBUCK1/2: PDN_BUCK2 1 -Pulldown enabled 0 -Pulldown disabled PWM_BUCK1 1 -BUCK1/2 isforcedtowork inPWM mode PWM_BUCK2 0 -BUCK1/2 worksinautomaticECO/PWM selectionmode BK1_FLAG MASK 1 -Mask theBUCK OK flag BK2_FLAG MASK 0 -No maskingofBUCK OK flag Register0x0D LDO Enable Control LDO1_EN InSTANDBY mode: InIDLE mode thebithas immediateeffect. LDO2_EN 1 -DuringnextSTARTUP sequence willbe 1 -Enable LDO3_EN enabled. 0 -Disable LDO4_EN 0 -Duringnextstartupsequence willbe LDO5_EN NOT enabled. LILO1_EN LILO2_EN LDO1_FLAG MASK 1-Mask theLDO1 OK flag 0 -No maskingofLDO1 OK flag Register0x0E PullDown PDNLDO1 LDO pull-downcontrol PDNLDO2 1 -Pulldown enabled PDNLDO3 0 -Pulldown disabled PDNLDO4 PDNLDO5 PDNLILO1 PDNLILO2 APU_TSD ThisbitdefineseithertoresetregistersornotbeforethePMU automaticallystartsstartup sequence fromThermalShutdown aftercoolingdown ifEN-pinisHigh. 1 -No change toregisters-contentstaysthesame as beforeThermalShutdown. 0 -IfCONFIG = '1'ResetregisterstodefaultvaluesbeforestartupfromThermal Shutdown.

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Table12.Register0x0F (Read Only Register) Addr Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x10 STATUS REVISION[3] REVISION[2] REVISION[1] REVISION[0] LDO1_OK B2_OKN B1_OKN TSD N TSD 1 -DeviceisinThermalShutdown 0 -DeviceisNOT inThermalShutdown B1_OKN 1 -Outputvoltagenotinregulation B2_OKN 0 -Outputvoltageinregulation LDO1_OKN REVISION[3:0] LP8725 Mask setrevision. To be incremented,whenever themask setisedited. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com OPERATION DESCRIPTION Device Information Using voltagemode architecturewithsynchronousrectification,theLP8725 has theabilitytodeliverup to800 mA per DC-DC convertordepending on the inputvoltageand outputvoltage,ambient temperature,and the inductorchosen. There aretwo modes ofoperationdependingon thecurrentrequired-PWM (PulseWidthModulation),and ECO The deviceoperatesinPWM mode at loadcurrentsof approximately75 mA (typ.)or higher.Lighteroutput currentloadscause thedevicetoautomaticallyswitchintoECO mode forreducedcurrentconsumption. CircuitOperation The DC-DC convertoroperatesas follows.Duringthefirstportionofeach switchingcycle,thecontrolblockinthe turnson theinternalPFET switch.Thisallowscurrenttoflowfrom theinputthroughtheinductortotheoutput filtercapacitorand load.The inductorlimitsthecurrenttoa ramp witha slopeof(VIN − VOUT )/L,by storingenergy ina magneticfield.Duringthesecond portionofeach cycle,thecontrollerturnsthePFET switchoff,blocking currentflowfrom theinput,and thenturnstheNFET synchronousrectifieron.The inductordraws currentfrom ground throughtheNFET totheoutputfiltercapacitorand load,which ramps theinductorcurrentdown witha slopeof–VOUT /L. The outputfilterstoreschargewhen theinductorcurrentishigh,and releasesitwhen low,smoothingthevoltage acrosstheload.The outputvoltageisregulatedby modulatingthePFET switchon timetocontroltheaverage currentsenttotheload.The effectisidenticaltosendinga duty-cyclemodulatedrectangularwave formedby the switchand synchronousrectifierat the SW pin to a low-passfilterformed by the inductorand outputfilter capacitor.The outputvoltageisequaltotheaveragevoltageattheSW pin. PWM Operation DuringPWM operationtheconverteroperatesas a voltage-modecontrollerwithinputvoltagefeedforward.This allowstheconvertertoachieveexcellentloadand lineregulation.The DC gainofthepower stageisproportional to the inputvoltage.To eliminatethisdependence,feed forwardinverselyproportionalto the inputvoltageis introduced.WhileinPWM mode, theoutputvoltageisregulatedby switchingata constantfrequencyand then modulatingthe energy per cycleto controlpower to the load.At the beginningof each clockcyclethe PFET switchisturnedon and theinductorcurrentramps up untilthecomparatortripsand thecontrollogicturnsoffthe switch.The currentlimitcomparatorcan also turnoffthe switchin case the currentlimitof the PFET is exceeded.Then theNFET switchisturnedon and theinductorcurrentramps down. The nextcycleisinitiatedby theclockturningofftheNFET and turningon thePFET. Figure13. TypicalPWM Operation

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 InternalSynchronous Rectification WhileinPWM mode, theDC-DC convertoruses an internalNFET as a synchronousrectifiertoreducerectifier forwardvoltagedropand associatedpower loss.Synchronousrectificationprovidesa significantimprovementin efficiencywhenever theoutputvoltageisrelativelylow compared tothevoltagedropacrossan ordinaryrectifier diode. CurrentLimiting A currentlimitfeatureallowsthe DC-DC convertorto protectitselfand externalcomponents duringoverload conditions.PWM mode implementscurrentlimitusingan internalcomparatorthattripsat1.05A (typ.)assuming IOUT = 600 mA. Iftheoutputisshortedtogroundand outputvoltagebecomes lowerthan0.3V (typ.),thedevice entersa timedcurrentlimitmode where the switchingfrequencywillbe one fourth,and NFET synchronous rectifierisdisabled,therebypreventingexcesscurrentand thermalrunaway. The currentlimitforeach DC-DC convertorisselectableviaserialinterfaceby registers0x09 bits6,7 and 0x0B bits6,7.The currentlimitselectedshouldbe ~ 1.5xto2xgreaterthantheoutputcurrentrequired. ECO Mode Operation By defaultthe DC-DC converterwillbe inAuto (ECO/PWM) Mode . By doingso the partswitchesfrom ECO (ECOnomy) statetoPWM (PulseWidthModulation)statebased on outputloadcurrent.At lightloads(lessthan 75mA approx)theconverterentersECO mode. Inthismode thepartoperateswithlowIq.DuringECO operation theconverterpositionstheoutputvoltageslightlyhigher(+30mV typ.)thanthenominaloutputvoltageinPWM operation.Because thereferenceissethigher,theoutputvoltageincreasestoreachthetargetvoltagewhen the partgoes from sleepstateto switchingstate.Once thisvoltageisreached the converterenterssleepmode, therebyreducingswitchinglossesand improvinglightloadefficiency.The outputvoltagerippleisslightlyhigher inECO mode (30mV p–p typ.). Figure14. TypicalECO Operation Note thatground noisemay impactquiescentcurrentinECO mode and care at board layoutisimportantto minimizethisrisk.See sectionon layoutguidelines. Startup The LP8725 bucks have a ‘soft-start’featuretolimitthein-rushcurrent.Thispreventslargecurrentspikesand voltageovershootand alsolimitsthe cases inwhich the inductormay saturate.At or closeto 0V the inrush currentto the capacitor(and load)islimitedto itsshortcircuitprotectionlimitof typically500 mA. Above a thresholdof around 150 mV, the currentlimitisincreasedto the buck’s peak currentlimitsetby the control registers.(Fora 600 mA max loadthisissettoapprox.1050 mA.) While in short-circuitprotection,the outputswitchesoff,but willcontinueto attemptto restart.Ifthe total capacitanceon the buck outputislargeor ifthe inductorvaluedrops too low,the thresholdmightnever be reached,so thebuck may notstart.See InductorSelectionand OutputCapacitorSelectionsections. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Stability The stabilityofthebuck isoptimizedforthe4.7µF capacitorsrecommended inthedatasheet.Eithertoosmallor toolargea capacitancecan cause an oscillationattheoutputand/orexcessiveringingduringloadtransients.Itis advisablenot to exceed a totalof 15 µF capacitanceat the output.See Table 14 forrecommended output capacitors. See alsotherecommended inductorstable(Table13)as stabilitymay be compromised by theuse ofinductors whose actualvaluemay change significantlyfromitsnominalvaluedue totheoperatingconditions.Thismay be thecase forthesmallercase sizechipinductors.

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VPP-RMS = VPP-C 2 + VPP-ESR 4 x f x CVPP-C = IRIPPLE (Vin ± Vout) x Vout L x f x Ioutmax x Vin where r = +IRMS = IOUTMAX x x 1 - VOUT VIN VOUT VIN LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013

APPLICATION INFORMATION

DC bias currentcharacteristicsof inductorsmust be considered.Differentmanufacturersfollowdifferent saturationcurrentratingspecifications,so attentionmust be giventodetails.DC biascurvesshouldbe requested fromthem as partoftheinductorselectionprocess. Minimum value of inductance to guarantee good performance is 0.5 µH at 1.5A (ILIM typ.)bias current over the ambient temp range.The inductor’s DC resistanceshouldbe lessthan 0.1Ω forgood efficiencyat highcurrentcondition.The inductorAC loss(resistance)alsoaffectsconversionefficiency.HigherQ factorat switchingfrequencyusuallygivesbetterefficiencyatlightloadtomedium loadinstead.Table13 listssuggested inductorsand suppliers. InputCapacitorSelection A ceramicinputcapacitorof4.7μF,6.3V/10Vissufficientformost applications.Placetheinputcapacitoras close as possibletotheVIN pinand GND pinofthedevice.A largervalueor highervoltageratingmay be used to improveinputvoltagefiltering.Use X7R, X5R orB types,do notuse Y5V orF. Minimum inputcapacitanceto guaranteegood performance is4.7µF atmaximum inputvoltageDC bias includingtolerancesand over ambient temp range.The inputfiltercapacitorsuppliescurrentto the PFET (high-side)switchinthefirsthalfofeach cycleand reducesvoltagerippleimposed on theinputpower source.A ceramiccapacitor'slow ESR providesthe best noisefilteringof the inputvoltagespikesdue to thisrapidly changingcurrent.Selectan inputfiltercapacitorwithsufficientripplecurrentrating.The inputcurrentripplecan be calculatedas: (1) (2) Output CapacitorSelection Use a 4.7μF,6.3V ceramiccapacitor,X7R, X5R orB types,do notuse Y5V orF.DC biasvoltagecharacteristics ofceramiccapacitorsmust be considered.DC biascharacteristicsvaryfrom manufacturertomanufacturerand DC biascurvesshouldbe requestedfrom them as partof the capacitorselectionprocess.The outputfilter capacitorsmooths outcurrentflowfrom theinductortotheload,helpsmaintaina steadyoutputvoltageduring transientload changes and reduces outputvoltageripple.These capacitorsmust be selectedwithsufficient capacitanceand sufficientlylowESR toperformthesefunctions. Minimum output capacitanceto guarantee good performance is 2.2 µF at the output voltageDC bias includingtolerancesand over ambient temp range.The outputvoltagerippleiscaused by thechargingand dischargingoftheoutputcapacitorand alsodue toitsESR and can be calculatedas: Voltagepeak topeak rippledue tocapacitance= Voltagepeak-to-peakrippledue toESR = VPP-ESR = (2x IRIPPLE )x R ESR Because thesetwo components are out of phase the rms valuecan be used to get an approximatevalueof peak-to-peakripple. Voltagepeak-to-peakripple,rootmean squared= Note thattheoutputrippleisdependenton thecurrentrippleand theequivalentseriesresistanceoftheoutput capacitor(ESR).The RESR isfrequencydependent(aswellas temperaturedependent);make surethevalue used forcalculationsisattheswitchingfrequencyofthepart. Table14 listssuggestedcapacitorsand suppliers. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Table13. Suggested Inductorsand Suppliers Model Vendor Dimensions LxWxH (mm) DCR (mΩ) LQM2HPN 1R0MG0 Murata 2.5x 2.0x 1.0(Max) 55 MIPSZ2520D1R0 FDK 2.5x 2.0x 1.0(Max) 90 MIPSZ2012D1R0 FDK 2.0x 1.25x 1.0(Max) 90 LPS3010-102NLC Coilcraft 3.3x 3.3x 1.0(Max) 85 Table14. Suggested Capacitorsand Suppliers Model Type Vendor VoltageRating Case SizeInch(mm) 4.7µF forC IN and C OUT C1608X5R0J475K Ceramic TDK 6.3 0603 (1608) C1608X5R1A475K Ceramic TDK 10 0603 (1608) Dynamic VoltageScaling Buck 1 and Buck 2 can be switchedbetween two outputvaluesstoredinregisters0x08 and 0x09 forBuck1 and 0x0A and 0x0B forBuck2. ForBuck 2 outputthiscontrolisachievedby changingtheDVS2_V bitintheGENERAL register0x00 (bit3). DVS2_V OUTPUT Reg0x00 Bit3

0 BUCK2_V2 Reg 0x0B[4-0]

1 BUCK2_V1 Reg 0x0A[4-0]

For Buck 1 thiscontrolcan be eitherviatheexternalDVS pinor viatheDVS1_V bitintheGENERAL register 0x00 (bit2).The controlconfigurationsareshown inthefollowingtable. DVS1 DVS pin OUTPUT Reg0x00 Bit2 0 0 BUCK1_V2 Reg 0x09[4-0] 0 1 BUCK1_V1 Reg 0x08[4-0] 1 0 BUCK1_V2 Reg 0x09[4-0] 1 1 BUCK1_V1 Reg 0x08[4-0] LDO Information Therearealltogether7 LDOs inLP8725 groupedas

DIGITAL;
ANALOG; and
LOW INPUT LOW OUTPUT (LILO) AllLDOs can be programmed throughserialinterfacefordifferentoutputvoltagevalues,whicharesummarized intheoutputvoltageselectiontables. At thePMU power on,LDOs startupaccordingtotheselectedstartupsequence and thedefaultvoltages.See STARTUP and SHUTDOWN Sequences fordetails. For stabilityallLDOs need tohave externalcapacitorsC OUT connectedtotheoutputwithrecommended valueof 1µF.Itisimportanttoselectthetypeofcapacitorwhose capacitancewillinno case (voltage,temperature,etc) be outsideoflimitsspecifiedintheLDO electricalcharacteristics.

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www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Analog-Type LDOs The analog LDOs are optimizedforsupplyinganalog loads having ULTRA LOW NOISE (10 µVRMS for IOUT >5mA) and excellentPSRR (70 dB at 10 kHz) performance.They can be programmed throughserial interfacefordifferentoutputvoltagevalues. For fastdischargingofoutputcapacitorsinshutdown,theLDOs may be connectedtoa 300Ω pulldown resistor tooutput. Insleepmode quiescentcurrentislowereddown to30 µA forenergysaving.Inthismode theseLDOs should notloadedmore than3-5mA ofoutputcurrent. Digital-TypeLDOs The DigitalLDOs are optimizedfordynamic performanceforfastchangingdigitalloadswhilstconsuming very littlequiescentcurrent~ 20 µA .They can be programmed throughserialinterfacefordifferentoutputvoltage values. For fastdischargingofoutputcapacitorsinshutdown,theLDOs may be connectedtoa 300Ω pulldown resistor tooutput. Insleepmode quiescentcurrentislowereddown to10 µA forenergysaving.Inthismode theseLDOs should notloadedmore than3-5mA ofoutputcurrent. LILO-Type LDOs The LILO-typeLDO isoptimizedforlowoutputvoltageand forgood dynamicperformancetosupplydifferentfast changing(digital)loads.These LDOs can be operatedas digitalLDOs alsoalbeitwithlowerPSRR and Noise performance. An innovativedesignofthealltheLDOs reducessensitivitytotheplacementoftheoutputcapacitor.The output capacitormay not be placedas closeas possibleto the outputpin,likeon conventionalLDOs. The general purpose LDOs do not need outputcapacitorcloseto the PMU. Ifa (1 µF or more) capacitorisattachedto a circuitload,customermay skiptheoutputcapacitoratthePMU. I2C-CompatibleSerialBus Interface InterfaceBus Overview The I2C-compatiblesynchronousserialinterfaceprovidesaccesstotheprogrammablefunctionsand registerson thedevice. Thisprotocoluses a two-wireinterfaceforbi-directionalcommunicationsbetween theICs connectedtothebus. The two interfacelinesare theSerialData Line(SDA),and theSerialClockLine(SCL).These linesshouldbe connectedtoa positivesupply,viaa pull-upresistorof1.5KΩ and remainHIGH even when thebus isidle. Every deviceon the bus isassigneda uniqueaddressand actsas eithera Master or a Slave dependingon whetheritgeneratesorreceivestheserialclock(SCL). Data Transactions One data bitistransferredduringeach clockpulse.Data issampled duringthe highstateof the serialclock (SCL).Consequently,throughoutthe clock’s highperiod,the data shouldremain stable.Any changes on the SDA lineduringthehighstateoftheSCL and inthemiddleofa transaction,abortsthecurrenttransaction.New data should be sent duringthe low SCL state.This protocolpermitsa singledata lineto transferboth command/controlinformationand datausingthesynchronousserialclock. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:LP8725

START CONDITION STOP CONDITION Data Line Stable: Data Valid Change of Data Allowed SDA SCL LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Figure15. BitTransfer Each datatransactioniscomposed ofa StartCondition,a number ofbytetransfers(setby thesoftware)and a Stop Conditionto terminatethe transaction.Every byte writtento the SDA bus must be 8 bitslong and is transferredwiththemost significantbitfirst.Aftereach byte,an Acknowledge signalmust follow.The following sectionsprovidefurtherdetailsofthisprocess. Startand Stop The Master deviceon the bus always generatesthe Startand Stop Conditions(controlcodes).Aftera Start Conditionisgenerated,the bus isconsideredbusy and itretainsthisstatusuntila certaintimeaftera Stop Conditionisgenerated.A high-to-lowtransitionofthedataline(SDA) whiletheclock(SCL) ishighindicatesa StartCondition.A low-to-hightransitionoftheSDA linewhiletheSCL ishighindicatesa StopCondition. Figure16. Startand Stop Conditions InadditiontothefirstStartCondition,a repeatedStartConditioncan be generatedinthemiddleofa transaction. Thisallowsanotherdevicetobe accessed,ora registerreadcycle. Acknowledge Cycle The Acknowledge Cycleconsistsoftwo signals:theacknowledgeclockpulsethemastersends witheach byte transferred,and theacknowledgesignalsentby thereceivingdevice.The mastergeneratestheacknowledge clockpulseon theninthclockpulseofthebytetransfer.The transmitterreleasestheSDA line(permitsittogo high)toallowthereceivertosend theacknowledgesignal.The receivermust pulldown theSDA lineduringthe acknowledge clockpulseand ensure thatSDA remains low duringthe high periodof the clockpulse,thus signalingthecorrectreceptionofthelastdatabyteand itsreadinesstoreceivethenextbyte.

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S Start Condition Transmitter Stays Off the Bus During the Acknowledgement Clock Acknowledgement Signal From Receiver 1 2 3 - 6 7 8 9 LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Figure17. Bus Acknowledge Cycle ”Acknowledge afterEvery Byte” Rule The mastergeneratesan acknowledgeclockpulseaftereach bytetransfer.The receiversends an acknowledge signalaftereverybytereceived. Thereisone exceptiontothe“acknowledgeaftereverybyte”rule. When the master is the receiver,itmust indicateto the transmitteran end of data by not-acknowledging (“negativeacknowledge”) the lastbyteclockedout of the slave.This“negativeacknowledge” stillincludesthe acknowledgeclockpulse(generatedby themaster),buttheSDA lineisnotpulleddown. Addressing TransferFormats Each deviceon thebus has a uniqueslaveaddress.The LP8725 operatesas a slavedevice.Slaveaddressis selectableby CONFIG and DEFSEL pins. Fortheactualslaveaddresses,see Table1. Beforeany dataistransmitted,themastertransmitstheaddressoftheslavebeingaddressed.The slavedevice shouldsend an acknowledgesignalon theSDA line,once itrecognizesitsaddress. The slaveaddressisthefirstseven bitsaftera StartCondition.The directionofthedatatransfer(R/W) depends on thebitsentaftertheslaveaddresstheeighthbit. When theslaveaddressissent,each deviceinthesystemcompares thisslaveaddresswithitsown. Ifthereisa match,thedeviceconsidersitselfaddressedand sends an acknowledgesignal.Depending upon thestateofthe R/W bit(1:read,0:write),thedeviceactsas a transmitterora receiver. ControlRegisterWriteCycle

Masterdevicegeneratesstartcondition.
Masterdevicesends slaveaddress(7bits)and thedatadirectionbit(r/w= '0').
Slavedevicesends acknowledgesignaliftheslaveaddressiscorrect.
Mastersends controlregisteraddress(8bits).
Slavesends acknowledgesignal.
Mastersends databytetobe writtentotheaddressedregister.
Slavesends acknowledgesignal.
Ifmaster willsend furtherdata bytes the controlregisteraddress willbe incrementedby one after acknowledgesignal.
Writecycleends when themastercreatesstopcondition. ControlRegisterRead Cycle
Masterdevicegeneratesa startcondition.
Masterdevicesends slaveaddress(7bits)and thedatadirectionbit(r/w= '0').

(7 bits) '0' A A A PControl Register Add. (8 bits) (8 bits) Register Data Data transferred, byte + Ack A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION From Slave to Master From Master to Slave LP8725 SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com

Mastersends controlregisteraddress(8bits).
Slavesends acknowledgesignal.
Masterdevicegeneratesrepeatedstartcondition.
Mastersends theslaveaddress(7bits)and thedatadirectionbit(r/w= “1”).
Slavesends acknowledgesignaliftheslaveaddressiscorrect.
Slavesends databytefromaddressedregister.
Ifthemasterdevicesends acknowledgesignal,thecontrolregisteraddresswillbe incrementedby one.Slave devicesends databytefromaddressedregister.
Read cycleends when themasterdoes notgenerateacknowledgesignalafterdatabyteand generatesstop condition. AddressMode Data Read <StartCondition> <SlaveAddress><r/w= ‘0’>[Ack] <RegisterAddr.>[Ack] <Repeated StartCondition> <SlaveAddress><r/w= ‘1’>[Ack] [RegisterData]<Ack orNAck > … additionalreadsfromsubsequentregisteraddresspossible <StopCondition> Data Write <StartCondition> <SlaveAddress><r/w= ‘0’>[Ack] <RegisterAddr.>[Ack] <RegisterData>[Ack] … additionalwritestosubsequentregisteraddresspossible <StopCondition> < > Data frommaster[]Data fromslave RegisterRead and WriteDetail Figure18. RegisterWriteFormat

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(7 bits) '0' A A Control Register Add. (8 bits) From Slave to Master From Master to Slave Slave Address (7 bits) ASr '1' R/W Data transferred, byte + Ack/NAck Register Data (8 bits) P A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION NA - ACKNOWLEDGE (SDA High) Sr - REPEATED START CONDITION Direction of the transfer will change at this point NA LP8725 www.ti.com SNVS618G –DECEMBER 2009–REVISED MAY 2013 Figure19. RegisterRead Format Layout Guidelines As forallDC-DC buck regulatorsboardlayoutisveryimportanttoensurebestperformance. The 4.7µF inputcapacitorsshouldbe placedfirst,as near toVINB1/2 pinand GNDB1/2 as possible.VINB1/2 are thevoltagerailsforthehigh-sidepower FETs. GNDB1/2 are thereturnpathsforthelow-sidepower FETs. The Inputcapacitorsshould have theirassociatedpads very near the pins thatthey willdecouple.These capacitorsareimportantinsourcingchargeduringswitchingevents.Inthisdevicewe have thetwo buck inputs side by side but we recommend thatseparatetracesare taken to each devicepin to ensure thisproper decoupling.Thiscan be seen intheexample layoutshown inthelayoutscheme below. The 4.7µF outputcapacitorsshouldbe thenextcomponents tobe placedinconjunctionwiththeinductor.The switchnode shouldbe keptas smallas possiblebutotherwisetheinductorplacementisleastsensitivetolayout variation.BestperformanceoftheLP8725 willbe realizedby maintainingtightphysicalcouplingofthegrounds oftheinputcapacitor,outputcapacitorand GND pinforeach switcher.The inductorshouldbe placedina way thatbestallowstheswitchingnode,outputnode,and tracktotheloadcircuittobe routedeasily. The groundingis very importantand any additionalresistance/inductanceshould be minimized.A ground polygonand/orplaneshouldbe used totieallcapacitorgroundstogetherand directlytothebuck GNDs. See the layoutscheme belowas an example. Finally,thefeedbacknetsshouldbe routed,where possibleroutethisaway from any switchingnodes and tie intotheoutputnode oftheregulator.The FB linesshouldcloselymatch theGND routingtoreducetheinductive loopof thispair.The FB and GND linesmake up a high-sideand low-sidesense connectionto maintainthe accuracy of the switcheroutputs.Ifthe FB lineshould cross the switchingtracemake thisas close to perpendicularas possible. Low impedance power connectionsshouldbe maintainedforalloftheseconnections.Care shouldalsobe given totheground routingforinputlinesand outputlinestominimizeinductiveloops,normallythisshouldbe taken careofby suitablegroundplanes. As thisisa dualbuck devicetherearea number ofaspectstobe aware of.The switchersarealmosta complete mirrorimage ofone anotheron thepartwhichleadstothepossibilityofsymmetricalplacementand layoutabout thepart.Symmetricallayoutwillgivebestmatchingbetween thetwo buck devices.However we recommend that theinputsare keptseparateintothedevice.There are some compromises thathave tobe considered.Inthe case ofourexample we have used viastoroutetheVINB12 and VINB2 toallowthecloseplacementoftheinput capacitors.The switchnode must alsobe routedvialayer2on theboard.Here we have placeda number ofvias toreduceany additionalimpedance. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:LP8725

SNVS618G –DECEMBER 2009–REVISED MAY 2013 www.ti.com Figure20. Layout Scheme used on EvalBoard

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www.ti.com 18-Jul-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LP8725TLE-A/NOPB ACTIVE DSBGA YZR 30 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 V023 LP8725TLE-B/NOPB ACTIVE DSBGA YZR 30 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 V028 LP8725TLE-C/NOPB ACTIVE DSBGA YZR 30 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 V040 LP8725TLE-D/NOPB ACTIVE DSBGA YZR 30 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM V031 LP8725TLE/NOPB ACTIVE DSBGA YZR 30 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 8725 LP8725TLX-A/NOPB ACTIVE DSBGA YZR 30 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 V023 LP8725TLX-B/NOPB ACTIVE DSBGA YZR 30 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 V028 LP8725TLX-C/NOPB ACTIVE DSBGA YZR 30 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 V040 LP8725TLX-D/NOPB ACTIVE DSBGA YZR 30 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM V031 LP8725TLX/NOPB ACTIVE DSBGA YZR 30 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 8725 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

www.ti.com 18-Jul-2013 Addendum-Page 2 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8725TLE-A/NOPB DSBGA YZR 30 250 210.0 185.0 35.0 LP8725TLE-B/NOPB DSBGA YZR 30 250 210.0 185.0 35.0 LP8725TLE-C/NOPB DSBGA YZR 30 250 210.0 185.0 35.0 LP8725TLE-D/NOPB DSBGA YZR 30 250 210.0 185.0 35.0 LP8725TLE/NOPB DSBGA YZR 30 250 210.0 185.0 35.0 LP8725TLX-A/NOPB DSBGA YZR 30 3000 210.0 185.0 35.0 LP8725TLX-B/NOPB DSBGA YZR 30 3000 210.0 185.0 35.0 LP8725TLX-C/NOPB DSBGA YZR 30 3000 210.0 185.0 35.0 LP8725TLX-D/NOPB DSBGA YZR 30 3000 210.0 185.0 35.0 LP8725TLX/NOPB DSBGA YZR 30 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2013 Pack Materials-Page 2

www.ti.com TLA30XXX (Rev C) 0.600±0.075 D E A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. NOTES: 4215057/A 12/12 D: Max = E: Max = 2.99 mm, Min = 2.59 mm, Min = 2.93 mm 2.53 mm

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Summary

LP8725 Power Management Unit for Application or Multimedia Processors and Subsystems

Description

LP8725 Power Management Unit for Application or Multimedia Processors and Subsystems

Source title LP8725TLE-D/NOPB Datasheet(PDF) - Texas Instruments

Read LP8725TLE-D/NOPB online.

LP8725 TI1 | Alldatasheet

Document overview

Technical content

2.2 PF VINLILO2

2 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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APPLICATION INFORMATION

0 BUCK2_V2 Reg 0x0B[4-0]

1 BUCK2_V1 Reg 0x0A[4-0]

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LP8725TLE-D/NOPB specifications and overview.

More parts from the same family.