LP8720

LP8720 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

Features

■ 5 Low Noise LDO’s for up to 300 mA ■ One high-efficiency Synchronous Magnetic Buck Regulator, IOUT 400 mA High efficiency PFM mode @low IOUT Auto Mode PFM/PWM switch Low inductance 2.2 µH @ 2 MHz clock Dynamic Voltage Scale control ■ I2C-compatible interface for the controlling of internal registers ■ 20–bump 2.5 x 2.0 mm micro SMD package Key Specifications ■ Programmable Vout from 0.8V to 2.3V on DC/DC ■ Automatic soft start on DC/DC ■ 200 mV typ Dropout Voltage at 300 mA on LDO’s ■ 2% (typ) Output Voltage accuracy on LDO’s Typical Application Diagram 30067501 © 2009 National Semiconductor Corporation 300675 www.national.com LP8720 One Step-Down DC/DC and Five Linear Regulators with I2C Compatible Interface

Device Pin Diagram (Micro SMD 20) TOP VIEW 30067502 Package Marking Information 30067503

Ordering Information

Order Number Package Type Product Identification Supplied as LP8720TLE micro SMD 8720 250 Tape & Reel LP8720TLX micro SMD 8720 3000 Tape & Reel Upon request there will be available custom versions – customer can order own default voltages and own startup sequence. For more information please contact local National Semiconductor Corp. sales office. www.national.com 2 LP8720

Pin Number Name Type Description A4 VBATT P Battery Input for LDO1 and all internal circuitry. E4 VINB P Battery Input for Buck. A2 VIN1 P Battery Input for LDO2 and LDO3. D1 VIN2 P Battery Input for LDO4 and LDO5. B4 LDO1 A LDO1 Output. A3 LDO2 A LDO2 Output. A1 LDO3 A LDO3 Output. C1 LDO4 A LDO4 Output. E1 LDO5 A LDO5 Output. E3 SW A Buck Output. D2 FB A Buck Feedback. D4 GNDB G Power Ground for Buck. B1 GND G IC Ground. C4 SDA DI/O I2C-compatible Serial Interface Data Input/Output. Open Drain output, external pull up resistor is needed, typ 1.5 kΩ. If not in use then hard wire to GND. C3 SCL DI I2C-compatible Serial Interface Clock input. External pull up resistor is needed, typ 1.5 kΩ. If not in use then hard wire to GND. B3 IRQ_N DO Interrupt output, active LOW. Open Drain output, external pull up resistor is needed, typ 10 kΩ. If not in use then hard wire to GND or leave floating. E2 EN DI Enable. EN=LO standby. EN=HI power on. Internal pull down resistor 500 kΩ. If not in use then hard wire to VBATT. B2 DEFSEL DI Control input that sets the default voltages and startup sequence. Must be hard wired to BATT or GND or left floating (Hi-Z) for specific application. When DEFSEL= VBATT then setup 1 is used for default voltages and startup sequence. When DEFSEL= GND then setup 2 is used for default voltages and startup sequence. When DEFSEL= floating (Hi-Z) setup 3 is used for default voltages and startup sequence. C2 IDSEL DI Control input that sets the slave address for serial interface. Must be hard wired to BATT or GND or left floating (Hi-Z) for specific application. When IDSEL= VBATT then slave address is 7h’7F When IDSEL= floating (Hi-Z) then slave address is 7h’7C When IDSEL= GND then slave address is 7h’7D D3 DVS DI Dynamical Voltage Scaling. When DVS=HI then Buck voltage set BUCK_V1 is in use. When DVS=LO then Buck voltage set BUCK_V2 is in use. Buck voltage set BUCK_V1 should be higher than Buck voltage set BUCK_V2. If not in use then hard wire to VBATT or GND. A: Analog Pin D Digital Pin I Input Pin DI/O Digital Input/Output Pin G Ground O Output Pin P Power Connection 3 www.national.com LP8720

POWER-ON-RESET: After VBATT gets above POR higher threshold DEFSEL-pin and IDSEL-pin are read. Then all internal registers of LP8720 are reset to the default values and after that LP8720 goes to STANDBY mode. This process duration max is 500 µs. STANDBY: In STANDBY mode only serial interface is working and all other PMU functions are disabled – PMU is in low power condition. In STANDBY mode LP8720 can be (re)configured via Serial Interface. START UP: START UP sequence is defined by registers contents. START UP sequence starts: 1) If rising edge on EN-pin. 2) After cooling down from thermal shutdown event if EN=HI. It is not recommended to write to LP8720 registers during START UP. If doing so then current START UP sequence may become undefined. IDLE: PMU will enter into IDLE mode (normal operating mode) after end of START UP sequence. In IDLE mode all LDO’s and BUCK can be enabled/disabled via Serial Interface. Also in IDLE mode LP8720 can be (re) configured via Serial Interface. SHUT DOWN: SHUT DOWN sequence is “reverse order of start up sequence” and this is defined by registers contents. SHUT DOWN starts 1) If falling edge on EN-pin. 2) If temperature exceeds thermal shutdown threshold TSD +160°C. It is not recommended to write to LP8720 registers during SHUT DOWN. If doing so then current SHUT DOWN sequence may become undefined. 30067504 Additional Functions SLEEP: If sum of all LDO’s load currents and BUCK load current is no higher than 5mA then user can put PMU to SLEEP. In SLEEP PMU GND current is minimized. In SLEEP LDO’s and BUCK cannot be loaded with big current. There are 2 possibilities to use SLEEP: 1) Control via Serial Interface. 2) Control by DVS-pin. DVS: Dynamic Voltage Scaling allows using 2 voltage sets for BUCK. There are 2 possibilities to use DVS: 1) Control via Serial Interface. 2) Control by DVS-pin. INTERRUPT: If interrupt is not masked then PMU forces IRQ_N low if temperature crossed TSD_EW limit (thermal shutdown early warning) or/and thermal shutdown event took place. IRQ_N is released by reading Interrupt register. www.national.com 4 LP8720

POWER-ON AND POWER-OFF SEQUENCES Start Up Sequence if DEFSEL=VBATT or DEFSEL=Hi-Z 30067505 tBON 150 µs – Reference and bias turn ON. Min 100 µs max 200 µs. tS 25 µs – time step. Time step accuracy is defined by OSC frequency accuracy. Note 1 START UP and SHUT DOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDO’s and BUCK are enabled/disabled. Enabling /disabling process duration depends on loading conditions. Buck startup duration is 140 µs for no load. LDO startup duration is no more than 35 µs. For details please see LDO’s and BUCK electrical specifications. Note 3 LDO5 and BUCK are disabled. If LDO5 and/or BUCK are enabled via Serial Interface and startup sequence is not changed via Serial interface, then LDO5 and BUCK are disabled with no delay from falling edge on EN-pin. Note 4 At this time point registers 0x09 and 0x0C are reset to POR default values. Note 5 At this time point registers 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are reset to POR default values. 5 www.national.com LP8720

Start Up Sequence if DEFSEL=GND 30067506 tBON 150 µs – Reference and bias turn ON. Min 100 µs max 200 µs. tS 25 µs – time step. Time step accuracy is defined by OSC frequency accuracy. Note 1 START UP and SHUT DOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDO’s and BUCK are enabled/disabled. Enabling /disabling process duration depends on loading conditions. Buck startup duration is 140 µs for no load. LDO startup duration is no more than 35 µs. For details please see LDO’s and BUCK electrical specifications. Note 3 LDO1, LDO2, LDO4, LDO5 and BUCK are disabled. If LDO1, LDO2, LDO4, LDO5 and/or BUCK are enabled via Serial Interface and startup sequence is not changed via Serial interface, then LDO1, LDO2, LDO4, LDO5 and BUCK are disabled with no delay from falling edge on EN-pin. Note 4 At this time point registers 0x09 and 0x0C are reset to POR default values. Note 5 At this time point registers 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are reset to POR default values. www.national.com 6 LP8720

DEFSEL Start Up Sequence Shut Down Sequence VBATT LDO1, 2, 3, 4 enable same time. LDO5 and BUCK enable via Serial Interface. In reverse order of start up sequence. GND LDO3 enable. LDO1, 2, 4, 5 and BUCK enable via Serial Interface . In reverse order of start up sequence. Hi-Z LDO1, 2, 3, 4 enable same time. LDO5 and BUCK enable via Serial Interface. In reverse order of start up sequence. Default Output Voltages Output Max Current [mA] Default output Voltage [V] and default ON/OFF if EN=HI DEFSEL=VBATT DEFSEL=GND DEFSEL=Hi-Z LDO1 300 3.0 ON 3.0 OFF 2.8 ON LDO2 300 2.6 ON 3.0 OFF 2.6 ON LDO3 300 1.8 ON 2.6 ON 1.8 ON LDO4 300 1.0 ON 2.6 OFF 1.2 ON LDO5 300 3.3 OFF 3.3 OFF 3.3 OFF BUCK 400 1.0 OFF 1.2/1.31) OFF 1.2 OFF Note 1) BUCK voltage is 1.2V if DVS=LO and 1.3V if DVS=HI. 7 www.national.com LP8720

When IDSEL= VBATT then slave address is 7h’7F When IDSEL= floating (Hi-Z) then slave address is 7h’7C When IDSEL= GND then slave address is 7h’7D Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR default DEFSEL VBATT GND Hi-Z 0x00 GENERAL_ SETTINGS EXT_DVS_ CONTROL EXT_SLEEP_ CONTROL SHORT_ TIMESTEP 0000 0001 0000 0101 0000 0001 0x01 LDO1_ SETTINGS LDO1_ T[2] LDO1_ T[1] LDO1_ T[0] LDO1_ V[4] LDO1_ V[3] LDO1_ V[2] LDO1_ V[1] LDO1_ V[0] 0111 1101 1111 1101 0111 1001 0x02 LDO2_ SETTINGS LDO2_ T[2] LDO2_ T[1] LDO2_ T[0] LDO2_ V[4] LDO2_ V[3] LDO2_ V[2] LDO2_ V[1] LDO2_ V[0] 0111 0101 1111 1101 0111 0101 0x03 LDO3_ SETTINGS LDO3_ T[2] LDO3_ T[1] LDO3_ T[0] LDO3_ V[4] LDO3_ V[3] LDO3_ V[2] LDO3_ V[1] LDO3_ V[0] 0110 1100 0111 0101 0110 1100 0x04 LDO4_ SETTINGS LDO4_ T[2] LDO4_ T[1] LDO4_ T[0] LDO4_ V[4] LDO4_ V[3] LDO4_ V[2] LDO4_ V[1] LDO4_ V[0] 0110 0011 1111 1010 0110 0101 0x05 LDO5_ SETTINGS LDO5_ T[2] LDO5_ T[1] LDO5_ T[0] LDO5_ V[4] LDO5_ V[3] LDO5_ V[2] LDO5_ V[1] LDO5_ V[0] 1111 1111 1111 1111 1111 1111 0x06 BUCK_ SETTINGS1 BUCK_ T[2] BUCK_ T[1] BUCK_ T[0] BUCK_ V1[4] BUCK_ V1[3] BUCK_ V1[2] BUCK_ V1[1] BUCK_ V1[0] 1110 0101 1110 1011 1110 1001 0x07 BUCK_ SETTINGS2 FORCE_ PWM BUCK_ V2[4] BUCK_ V2[3] BUCK_ V2[2] BUCK_ V2[1] BUCK_ V2[0] 0000 0101 0000 1001 0000 1001 0x08 ENABLE_ BITS DVS_ V2/V1 SLEEP_ MODE BUCK_ EN LDO5_ EN LDO4_ EN LDO3_ EN LDO2_ EN LDO1_ EN 1000 1111 1000 0100 1000 1111 0x09 PULLDOWN_ BITS APU_ TSD BUCK_ PULLDOWN LDO5_ PULLDOWN LDO4_ PULLDOWN LDO3_ PULLDOWN LDO2_ PULLDOWN LDO1_ PULLDOWN 0011 1111 0011 1111 0011 1111 0x0A STATUS_ BITS TSD TSD_EW 0000 0000 0000 0000 0000 0000 0x0B INTERRUPT_ BITS *) TSD_ INT TSD_EW_ INT 0000 0000 0000 0000 0000 0000 0x0C INTERRUPT_ MASK *) TSD_ MASK TSD_EW_ MASK 0000 0011 0000 0011 0000 0011 *) Registers STATUS_BITS 0x0A and INTERRUPT_BITS 0x0B are read only. www.national.com 8 LP8720

EXT_DVS_CONTROL 1 – DVS-pin control: DVS=HI then BUCK_V1[4:0] DVS=LO then BUCK_V2[4:0] 0 – Serial interface control: DVS_V2/V1=1 then BUCK_V1[4:0] DVS_V2/V1=0 then BUCK_V2[4:0] EXT_SLEEP_CONTROL 1 – DVS-pin control: DVS=HI then normal DVS=LO then SLEEP 0 – Serial interface control: SLEEP_MODE=0 then normal SLEEP_MODE=1 then SLEEP SHORT_TIMESTEP 1 – time step tS=25 µs 0 – time step tS=50 µs By request time step 100 µs/200 µs is available. Registers 0x01 – 0x07 LDO1_V[4:0] LDO2_V[4:0] LDO3_V[4:0] LDO5_V[4:0] 00000 – 1.20V 00001 – 1.25V 00010 – 1.30V 00011 – 1.35V 00100 – 1.40V 00101 – 1.45V 00110 – 1.50V 00111 – 1.55V 01000 – 1.60V 01001 – 1.65V 01010 – 1.70V 01011 – 1.75V 01100 – 1.80V 01101 – 1.85V 01110 – 1.90V 01111 – 2.00V 10000 – 2.10V 10001 – 2.20V 10010 – 2.30V 10011 – 2.40V 10100 – 2.50V 10101 – 2.60V 10110 – 2.65V 10111 – 2.70V 11000 – 2.75V 11001 – 2.80V 11010 – 2.85V 11011 – 2.90V 11100 – 2.95V 11101 – 3.00V 11110 – 3.10V 11111 – 3.30V LDO4_V[4:0] 00000 – 0.80V 00001 – 0.85V 00010 – 0.90V 00011 – 1.00V 00100 – 1.10V 00101 – 1.20V 00110 – 1.25V 00111 – 1.30V 01000 – 1.35V 01001 – 1.40V 01010 – 1.45V 01011 – 1.50V 01100 – 1.55V 01101 – 1.60V 01110 – 1.65V 01111 – 1.70V 10000 – 1.75V 10001 – 1.80V 10010 – 1.85V 10011 – 1.90V 10100 – 2.00V 10101 – 2.10V 10110 – 2.20V 10111 – 2.30V 11000 – 2.40V 11001 – 2.50V 11010 – 2.60V 11011 – 2.65V 11100 – 2.70V 11101 – 2.75V 11110 – 2.80V 11111 – 2.85V BUCK_V1[4:0] BUCK_V2[4:0] 0000 External resistor divider 00001 – 0.80V 00010 – 0.85V 00011 – 0.90V 00100 – 0.95V 00101 – 1.00V 00110 – 1.05V 00111 – 1.10V 01000 – 1.15V 01001 – 1.20V 01010 – 1.25V 01011 – 1.30V 01100 – 1.35V 01101 – 1.40V 01110 – 1.45V 01111 – 1.50V 10000 – 1.55V 10001 – 1.60V 10010 – 1.65V 10011 – 1.70V 10100 – 1.75V 10101 – 1.80V 10110 – 1.85V 10111 – 1.90V 11000 – 1.95V 11001 – 2.00V 11010 – 2.05V 11011 – 2.10V 11100 – 2.15V 11101 – 2.20V 11110 – 2.25V 11111 – 2.30V BUCK_V1[4:0] should be higher (or equal) than BUCK_V2[4:0]. LDO1_T[2:0] LDO2_T[2:0] LDO3_T[2:0] LDO4_T[2:0] LDO5_T[2:0] BUCK_T[2:0] 000 – start up delay 0 001 – start up delay = 1 * time step tS 010 – start up delay = 2 * time step tS 011 – start up delay = 3 * time step tS 100 – start up delay = 4 * time step tS 101 – start up delay = 5 * time step tS 110 – start up delay = 6 * time step tS 111 – NO startup For proper startup operation “111 NO start up” should have corresponding bit in ENABLE_BITS register 0x08 set to 0 (disable). FORCE_PWM 1 – Buck is forced to work in PWM mode 0 – Buck works in automatic PFM/PWM selection mode. 9 www.national.com LP8720

LDO1_EN LDO2_EN LDO3_EN LDO4_EN LDO5_EN BUCK_EN In STANDBY mode 1 – During next START UP sequence will be enabled. 0 – During next START UP sequence will be NOT enabled. For proper operation output having “111 NO start up” should have corresponding enable bit 0 (disable). In IDLE mode the bit has immediate effect. 1 – Enable 0 – Disable SLEEP_MODE 1 – SLEEP 0 – normal This bit has effect only if EXT_SLEEP_CONTROL=0 (register 0x00) DVS_V2/V1 1 – buck voltage is BUCK_V1[4:0] 0 – buck voltage is BUCK_V2[4:0] This bit has effect only if EXT_DVS_CONTROL=0 (register 0x00) Register 0x09 LDO1_PULLDOWN LDO2_PULLDOWN LDO3_PULLDOWN LDO4_PULLDOWN LDO5_PULLDOWN BUCK_PULLDOWN 1 – Pull down enabled 0 – Pull down disabled APU_TSD This bit defines either to reset registers or not before LP8720 automatically starts START UP sequence form Thermal Shutdown after cooling down if EN-pin is High. 1 – No change to registers – registers content stays the same as before Thermal Shutdown. 0 – Reset registers to default values before START UP from Thermal Shutdown. Register 0x0A (Read Only) TSD 1 – device is in Thermal Shutdown. 0 – device is NOT in Thermal Shutdown . TSD_EW 1 – device temperature is higher than Thermal Shutdown Early Warning threshold. 0 – device temperature is lower than Thermal Shutdown Early Warning threshold. Register 0x0B (Read Only) TSD_INT 1 – Interrupt that was caused by Thermal Shutdown 0 – No Interrupt that was caused by Thermal Shutdown TSD_EW 1 – Interrupt that was caused by Thermal Shutdown Early Warning 0 – No Interrupt that was caused by Thermal Shutdown Early Warning Note 1: all reads from this register are destructive (all bits are reset to 0 after reading). Note 2: read form this register releases IRQ_N-pin (if was pushed down). Register 0x0C TSD_MASK 1 – TSD interrupt is masked 0 – TSD interrupt is NOT masked TSD_EW_MASK 1 – TSD_EW interrupt is masked 0 – TSD_EW interrupt is NOT masked www.national.com 10 LP8720

LP8720 has internal reference block creating all necessary references and biasing for all blocks. OSCILLATOR There is internal oscillator giving clock to the bucks and to logic control. VBATT=3.6V Parameter Typ Min Max Unit Oscillator frequency 2.0 1.9 2.1 MHz THERMAL SHUTDOWN The Thermal Shutdown (TSD) function monitors the chip tem- perature to protect the chip from temperature damage caused eg. by excessive power dissipation. The temperature moni- toring function has two threshold values TSD and TSD_EW that result in protective actions. When TSD_EW +125ºC is exceeded, then IRQ_N is set to low and “1” is written to TSD_EW bit in both STATUS register and in INTERRUPT register. If the temperature exceeds TSD +160ºC, then PMU initiates Emergency Shutdown. The POWER UP operation after Thermal Shutdown can be initiated only after the chip has cooled down to the +115ºC threshold Parameter Typ Unit TSD *) 160 °C TSD_EW *) 125 °C TSD_EW Hysteresis *) 10 °C *) Guaranteed by design. 11 www.national.com LP8720

Absolute Maximum Ratings (Note 1, Note If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VBATT = VINB, VBATT -0.3V to +6V VIN1, VIN2 -0.3V to VBATT+0.15V, max 6V All other pins -0.3V to VBATT+0.3V, max 6V Junction Temperature (TJ-MAX) 150ºC Storage Temperature -40 to 150ºC Maximum Continuous Power Dissipation PD-MAX (Note 3) 1.75 W ESD (Note 4) 2 kV HBM 200V MM Operating Ratings (Note 1, Note 2) VBATT = VINB, VBATT 2.7 to 4.5V VIN1, VIN2 2.5V to VBATT All input-only pins 0V to VBATT Junction Temperature (TJ) -40 to 125ºC Ambient Temperature (TA) -40 to 85ºC Maximum Power Dissipation (TA = 70ºC), (Note 5) 1.2 W Thermal Properties (Note 9) Junction-to-Ambient Thermal Resistance ( θJA) (Jedec Standard Thermal PCB) Micro SMD 20 45°C/W Current Consumption Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol Parameter Conditions Typ Limit UnitsMin Max IQ(STANDBY) Battery Standby Current VBATT = 3.6V 0.7 5 µA IQ(SLEEP) Battery Current in SLEEP Mode @ 0 load BUCK and all LDO’s enabled 190 270 µA IQ(SLEEP) Battery Current in SLEEP Mode @ 0 load LDO1, LDO2, LDO3 and LDO4 enabled 170 µA IQ(SLEEP) Battery Current in SLEEP Mode @ 0 load LDO3 enabled 100 150 µA IQ(SLEEP) Battery Current in SLEEP Mode @ 0 load LDO1 and BUCK enabled 100 µA IQ Battery Current @ 0 load BUCK and all LDO’s enabled 270 400 µA IQ Battery Current @ 0 load LDO1, LDO2, LDO3 and LDO4 enabled 230 µA IQ Battery Current @ 0 load LDO3 enabled 120 200 µA IQ Battery Current @ 0 load LDO1 and BUCK enabled 120 µA Power on Reset Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol Parameter Conditions Typ Limit UnitsMin Max VPOR_HI POR higher threshold VVBATT rising 2.2 2.0 2.4 V VPOR_LO POR lower threshold VVBATT falling (Note 7) 1.4 V www.national.com 12 LP8720

Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2µF, CVINB=10µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol Parameter Conditions Typ Limit UnitsMin Max Logic and Control Inputs VIL Input Low Level EN, SCL, SDA, DVS 0.4 V VIH Input High Level EN, SCL, SDA, DVS 1.2 V IIL Input Current All logic inputs -5 +5 µA RPD Pull Down Resistance From EN to GND 550 300 900 kΩ Logic and Control Outputs VOL Output Low Level IRQ_N, SDA, IOUT=2mA 0.4 V VOH Output High Level IRQ_N, SDA are Open drain outputs. NA µA 13 www.national.com LP8720

Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6, Note 10) Symbol Parameter Conditions Typ Limit UnitsMin Max VVOUT,PFM Output Voltage regulation in PFM mode relative to regulation in PWM mode (Note 7) 1.5 % VOUT Line Regulation 3.0V ≤ VIN ≤ 4.5V IOUT = 10 mA 0.14 %/V VOUT Load Regulation 100mA ≤ IOUT ≤ 300mA 0.09 %/mA ILIM_PWM Switch Peak Current Limit PWM Mode @ 400 mA 3.0V ≤ VIN ≤ 4.5V 900 500 mA RDSON(P) P channel FET on resistance VIN = 3.6V, ID = 100mA 310 500 mΩ RDSON(N) N channel FET on resistance 160 300 mΩ fOSC Internal Oscillator Frequency PWM Mode 2 1.9 1.7 2.1

2.3 MHz

Efficiency IOUT = 5mA, PFM-mode VOUT = 1.2V (Note 7) 88 %IOUT = 200mA, PWM-mode VOUT = 1.2V (Note 7) 90 TSTUP Start Up Time IOUT = 0, VOUT = 1.2V (Note 7) 140 µs Buck Output Voltage Programming in Register 0x06 and 0x07 BUCK1_Vx VOUT BUCK1_Vx VOUT 5h’00 External resistor divider 5h’10 1.55 5h’01 0.80 5h’11 1.60 5h’02 0.85 5h’12 1.65 5h’03 0.90 5h’13 1.70 5h’04 0.95 5h’14 1.75 5h’05 1.00 5h’15 1.80 5h’06 1.05 5h’16 1.85 5h’07 1.10 5h’17 1.90 5h’08 1.15 5h’18 1.95 5h’09 1.20 5h’19 2.00 5h’0A 1.25 5h’1A 2.05 5h’0B 1.30 5h’1B 2.10 5h’0C 1.35 5h’1C 2.15 5h’0D 1.40 5h’1D 2.20 5h’0E 1.45 5h’1E 2.25 5h’0F 1.50 5h’1F 2.30 www.national.com 14 LP8720

Output Voltage Selection Using External Resistor Divider Buck1 output voltage can be programmed via the selection of the external feedback resistor network. 30067508 VOUT will be adjusted to make the voltage at FB equal to 0.5V. The resistor from FB to ground R FB2 should be around 200 kΩ to keep the current drawn through the resistor network to a minimum but large enough that it is not susceptible to noise. With RFB2=200 kΩ and VFB at 0.5V, the current through the resistor feedback network will be 2.5 µA. The formula for output voltage selection is VOUT – output voltage VFB – feedback voltage (0.5V) For any out voltage greater than or equal to 0.8V a transfer function zero should be added by the addition of a capacitor C1. The formula for calculation of C1 is: For recommended component values see the table below. VOUT [V] RFB1 [kΩ] RFB2 [kΩ] C1 [pF] L [µH] COUT [µF] 1.0 200 200 18 2.2 10 1.2 280 200 12 2.2 10 1.4 360 200 10 2.2 10 1.5 360 180 10 2.2 10 1.6 440 200 8.2 2.2 10 1.85 540 200 6.8 2.2 10 15 www.national.com LP8720

LDO’s There are all together 5 LDO’s in LP8720 grouped as A-type LDO’s (LDO 2,3) D-type LDO’s (LDO 1,5) LO-type LDO (LDO4) The A-type LDO’s are optimized for supplying of analog loads and have ultra low noise (15 µVRMS) and excellent PSRR (70dB) performance. The D-type LDO’s are optimized for good dynamic perfor- mance to supply different fast changing (digital) loads. The LO-type LDO is optimized for low output voltage and for good dynamic performance to supply different fast changing (digital) loads. LDO1, 2, 3 and 5 Output Voltage Programming Data Code LDOx_V LDOx [V] Data Code LDOx_V LDOx [V] 5h’00 1.20 5h’10 2.10 5h’01 1.25 5h’11 2.20 5h’02 1.30 5h’12 2.30 5h’03 1.35 5h’13 2.40 5h’04 1.40 5h’14 2.50 5h’05 1.45 5h’15 2.60 5h’06 1.50 5h’16 2.65 5h’07 1.55 5h’17 2.70 5h’08 1.60 5h’18 2.75 5h’09 1.65 5h’19 2.80 5h’0A 1.70 5h’1A 2.85 5h’0B 1.75 5h’1B 2.90 5h’0C 1.80 5h’1C 2.95 5h’0D 1.85 5h’1D 3.00 5h’0E 1.90 5h’1E 3.10 5h’0F 2.00 5h’1F 3.30 All LDO’s can be programmed through serial interface for 32 different output voltage value, which are summarized in the in the “LDO Output Voltage Programming” tables below. At the PMU power on, LDO’s start up according to the select- ed startup sequence and the default voltages after start-up sequence depend on startup setup. See section Power-On and Power-Off Sequences for details. For stability all LDO’s have to have connected to output an external capacitor COUT with recommended value of 1 µF. It is important to select the type of capacitor which capacitance will in no case (voltage, temperature, etc) be outside of limits specified in the LDO electrical characteristics. LDO4 Output Voltage Programming Data Code LDO4_V LDO4 [V] Data Code LDO4_V LDO4 [V] 5h’00 0.80 5h’10 1.75 5h’01 0.85 5h’11 1.80 5h’02 0.90 5h’12 1.85 5h’03 1.00 5h’13 1.90 5h’04 1.10 5h’14 2.00 5h’05 1.20 5h’15 2.10 5h’06 1.25 5h’16 2.20 5h’07 1.30 5h’17 2.30 5h’08 1.35 5h’18 2.40 5h’09 1.40 5h’19 2.50 5h’0A 1.45 5h’1A 2.60 5h’0B 1.50 5h’1B 2.65 5h’0C 1.55 5h’1C 2.70 5h’0D 1.60 5h’1D 2.75 5h’0E 1.65 5h’1E 2.80 5h’0F 1.70 5h’1F 2.85 www.national.com 16 LP8720

A-Type LDO Electrical Characteristics Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol Parameter Conditions LDO# Typ Limit UnitsMin Max VOUT Output Voltage Accuracy IOUT = 1mA, VOUT = 2.85V 2,3 -2 +2 % -3 +3 % ISC Output Current Limit VOUT = 0V 2,3 600 mA VDO Dropout Voltage IOUT = IMAX (Note 8) 2,3 200 400 mV ΔVOUT Line Regulation VOUT + 0.5V ≤ VIN ≤ 4.5V IOUT = IMAX 2,3 1 mV Load Regulation 1mA ≤ IOUT ≤ IMAX 2,3 5 mV eN Output Noise Voltage 10Hz ≤ f ≤ 100kHz COUT = 1µF (Note 7) 2,3 15 µVRMS PSRR Power Supply Ripple Rejection Ratio f=10kHz, COUT = 1µF IOUT = 20mA (Note 7) 2,3 70 dB tSTART UP Start-Up Time from Shut- down COUT = 1µF, IOUT = IMAX (Note 7) 2,3 35 µs VTransient Start-Up Transient Overshoot COUT = 1µF, IOUT = IMAX (Note 7) 2,3 30 mV COUT External output capacitance for stability 2,3 1.0 0.5 20 µF D-Type and LO-Type LDO Electrical Characteristics Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol Parameter Conditions LDO# Typ Limit UnitsMin Max VOUT Output Voltage Accuracy IOUT = 1mA, VOUT = 2.85V 1,5 -2 +2 % -3 +3 % IOUT = 1mA, VOUT = 1.20V 4 -2 +2 % -3 +3 % IOUT = 1mA, VOUT = 2.60V 4 -3 +3 % -4 +4 % ISC Output Current Limit VOUT = 0V 1,4,5 600 mA VDO Dropout Voltage IOUT = IMAX (Note 8) 1,4,5 190 400 mV ΔVOUT Line Regulation VOUT + 0.5V ≤ VIN ≤ 4.5V IOUT = IMAX 1,4,5 2 mV Load Regulation 1mA ≤ IOUT ≤ IMAX 1,4,5 5 mV eN Output Noise Voltage 10Hz ≤ f ≤ 100kHz COUT = 1µF (Note 7) 1,4,5 100 µVRMS PSRR Power Supply Ripple Rejection Ratio f=10kHz, COUT = 1µF IOUT = 20mA (Note 7) 1,4,5 55 dB tSTART UP Start-Up Time from Shut- down COUT = 1µF, IOUT = IMAX (Note 7) 1,4,5 35 µs VTransient Start-Up Transient Overshoot COUT = 1µF, IOUT = IMAX (Note 7) 1,4,5 30 mV COUT External output capacitance for stability 1,4,5 1.0 0.5 20 µF 17 www.national.com LP8720

Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6, Note 7) Symbol Parameter Conditions Typ Limit UnitsMin Max fCLK Clock Frequency 400 kHz tBF Bus-Free Time between START and STOP 1.3 µs tHOLD Hold Time Repeated START Condition 0.6 µs tCLK-LP CLK Low Period 1.3 µs tCLK-HP CLK High Period 0.6 µs tSU Set-Up Time Repeated START Condition 0.6 µs tDATA-HOLD Data Hold Time 50 ns tDATA-SU Data Set-Up Time 100 ns tSU Set-Up Time for STOP Condition 0.6 µs tTRANS Maximum Pulse Width of Spikes that Must Be Suppressed by the Input Filter of Both DATA & CLK Signals 50 ns Notes to Electrical Characteristics Tables Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula P = (TJ – TA)/θJA, (eq. 1) where TJ is the junction temperature, T A is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The 1.75W rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150ºC for T J, 70ºC for TA, and 45°C/W for θJA. More power can be dissipated safely at ambient temperatures below 70°C. Less power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum power dissipation can be increased by 22mW for each degree below 70°C, and it must be de-rated by 22 mW for each degree above 70ºC. Note 4: The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is a 200 pF capacitor discharged directly into each pin, MIL-STD-883 3015.7. Note 5: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 1.2W rating for Micro SMD 20 appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125°C, for TJ, 70°C for TA, and 45° C/W for θJA into (eg. 1) above. More power can be dissipated at ambient temperatures below 70°C. Less power can be dissipated at ambient temperatures above 70°C. The maximum power dissipation for operation can be increased by 22mW for each degree below 70°C, and it must be de-rated by 22 mW for each degree above 70°C. Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 7: Guaranteed by design. Note 8: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Note 9: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 10: Guaranteed for output voltages no less than 1.0V www.national.com 18 LP8720

”ACKNOWLEDGE AFTER EVERY BYTE” RULE The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the trans- mitter an end of data by not-acknowledging (“negative ac- knowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. ADDRESSING TRANSFER FORMATS Each device on the bus has a unique slave address. The LP8720 operates as a slave device. Slave address is se- lectable by IDSEL-pin. When IDSEL= VBATT then slave address is 7h’7F When IDSEL= floating (Hi-Z) then slave address is 7h’7C When IDSEL= GND then slave address is 7h’7D Before any data is transmitted, the master transmits the ad- dress of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recog- nizes its address. The slave address is the first seven bits after a Start Condi- tion. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowl- edge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. CONTROL REGISTER WRITE CYCLE

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes the control register address will be incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition. CONTROL REGISTER READ CYCLE
• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. Address Mode Data Read <Start Condition> <Slave Address><r/w = ‘0’>[Ack] <Register Addr.>[Ack] <Repeated Start Condition> <Slave Address><r/w = ‘1’>[Ack] [Register Data]<Ack or NAck> … additional reads from subsequent register address possible <Stop Condition> Data Write <Start Condition> <Slave Address><r/w = ‘0’>[Ack] <Register Addr.>[Ack] <Register Data>[Ack] … additional writes to subsequent register address possible <Stop Condition> < > Data from master [ ] Data from slave www.national.com 20 LP8720

Physical Dimensions inches (millimeters) unless otherwise noted Micro SMD 20 Package X1 = 1.970 mm ±0.030 mm X2 = 2.466 mm ±0.030 mm X3 = 0.600 mm ±0.075 mm www.national.com 22 LP8720

23 www.national.com LP8720

LP8720 One Step-Down DC/DC and Five Linear Regulators with I2C Compatible Interface For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy PowerWise® Solutions www.national.com/powerwise Applications & Markets www.national.com/solutions Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless PowerWise® Design University www.national.com/training THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2009 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: support@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Technical Support Center Email: europe.support@nsc.com National Semiconductor Asia Pacific Technical Support Center Email: ap.support@nsc.com National Semiconductor Japan Technical Support Center Email: jpn.feedback@nsc.com www.national.com