LP8545SQX/NOPB

LP8545_14 TI1 | Alldatasheet

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 High-EfficiencyLEDBacklightDriverforNotebooks Check for Samples: LP8545 1FEATURES DESCRIPTION The LP8545 is a white LED driver with integrated 2• High-Voltage DC/DC Boost Converter with boost converter. It has six adjustable current sinksIntegrated FET with Four Switching Frequency which can be controlled by PWM input or with I2C-Options: 156/312/625/1250 kHz compatible serial interface.

• Configurable for Use with External FET for The boost converter has adaptive output voltageApplications Needing Higher Output Voltage control based on the LED driver voltages. This• 2.7V – 22V Input Voltage Range to Support feature minimizes the power consumption by1x… 5x Cell Li-Ion Batteries adjusting the voltage to lowest sufficient level in all
• Programmable PWM Resolution conditions. – 8 to 13 True Bit (Steady State) LED outputs have 8-bit current resolution and up to 13-bit PWM resolution with additional 1-3 bit dithering– Additional 1 to 3 Bits Using Dithering to achieve smooth and precise brightness control.During Brightness Changes Proprietary Phase Shift PWM control is used for LED• I2C and PWM Brightness Control outputs to reduce peak current from the boost
• PWM Output Frequency and LED Current Set converter, thus making the boost capacitors smaller. Through Resistors The Phase Shifting scheme also eliminates audible noise.• Optional Synchronization to Display VSYNC Signal Internal EEPROM is used for storing the configuration data. This makes it possible to have minimum• 6 LED Outputs with LED fault (Short/Open) external component count and make the solution veryDetection small.• Low Input Voltage, Over-Temperature, Over- Current Detection and Shutdown LP8545 has safety features which make it possible to detect LED outputs with open or short fault. As well• Minimum Number of External Components low input voltage and boost over-current conditions• WQFN 24-Pin Package, 4 x 4 x 0.8 mm are monitored and chip is turned off in case of these events. Thermal de-rating function prevents APPLICATIONS overheating of the device by reducing backlight brightness when set temperature has been reached.• Notebook and Netbook LCD Display LED Backlight LP8545 is available in TI's WQFN 24-pin package.
• LED Lighting Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2010–2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

L1 D12.7V /cb1 22V FILTER +5V input rail FSET 15 /ce9H VSYNC C OUTC IN 10 /ce9F 4.7 /ce9FC VLDO1 /ce9F VDDIO reference voltage VSYNC signal 120 k/c35 100 nF R ISET 1 /ce9F FAULTCan be left floating if not used GD 39 pF VIN R FSET VBATT 5.5V /cb1 22V 10V /cb1 40V, 180 mA /cb1 400 mA 10V /cb1 25V, 180 mA MCU LP8545 SW FB VLDO GNDs EN ISET VDDIO PWM SCLK SDA OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 L1 D15.5V /cb1 22V FILTER FSET 15 /ce9H VSYNC 10V /cb1 40V, 180 mA /cb1 400 mA C OUTC IN 10 /ce9F 4.7 /ce9F C VLDO 1 /ce9F VDDIO reference voltage VSYNC signal 120 k/c35 100 nF 1 /ce9F FAULTCan be left floating if not used GD 39 pF VIN R ISET R FSET VBATT LP8545 SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com Typical Application (1) Typical Application for Low Input Voltage (2) Note: Separate 5V rail to VLDO can be also used to improve efficiency for applications with higher battery voltage. No power sequencing requirements between VIN/VLDO and VBATT.

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Figure 1. Package Number RTW0024A Figure 2. Package Number RTW0024A

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com Pin Descriptions(1) Pin # Name Type Description

1 GND_SW G Boost switch ground

2 PWM A PWM dimming input. This pin must be connected to GND if not used. 3 ISET A Set resistor for LED current. This pin can be left floating if not used.

4 EN I Enable input pin

5 FSET A PWM frequency set resistor. This pin can be left floating if not used. 6 GD A Gate driver for external FET. If not used, can be left floating. 7 FAULT OD Fault indication output. If not used, can be left floating. PWM input pin then this pin can be connected to GND.

9 GND_S G Signal ground

10 SCLK I Serial clock. This pin must be connected to GND if not used. 11 SDA I/O Serial data. This pin must be connected to GND if not used.

12 OUT1 A Current sink output

13 OUT2 A Current sink output

14 OUT3 A Current sink output

15 GND_L G LED ground

16 OUT4 A Current sink output

17 OUT5 A Current sink output

18 OUT6 A Current sink output

19 VSYNC I VSYNC input. This pin must be connected to GND if not used. 20 FILTER A Low pass filter for PLL. This pin can be left floating if not used.

21 FB A Boost feedback input

22 VLDO P LDO output voltage. External 5V rail can be connected to this pin in low voltage application. 23 VIN P Input power supply up to 22V. If 2.7V ≤ VBATT < 5.5V (Typical Application for Low Input Voltage (2)) then external 5V rail must be used for VLDO and VIN. 24 SW A Boost switch. With external FET (typ. app. (3)) this pin acts as a current sense. (1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 ABSOLUTE MAXIMUM RATINGS (1)(2)(3) VIN -0.3V to +24.0V VLDO -0.3V to +6.0V Voltage on Logic Pins (VSYNC, PWM, EN, SCLK, SDA) -0.3V to +6.0V Voltage on Logic Pin (FAULT) -0.3V to VDDIO + 0.3V Voltage on Analog Pins (FILTER, GD, VDDIO, ISET, FSET) -0.3V to +6.0V Continuous Power Dissipation (4) Internally Limited Junction Temperature (TJ-MAX) 125°C Storage Temperature Range -65°C to +150°C Maximum Lead Temperature (Soldering) (5) ESD Rating (6) Human Body Model: 2 kV Machine Model: 200V Charged Device Model: 1 kV (1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. (3) All voltages are with respect to the potential at the GND pins. (4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). (5) For detailed soldering specifications and information, please refer to Texas Instrument AN1187: Leadless Leadframe Package (LLP). (6) Human Body Model, applicable standard JESD22-A114C. Machine Model, applicable standard JESD22- A115-A. Charged Device Model, applicable standard JESD22A-C101. RECOMMENDED OPERATING RATINGS (1)(2) Input Voltage Range (VIN) 5.5V to 22.0V typ. app. (1), (3) Input Voltage Range (VIN + VLDO) typ. app. (2) 4.5V to 5.5V VDDIO 1.65V to 5V V(OUT1...OUT6, SW, FB) 0V to 40V Junction Temperature (TJ) Range -30°C to +125°C Ambient Temperature (TA) Range (3) -30°C to +85°C (1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. (2) All voltages are with respect to the potential at the GND pins. (3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). THERMAL PROPERTIES Junction-to-Ambient Thermal Resistance (θJA), RTW Package (1) 35 to 50°C/W (1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LP8545

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (1)(2) Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating ambient temperature range (-30°C ≤ TA ≤ +85°C). Unless otherwise specified: VIN = 12.0V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF. RISET = 16 kΩ. (3) Symbol Parameter Condition Min Typ Max Units Standby Supply Current Internal LDO disabled 1 μA EN=L and PWM=L LDO enabled, boost enabled, no current going through LED outputs, Internal FET 4.0usedIIN 5 MHz PLL ClockNormal Mode Supply Current mA 10 MHz PLL Clock 4.8 20 MHz PLL Clock 6.0 40 MHz PLL Clock 8.4 fOSC Internal Oscillator Frequency -4 +4 %Accuracy -7 +7 VLDO Internal LDO Voltage 4.5 5.0 5.5 V ILDO Internal LDO External Loading 5.0 mA (1) All voltages are with respect to the potential at the GND pins. (2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. (3) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. BOOST CONVERTER ELECTRICAL CHARACTERISTICS Symbol Parameter Condition Min Typ Max Units RDSON Switch ON Resistance ISW = 0.5A 0.12 Ω VMAX Boost Maximum Output Voltage 40 V 9.0V ≤ VBATT, VOUT = 35V 450 Maximum Continuous LoadILOAD 6.0V ≤ VBATT, VOUT = 35V 300 mACurrent, Internal FET 3.0V ≤ VBATT, VOUT = 25V 180 9.0V ≤ VBATT, VOUT = 50V 320Maximum Continuous LoadILOAD mACurrent, External FET 6.0V ≤ VBATT, VOUT = 50V 190 VOUT/VIN Conversion Ratio 10 BOOST_FREQ = 00 156 BOOST_FREQ = 01 312fSW Switching Frequency kHzBOOST_FREQ = 10 625 BOOST_FREQ = 11 1250 VBOOST ≥ 38V VBOOST + 1.6VVOV Over-voltage Protection Voltage VVBOOST < 38V VBOOST + 4V tPULSE Switch Pulse Minimum Width no load 50 ns tSTARTUP Startup Time (1) 6 ms BOOST_IMAX[1:0] = 00 0.9 BOOST_IMAX[1:0] = 01 1.4IMAX SW Pin Current Limit ABOOST_IMAX[1:0] = 10 2.0 BOOST_IMAX[1:0] = 11 2.5 VGD Gate Driver Pin Voltage EN_EXT_FET = 1 0 VLDO V (1) Startup time is measured from the moment boost is activated until the VOUT crosses 90% of its target value.

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 LED DRIVER ELECTRICAL CHARACTERISTICS Symbol Parameter Condition Min Typ Max Units ILEAKAGE Leakage Current Outputs OUT1...OUT6, VOUT = 40V 0.1 1 µA EN_I_RES = 0, CURRENT[7:0] = FFh 30Maximum Source CurrentIMAX mAOUT1...OUT6 EN_I_RES = 1 50 Output Current Accuracy -3 +3IOUT Output current set to 23 mA, EN_I_RES = 1 %(1) -4 +4 IMATCH Matching (1) Output current set to 23 mA, EN_I_RES = 1 0.5 % fLED = 5 kHz, fPLL = 5 MHz 10 fLED = 10 kHz, fPLL = 5 MHz 9 fLED = 20 kHz, fPLL = 5 MHz 8PWM Output ResolutionPWMRES bits(2) fLED = 5 kHz, fPLL = 40 MHz 13 fLED = 10 kHz, fPLL = 40 MHz 12 fLED = 20 kHz, fPLL = 40 MHz 11 PWM_FREQ[4:0] = 00000b 600PLL clock 5 MHz fLED LED Switching Frequency (2) Hz PWM_FREQ[4:0] = 11111b 19.2kPLL clock 5 MHz Output current set to 20 mA 55 120 175 VSAT Saturation Voltage (3) mV Output current set to 30 mA 80 180 270 (1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT6), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN/AVG). The largest number of the two (worst case) is considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that some manufacturers have different definitions in use. (2) PWM output resolution and frequency depend on the PLL settings. Please see section “PWM Frequency Setting”for full description (3) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1V. PWM INTERFACE CHARACTERISTICS Symbol Parameter Condition Min Typ Max Units fPWM PWM Frequency Range 0.1 25 kHz tMIN_ON Minimum Pulse ON time 1 µs tMIN_OFF Minimum Pulse OFF time 1 Turn on delay from standby to PWM input active, EN pin rise from low totSTARTUP 6 msbacklight on high PWM input low time for turn off, slopeTSTBY Turn Off Delay 50 msdisabled fIN < 9.0 kHz 10 fIN < 4.5 kHz 11PWMRES PWM Input Resolution bitsfIN < 2.2 kHz 12 fIN < 1.1 kHz 13 UNDER-VOLTAGE PROTECTION Symbol Parameter Condition Min Typ Max Units UVLO[1:0] = 00 Disabled UVLO[1:0] = 01, falling 2.55 2.70 2.94 UVLO[1:0] = 01, rising 2.62 2.76 3.00 VUVLO VIN UVLO Threshold Voltage UVLO[1:0] = 10, falling 5.11 5.40 5.68 V UVLO[1:0] = 10, rising 5.38 5.70 5.98 UVLO[1:0] = 11, falling 7.75 8.10 8.45 UVLO[1:0] = 11, rising 8.36 8.73 9.20 Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LP8545

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com LOGIC INTERFACE CHARACTERISTICS Symbol Parameter Condition Min Typ Max Units Logic Input EN VIL Input Low Level 0.4 V VIH Input High Level 1.2 V II Input Current -1.0 1.0 µA Logic Input VSYNC VIL Input Low Level 0.4 V VIH Input High Level 2.2 V II Input Current -1.0 1.0 µA fVSYNC Frequency Range 58 60 55000 Hz Logic Input PWM VIL Input Low Level 0.4 V VIH Input High Level 2.2 V II Input Current -1.0 1.0 µA Logic Inputs SCL, SDA VIL Input Low Level 0.2xVDDIO V VIH Input High Level 0.8xVDDIO V II Input Current -1.0 1.0 µA Logic Outputs SDA, FAULT VOL Output Low Level IOUT = 3 mA (pull-up current) 0.3 0.5 V IL Output Leakage Current VOUT = 2.8V -1.0 1.0 µA

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 I2C SERIAL BUS TIMING PARAMETERS (SDA, SCLK) (1) Limit Symbol Parameter Units Min Max fSCLK Clock Frequency 400 kHz 1 Hold Time (repeated) START Condition 0.6 µs 2 Clock Low Time 1.3 µs

3 Clock High Time 600 ns

4 Setup Time for a Repeated START Condition 600 ns

5 Data Hold Time 50 ns

6 Data Setup Time 100 ns

7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns

9 Set-up Time for STOP condition 600 ns

10 Bus Free Time between a STOP and a START Condition 1.3 µs Capacitive Load Parameter for Each Bus LineCb 10 200 nsLoad of 1 pF corresponds to 1 ns. (1) Ensured by design. VDDIO = 1.65V to 5.5V. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LP8545

Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8.

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EN = L (VLDO low) or POR = H EN_BOOST = 1* TSD = H ~2 ms Delay BOOST STARTUP EN = H (pin) and BL_CTL = 1 or PWM = H (pin) BL_CTL = 0 and PWM = L EN_BOOST = 0* ~4 ms Delay NORMAL MODE EN_BOOST rising edge* * TSD = L VREF = 95% OK* EN = H (pin) VLDO ok LP8545 SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com MODES OF OPERATION RESET: In the RESET mode all the internal registers are reset to the default values. Reset is entered always VLDO voltage is low. EN pin is enable for the internal LDO. Power On Reset (POR) will activate during the chip startup or when the supply voltage VLDO fall below POR level. Once VLDO rises above POR level, POR will inactivate and the chip will continue to the STANDBY mode. STANDBY: The STANDBY mode is entered if the register bit BL_CTL is LOW and external PWM input is not active and POR is not active. This is the low-power consumption mode, when only internal 5V LDO is enabled. Registers can be written in this mode and the control bits are effective immediately after startup. STARTUP: When BL_CTL bit is written high or PWM signal is high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, Bias, Oscillator etc.). Internal EPROM and EEPROM are read in this mode. To ensure the correct oscillator initialization etc, a 2 ms delay is generated by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables the chip operation and STARTUP mode is entered until no thermal shutdown event is present. BOOST STARTUP:Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in low current PWM mode during the 4 ms delay generated by the state-machine. All LED outputs are off during the 4 ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH. NORMAL: During NORMAL mode the user controls the chip using the external PWM input or with Control Registers through I2C. The registers can be written in any sequence and any number of bits can be altered in a register in one write.

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 FUNCTIONAL DESCRIPTION LP8545 is a high voltage LED driver for medium sized LCD backlight applications. It includes high voltage boost converter which can be used either with internal FET or with external FET depending on boost output voltage requirements. Boost voltage automatically sets to the correct level needed to drive the LED strings. This is done by monitoring LED output voltage drop in real time. Six constant current sinks with PWM control are used for driving LEDs. Constant current value is set with EEPROM bits and with RISET resistor. Brightness (PWM) is controlled either with I2C register or with PWM input. PWM frequencies are set with EEPROM bits and with RFSET resistor. Special Phase-Shift PWM mode can be used to reduce boost output current peak, thus reducing output ripple, capacitor size and audible noise. With LP8545 it is possible to synchronize the PWM output frequency to VSYNC signal received from video processor. Internal PLL ensures that the PWM output clock is always synchronized to the VSYNC signal. Special dithering mode makes it possible to increase output resolution during fading between two brightness values and by this making the transition look very smooth with virtually no stepping. Transition slope time can be adjusted with EEPROM bits. Safety features include LED fault detection with open and short detection. LED fault detection will prevent system overheating in case of open in some of the LED strings. Chip internal temperature is constantly monitored and based on this LP8545 can reduce the brightness of the backlight to reduce thermal loading once certain trip point is reached. Threshold is programmable in EEPROM. If chip internal temperature reaches too high, the boost converter and LED outputs are completely turned off until the internal temperature has reached acceptable level. Boost converter is protected against too high load current and over-voltage. LP8545 notifies the system about the fault through I2C register and with FAULT pin. EEPROM programmable functions include:

• PWM frequencies
• Phase shift PWM mode
• LED constant current
• Boost output frequency
• Temperature thresholds
• Slope for brightness changes
• Dithering options
• PWM output resolution
• Boost control bits External components RISET and RFSET can also be used for selecting the output current and PWM frequencies. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LP8545

60 Hz EN_VSYNC

duty cycle measurement, internal timings such as slope time for output brightness changes. <PWM_RESOLUTION[1:0]> EEPROM Bits. correct PLL behavior during next startup. Figure 12. Principle of the Clock Generation

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5 MHz

0 0 PWM input pin duty cycle control. Default. 0 1 PWM input pin duty cycle control. and dither are effective in this mode. PWM input resolution is defined by the input PWM clock frequency. and dither are not effective in this mode. bypassed and this flow chart does not apply. Figure 13. PWM Calculation Data Flow is reduced if the temperature has reached the temperature limit set to the <TEMP_LIM[1:0]> EEPROM bits.

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com Resolution Selector Resolution selector takes the necessary MSB bits from the input data to match the output resolution. For example if 11-bit resolution is used for output, then 11 MSB bits are selected from the input. Dither bits are not taken into account for the output resolution. This is to make sure that in steady state condition, there is no dithering used for the output. Sloper Sloper makes the smooth transition from one brightness value to another. Slope time can be adjusted from 0 to 500 ms with <SLOPE[3:0]> EEPROM bits. The sloper output is 16-bit value. Dither With dithering the output resolution can be “artificially” increased during sloping from one brightness value to another. This way the brightness change steps are not visible to eye. Dithering can be from 0 to 3 bits, and is selected with <DITHER[1:0]> EEPROM bits. PWM Comparator The PWM counter clocks the PWM comparator based on the duty cycle value received from Dither block. Output of the PWM comparator controls directly the LED drivers. If PSPWM mode is used, then the signal to each LED output is delayed certain amount. Current Setting Maximum current of the LED outputs is controlled with CURRENT[7:0] EEPROM register bits linearly from 0 to 30 mA. If EN_I_RES = 1 the maximum LED output current can be scaled also with external resistor, RISET. RISET controls the LED current as follows:

• Default value for CURRENT[7:0] = 7Fh (127d). (1) Therefore the output current can be calculated as follows: Note: formula is only approximation for the actual current.
• E.g. If 16 kΩ RISET resistor is used, then the LED maximum current is 23 mA. (2) PWM Frequency Setting PWM frequency is selected with PWM_FREQ[4:0] EEPROM register. If PLL clock frequency multiplication is used, it will effect to the output PWM frequency as well. <PWM_RESOLUTION[1:0]> EEPROM bits will select the PLL output frequency and hence the PWM frequency and resolution. Below are listed PWM frequencies with <EN_VSYNC]> = 0. PWM resolution setting affects the PLL clock frequency (5 MHz… 40 MHz). Highlighted frequencies with boldface can be selected also with external resistor RFSET. To activate RFSET frequency selection the <EN_F_RES> EEPROM bit must be 1. PWM_RES[1:0] 00 01 10 11 PWM FREQ[4:0] 5 MHz 10 MHz 20 MHz 40 MHz Resolution (bits) 11111 19232 - - - 8 11110 16828 - - - 8 11101 14424 - - - 8 11100 12020 - - - 8 11011 9616 19232 - - 9 11010 7963 15927 - - 9 11001 6386 12771 - - 9 11000 4808 9616 19232 - 10 10111 4658 9316 18631 - 10

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 PWM_RES[1:0] 00 01 10 11 PWM FREQ[4:0] 5 MHz 10 MHz 20 MHz 40 MHz Resolution (bits) 10110 4508 9015 18030 - 10 10101 4357 8715 17429 - 10 10100 4207 8414 16828 - 10 10011 4057 8114 16227 - 10 10010 3907 7813 15626 - 10 10001 3756 7513 15025 - 10 10000 3606 7212 14424 - 10 01111 3456 6912 13823 - 10 01110 3306 6611 13222 - 10 01101 3155 6311 12621 - 10 01100 3005 6010 12020 - 10 01011 2855 5710 11419 - 10 01010 2705 5409 10818 - 10 01001 2554 5109 10217 - 10 01000 2404 4808 9616 19232 11 00111 2179 4357 8715 17429 11 00110 1953 3907 7813 15626 11 00101 1728 3456 6912 13823 11 00100 1503 3005 6010 12020 11 00011 1202 2404 4808 9616 12 00010 1052 2104 4207 8414 12 00001 826 1653 3306 6611 12 00000 601 1202 2404 4808 13 RFSET resistance values with corresponding PWM frequencies: PWM_RES[1 00 01 10 11 :0] RFSET (kΩ) 5 MHz Clock Resolution 10 MHz Resolution 20 MHz Resolution 40 MHz Resolution Clock Clock Clock 10...15 19232 8 19232 9 19232 10 19232 11 26...29 16828 8 15927 9 16227 10 17429 11 36...41 14424 8 12771 9 14424 10 15626 11 50...60 12020 8 9616 10 12020 10 12020 11 85...100 9616 9 8715 10 9616 11 9616 12 135...150 7963 9 7813 10 7813 11 8414 12 200...300 6386 9 6311 10 6010 11 6811 12 450... 4808 10 4808 11 4808 12 4808 13 Phase shift PWM Scheme Phase shift PWM scheme allows delaying the time when each LED output is active. When the LED output are not activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the ripple seen on the boost output and allows smaller output capacitors. Reduced ripple also reduces the output ceramic capacitor audible ringing. PSPWM scheme also increases the load frequency seen on boost output by x6 and therefore transfers the possible audible noise to so high frequency that human ear cannot hear it. Description of the PSPWM mode is seen on the following diagram. PSPWM mode is enabled by setting <EN_PSPWM> EEPROM bit to 1. Shift time is the delay between outputs and it is defined as 1 / (fPWM x 6). If the <EN_PSPWM> bit is 0, then the delay is 0 and all outputs are active simultaneously. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LP8545

Figure 14. Phase Shift PWM Mode During transition between two brightness (PWM) values special dithering scheme is used if the slope is enabled. It allows increased resolution and smaller average steps size. Dithering is not used in steady state condition. every 8th pulse is made 1 LSB longer to increase the average value by 1/8 of LSB. Figure 15. Sloper Operation

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Figure 16. Example of the Dithering, other voltages than normal input voltage are required. A complete EEPROM memory map is shown in Table 3. EEPROM NVM can be programmed or read by customer for bench validation. configuration is required, please contact the TI Sales Office for availability.

R S R /c36 Osc/ ramp gm VREF FB Boost output voltage adjustment Active Load Startup GD LP8545 SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com Boost Converter Operation The LP8545 boost DC/DC converter generates a 10… 40V supply voltage for the LEDs from 2.7… 22V input voltage. The output voltage can be controlled either with EEPROM register bits <VBOOST[4:0]> or automatic adaptive voltage control can be used. Higher output voltages can be achieved with external FET and by using resistor divider in the FB pin. GD pin operates as gate driver for the external FET in this case. To activate external FET gate driver, <EN_EXT_FET> bit in EEPROM register must be set to 1. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The topology of the magnetic boost converter is called CPM (current programmed mode) control, where the inductor current is measured and controlled with the feedback. Switching frequency is selectable between 156 kHz and 1.25 MHz with EEPROM bit <BOOST_FREQ[1:0]>. When <EN_BOOST> EEPROM register bit is set to 1, then boost will activate automatically when backlight is enabled. In adaptive mode the boost output voltage is adjusted automatically based on LED driver headroom voltage. Boost output voltage control step size is, in this case, 125 mV to ensure as small as possible driver headroom and high efficiency. Enabling the adaptive mode is done with <EN_ADAPT> EEPROM bit. If boost is started with adaptive mode enabled, then the initial boost output voltage value is defined with the <VBOOST[4:0]> EEPROM register bits in order to eliminate long output voltage iteration time when boost is started for the first time. The following figure shows the boost topology with the protection circuitry: Protection Three different protection schemes are implemented: 1. Over-voltage protection, limits the maximum output voltage. – Over-voltage protection limit changes dynamically based on output voltage setting. – Keeps the output below breakdown voltage. – Prevents boost operation if battery voltage is much higher than desired output. 2. Over-current protection, limits the maximum inductor current. 3. Duty cycle limiting. Manual Output Voltage Control User can control the boost output voltage with <VBOOST[4:0]> EEPROM register bits when adaptive mode is disabled. VBOOST[4:0] Voltage (typical) Bin Dec Volts 00000 0 10 00001 1 11 00010 2 12 00011 3 13

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Figure 17. Boost Adaptive Control Principle with PSPWM an external 5V line is used to power VLDO pin. enabled with <EN_LED_FAULT> EEPROM bit. Shorted or open LED string is detected.

• The corresponding LED string is taken out of boost adaptive control loop;
• Fault bits are set in the fault register to identify whether the fault has been open/short and how many strings are faulty; and
• Fault open-drain pin is pulled down. LED fault sensitivity can be adjusted with <LED_FAULT_THR[1:0]> EEPROM bits which sets the allowable variation between LED output voltage from 2.3V to 5.3V. Depending on application and how much variation there can be in normal operation between LED string forward voltages this setting can be adjusted. Fault is cleared by setting EN pin low or by reading the fault register. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LP8545

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com Under-Voltage Detection LP8545 has detection for too-low VIN voltage. Threshold level for the voltage is set with EEPROM register bits as seen in the following table: UVLO[1:0] Threshold (V)

00 OFF

01 2.7V 10 5.7V 11 8.7V When under voltage is detected the LED outputs and boost will shutdown, FAULT pin is pulled down and corresponding fault bit is set in fault register. LEDs and boost will start again when the voltage has increased above the threshold level. Hysteresis is implemented to threshold level to avoid continuous triggering of fault when threshold is reached. Fault is cleared by setting EN pin low or by reading the fault register. Over-Current Protection LP8545 has detection for too-high loading on the boost converter. When over-current fault is detected, the LP8545 will shut down. Fault is cleared by setting EN pin low or by reading the fault register. Device Thermal Regulation LP8545 has an internal temperature sensor which can be used to measure the junction temperature of the device and protect the device from overheating. During thermal regulation, LED PWM is reduced by 2% of full scale per °C whenever the temperature threshold is reached. Temperature regulation is enabled automatically when chip is enabled. 11-bit temperature value can be read from Temp MSB and Temp LSB registers, MSB should be read first. Temperature limit can be programmed in EEPROM as shown in the following table. Thermal regulation function does not generate fault signal. TEMP_LIM[1:0] Over-Temp Limit (°C) If the LP8545 reaches thermal shutdown temperature (150°C ) the LED outputs and boost will shut down to protect it from damage. Also the fault pin will be pulled down to indicate the fault state. Device will activate again when temperature drops below 130°C degrees. Fault is cleared by setting EN pin low or by reading the fault register.

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Figure 20. Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle. transferred, and the acknowledge signal sent by the receiving device. signal after every byte received. master), but the SDA line is not pulled down. combined with data direction bit. Slave address is 2Ch as 7-bit or 58h for write and 59h for read in 8-bit format. should send an acknowledge signal on the SDA line, once it recognizes its address. on the bit sent after the slave address — the eighth bit. R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. Figure 21. I2C Chip Address

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• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes the control register address will be incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition. Control Register Read Cycle
• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

Table 1. Data Read and Write Cycles

NAS '0'Slave Address (7 bits) Control Register Add. (8 bits)A A Data- Data (8 bits) P R/W Data transfered, byte + Ack/NAck Sr Slave Address (7 bits) '1' A R/W Direction of the transfer will change at this point From Master to Slave From Slave to Master A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION Sr - REPEATED START CONDITION Register Read Format NA - ACKNOWLEDGE (SDA High) S '0'Slave Address (7 bits) Control Register Add. (8 bits)A A A Register Data (8 bits) P R/W From Master to Slave From Slave to Master A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION Data transfered, byte + AckRegister Write Format LP8545 SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com <>Data from master [ ] Data from slave Register Read and Write Detail

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ISAT > x (VOUT /cb1 VIN) VOUT VIN Where D = Where IRIPPLE = (2 x L x f) (VOUT /cb1 VIN) (VOUT ) + IRIPPLE IOUTMAX /c27/cb6 LP8545 www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 APPLICATIONS INFORMATION Recommended External Components Inductor Selection There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. Shielded inductors radiate less noise and should be preferred. The saturation current should be greater than the sum of the maximum load current and the worst case average to peak inductor current. The equation below shows the worst case conditions.

• IRIPPLE: Average to peak inductor current
• IOUTMAX: Maximum load current
• VIN: Maximum input voltage in application
• L: Min inductor value including worst case tolerances
• f: Minimum switching frequency
• D: Duty cycle for CCM Operation
• VOUT: Output voltage (3) Example using above equations:
• VIN = 12V
• VOUT = 38V
• IOUT = 400 mA
• L = 15 µH − 20% = 12 µH
• f = 1.25 MHz
• ISAT = 1.6A As a result the inductor should be selected according to the ISAT. A more conservative and recommended approach is to choose an inductor that has a saturation current rating greater than the maximum current limit of 2.5A. A 15 μH inductor with a saturation current rating of 2.5A is recommended for most applications. The inductor’s resistance should be less than 300 mΩ for good efficiency. For high efficiency choose an inductor with high frequency core material such as ferrite to reduce core losses. To minimize radiated noise, use shielded core inductor. Inductor should be placed as close to the SW pin and the IC as possible. Special care should be used when designing the PCB layout to minimize radiated noise and to get good performance from the boost converter. Output Capacitor A ceramic capacitor with 50V voltage rating or higher is recommended for the output capacitor. The DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance value selection. For light loads a 4.7 µF capacitor is sufficient. Effectively the capacitance should be 4 µF for < 150 mA loads. For maximum output voltage/current 10 µF capacitor (or two 4.7 µF capacitors) is recommended to minimize the output ripple. For high output voltage (55V) application 100V voltage rating capacitors should be used. 2 x 2.2 µF capacitors are enough. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LP8545

A 1µF ceramic capacitor with 10V voltage rating is recommended for the LDO capacitor. recovery times cause the efficiency and the load regulation to suffer. time is desired, please contact TI representative for guidance. Table 2. Register Map

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Table 3. EEPROM Memory Map BRT 7:0 R/W Backlight PWM 8-bit linear control.

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com Fault Address 02h Reset value 0000 0000b Fault register 7 6 5 4 3 2 1 0 OPEN SHORT 2_CHANNELS 1_CHANNEL BL_FAULT OCP TSD UVLO Name Bit Access Description OPEN 7 R LED open fault detection 0 = No fault 1 = LED open fault detected. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. SHORT 6 R LED short fault detection 0 = No fault 1 = LED short fault detected. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. 2_CHANNELS 5 R LED fault detection 0 = No fault 1 = 2 or more channels have generated either short or open fault. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. 1_CHANNEL 4 R LED fault detection 0 = No fault 1 = 1 channel has generated either short or open fault. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. BL_FAULT 3 R LED fault detection 0 = No fault 1 = LED fault detected. Generated with OR function of all LED faults. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. OCP 2 R Over current protection 0 = No fault 1 = Over current detected in boost output. OCP detection block monitors the boost output and if the boost output has been too low for more than 50 ms it will generate OCP fault and disable the boost. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. After clearing the fault boost will startup again. TSD 1 R Thermal shutdown 0 = No fault 1 = Thermal fault generated, 150°C reached. Boost converted and LED outputs will be disabled until the temperature has dropped down to 130°C. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. UVLO 0 R Under voltage detection 0 = No fault 1 = Under voltage detected in VIN pin. Boost converted and LED outputs will be disabled until VIN voltage is above the threshold voltage. Threshold voltage is set with register 02h or setting EN pin low.

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 Identification Address 03h Reset value 1111 1100b Identification register 7 6 5 4 3 2 1 0 PANEL MFG[3:0] REV[2:0] Name Bit Access Description PANEL 7 R Panel ID code MFG 6:3 R Manufacturer ID code REV 2:0 R Revision ID code Direct Control Address 04h Reset value 0000 0000b Direct Control register 7 6 5 4 3 2 1 0 OUT[6:1] Name Bit Access Description OUT 5:0 R/W Direct control of the LED outputs 0 = Normal operation. LED output are controlled with PWM. 1 = LED output is forced to 100% PWM. Temp MSB Address 05h Reset value 0000 0000b Temp MSB register 7 6 5 4 3 2 1 0 TEMP[10:3] Name Bit Access Description TEMP 7:0 R Device internal temperature sensor reading first 8 MSB. MSB must be read before LSB, because reading of MSB register latches the data. Temp LSB Address 06h Reset value 0000 0000b Temp LSB register 7 6 5 4 3 2 1 0 TEMP[2:0] Name Bit Access Description TEMP 7:5 R Device internal temperature sensor reading last 3 LSB. MSB must be read before LSB, because reading of MSB register latches the data. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: LP8545

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com EEPROM Control Address 72h Reset value 0000 0000b EEPROM Control register 7 6 5 4 3 2 1 0 EE_READY EE_INIT EE_PROG EE_READ Name Bit Access Description EE_READY 7 R EEPROM ready 0 = EEPROM programming or read in progress 1 = EEPROM ready, not busy EE_INIT 2 R/W EEPROM initialization bit. This bit must be written 1 before EEPROM read or programming. EE_PROG 1 R/W EEPROM programming. 0 = Normal operation 1 = Start the EEPROM programming sequence. EE_INIT must be written 1 before EEPROM programming can be started. Programs data currently in the EEPROM registers to non volatile memory (NVM). Programming sequence takes about 200 ms. Programming voltage is generated inside the chip. EE_READ 0 R/W EEPROM read 0 = Normal operation 1 = Reads the data from NVM to the EEPROM registers. Can be used to restore default values if EEPROM registers are changed during testing. Programming sequence (program data permanently from registers to NVM): 1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h) 2. Write data to EEPROM registers (address A0h… A7h). 3. Write EE_INIT to 1 in address 72h. (04h to address 72h). 4. Write EE_PROG to 1 and EE_INIT to 0 in address 72h. (02h to address 72h). 5. Wait 200 ms. 6. Write EE_PROG to 0 in address 72h. (00h to address 72h). Read sequence (load data from NVM to registers): 1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h). 2. Write EE_INIT to 1 in address 72h. (04h to address 72h). 3. Write EE_READ to 1 and EE_INIT to 0 in address 72h. (01h to address 72h). 4. Wait 200 ms. 5. Write EE_READ to 0 in address 72h. (00h to address 72h). Data written to EEPROM registers is effective immediately even if the EEPROM programming sequence has not been done. When power is turned off, the device will, however, lose the data if it is not programmed to the NVM. During startup, the device automatically loads the data from NVM to registers. NOTE EEPROM NVM can be programmed or read by customer for bench validation. Programming for production devices should be done in TI production test, where appropriate checks will be performed to confirm EEPROM validity. Writing to EEPROM Control register of production devices (for burning or reading EEPROM) is not recommended. If special EEPROM configuration is required, please contact the TI Sales Office for availability.

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 EEPROM Bit Explanations EEPROM Default Values ADDR LP8545SQX A0H 0111 1111 A1H 1011 0101 A2H 1010 1111 A3H 0111 1011 A4H 0010 1000 A5H 1100 1111 A6H 0110 0100 A7H 0010 1101 EEPROM Address 0 Address A0h EEPROM ADDRESS 0 register 7 6 5 4 3 2 1 0 CURRENT[7:0] Name Bit Access Description CURRENT 7:0 R/W Backlight current adjustment. If EN_I_RES = 0 the maximum backlight current is defined only with these bits as described below. If EN_I_RES = 1, then the external resistor connected to ISET pin also scales the LED current. With 16 kΩ resistor and CURRENT set to 7FH the output current is then 23 mA. EN_I_RES = 0 EN_I_RES = 1 0000 0000 0 mA 0 mA 0000 0001 0.12 mA (1/255) x 600 x 1.23V/RISET 0000 0010 0.24 mA (2/255) x 600 x 1.23V/RISET 0111 1111 (default) 15.00 mA (127/255) x 600 x 1.23V/RISET 1111 1101 29.76 mA (253/255) x 600 x 1.23V/RISET 1111 1110 29.88 mA (254/255) x 600 x 1.23V/RISET 1111 1111 30.00 mA (255/255) x 600 x 1.23V/RISET EEPROM Address 1 Address A1h EEPROM ADDRESS 1 register 7 6 5 4 3 2 1 0 BOOST_FREQ[1:0] EN_LED_FAULT TEMP_LIM[1:0] SLOPE[2:0] Name Bit Access Description BOOST_FREQ 7:6 R/W Boost Converter Switch Frequency 00 = 156 kHz 01 = 312 kHz 10 = 625 kHz 11 = 1250 kHz EN_LED_FAULT 5 R/W Enable LED fault detection 0 = LED fault detection disabled 1 = LED fault detection enabled Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: LP8545

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com EEPROM ADDRESS 1 register TEMP_LIM 4:3 R/W Thermal deration function temperature threshold 00 = thermal deration function disabled 01 = 110°C 10 = 120°C 11 = 130°C SLOPE 2:0 R/W Slope time for brightness change 000 = Slope function disabled, immediate brightness change 001 = 50 ms 010 = 75 ms 011 = 100 ms 100 = 150 ms 101 = 200 ms 110 = 300 ms 111 = 500 ms EEPROM Address 2 Address A2h EEPROM ADDRESS 2 register 7 6 5 4 3 2 1 0 ADAPTIVE_SPEED[1:0] ADV_SLO EN_EXT_FET EN_ADAPT EN_BOOST BOOST_IMAX[1:0] PE Name Bit Access Description ADAPTIVE 7 R/W Boost converter adaptive control speed adjustment SPEED[1] 0 = Normal mode 1 = Adaptive mode optimized for light loads. Activating this helps the voltage droop with light loads during boost / backlight startup. ADAPTIVE 6 R/W Boost converter adaptive control speed adjustment SPEED[0] 0 = Adjust boost once for each phase shift cycle or normal PWM cycle 1 = Adjust boost every 16th phase shift cycle or normal PWM cycle ADV_SLOPE 5 R/W Advanced slope 0 = Advanced slope is disabled 1 = Use advanced slope for brightness change to make brightness changes smooth for eye EN_EXT_FET 4 R/W Enable external FET gate driver 0 = Internal FET used 1 = External FET used and GD pin used for driving the external FET gate EN_ADAPT 3 R/W Enable boost converter adaptive mode 0 = adaptive mode disabled, boost converter output voltage is set with VBOOST EEPROM register bits 1 = adaptive mode enabled. Boost converter startup voltage is set with VBOOST EEPROM register bits, and after startup voltage is reached the boost converter will adapt to the highest LED string VF. LED driver output headroom is set with DRV_HEADR EEPROM control bits. EN_BOOST 2 R/W Enable boost converter 0 = boost is disabled 1 = boost is enabled and will turn on automatically when backlight is enabled

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www.ti.com SNVS635D –APRIL 2010–REVISED DECEMBER 2013 EEPROM ADDRESS 2 register BOOST_IMAX 1:0 R/W Boost converter inductor maximum current 00 = 0.9A 01 = 1.4A 10 = 2.0A 11 = 2.5A (recommended) EEPROM Address 3 Address A3h EEPROM ADDRESS 3 register 7 6 5 4 3 2 1 0 UVLO[1:0] EN_PSPWM PWM_FREQ[4:0] Name Bit Access Description UVLO 7:6 R/W 00 = Disabled 01 = 2.7V 10 = 6V 11 = 9V EN_PSPWM 5 R/W Enable phase shift PWM scheme 0 = phase shift PWM disabled, normal PWM mode used 1 = phase shift PWM enabled PWM_FREQ 4:0 R/W PWM output frequency setting. See PWM Frequency Setting for full description of selectable PWM frequencies. EEPROM Address 4 Address A4h EEPROM ADDRESS 4 register 7 6 5 4 3 2 1 0 PWM_RESOLUTION[1:0] EN_I_RES LED_FAULT_THR[1:0] DRV_HEADR[2:0] Name Bit Access Description PWM 7:6 R/W PWM output resolution selection. Actual resolution depends also on the output RESOLUTION frequency. See PWM Frequency Setting for full description. EN_I_RES 5 R/W Enable LED current set resistor 0 = Resistor is disabled and current is set only with CURRENT EEPROM register bits 1 = Enable LED current set resistor. LED current is defined by the RISET resistor and the CURRENT EEPROM register bits. LED_FAULT_TH 4:3 R/W LED fault detector thresholds. VSAT is the saturation voltage of the driver, typically R 200 mV. 00 = 2.3V 01 = 3.3V 10 = 4.3V 11 = 5.3V Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: LP8545

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com EEPROM ADDRESS 4 register DRV_HEADR 2:0 R/W LED output driver headroom control. VSAT is the saturation voltage of the driver, typically 200 mV. 000 = VSAT + 125 mV 001 = VSAT + 250 mV 010 = VSAT + 375 mV 011 = VSAT + 500 mV 100 = VSAT + 625 mV 101 = VSAT + 750 mV 110 = VSAT + 875 mV 111 = VSAT + 1000 mV EEPROM Address 5 Address A5h EEPROM ADDRESS 5 register 7 6 5 4 3 2 1 0 EN_VSYNC DITHER[1:0] VBOOST[4:0] Name Bit Access Description EN_VSYNC 7 R/W Enable VSYNC function 0 = VSYNC input disabled 1 = VSYNC input enabled. VSYNC signal is used by the internal PLL to generate PWM output and boost frequency. DITHER 6:5 R/W Dither function controls 00 = Dither function disabled 01 = 1-bit dither used for output PWM transitions 10 = 2-bit dither used for output PWM transitions 11 = 3-bit dither used for output PWM transitions VBOOST 4:0 R/W Boost voltage control from 10V to 40V with 1V step (without FB resistor divider). If adaptive boost control is enabled, this sets the initial start voltage for the boost converter. If adaptive mode is disabled, this will directly set the output voltage of the boost converter. 0 0000 = 10V 0 0001 = 11V 0 0010 = 12V ... 1 1101 = 39V 1 1110 = 40V 1 1111 = 40V EEPROM Address 6 Address A6h EEPROM ADDRESS 6 register 7 6 5 4 3 2 1 0 PLL[12:5] Name Bit Access Description PLL 7:0 R/W 13-bit counter value for PLL, 8 MSB bits. PLL[12:0] bits are used when en_vsync = 1. See table below for PLL value calculation.

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table below for PLL value calculation. PWM Frequency Setting for full description of the PWM frequencies. ignored to remove constant switching between two values. Table 4. PLL Value Calculation PLL frequency is set by PWM_RESOLUTION[1:0] bits.

SNVS635D –APRIL 2010–REVISED DECEMBER 2013 www.ti.com

REVISION HISTORY

Changes from Revision C (March 2013) to Revision D Page

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www.ti.com 18-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LP8545SQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L8545SQ LP8545SQE/NOPB ACTIVE WQFN RTW 24 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -30 to 85 L8545SQ LP8545SQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -30 to 85 L8545SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 18-Nov-2013 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Nov-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8545SQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LP8545SQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0 LP8545SQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Nov-2013 Pack Materials-Page 2

www.ti.com SQA24A (Rev B)

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