LP1071 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2005. All rights reserved. PRELIMINARY Freescale Semiconductor Advance Information This document contains information on a new product. Specifications and information herein are subject to change without notice. Document Number: LP1071 Rev. 0.5, 12/2005
1 Introduction
1.1 The LP1070 Family
Freescale Semiconductor’s 802.11 LP1070 family consists of high-performance, highly optimized PHY and MAC baseband Wireless LAN processors that fully implement the IEEE 802.11a, 802.11b and 802.11g PHY standards. These baseband processors are poised to revolutionize the Wireless LAN industry by setting new standards for power consumption, size, cost and performance. The LP1070 family is based on Freescale's proprietary Wireless Broadband Signal Processor™ (WBSP™), an innovative and revolutionary receiver architecture that significantly reduces size and power consumption while providing maximum flexibility to support multiple wireless standards with no additional overhead. In addition to their superior performance and ultra low power consumption, the LP1070 processors provide the customers with the flexibility to tailor the chip characteristics to their needs. With software control, the LP1071 802.11a/b/g Baseband System Solution
Contents
11 Appendix: Comparison of LP1071 and
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terminal manufacturers can tune the chip performance to get the exact balance they opt for when it comes to power consumption and performance.
1.2 General Description
The high-performance LP1071 baseband processor integrates the IEEE 802.11a/b/g PHY and full MAC functionality with the industry’s smallest package and the lowest power consumption compared to any baseband processor in the market. The LP1071 was designed to target embedded devices and small form factor SDIO WLAN devices. Its support for SDIO host interface combined with its ultra low power consumption and small size make it the optimal solution for mobile devices. It has been designed with a generic RF interface that lets it interface with virtually any RF components in the market. It has been fully tested to interface with RF solutions from Maxim and Airoha, thus providing terminal manufacturers with added flexibility in selecting the most appropriate RF parts based on their application and form factor. The LP1071’s integrated ADC and DAC reduce the terminal manufacturers' bill of material and overall system cost. The integrated internal memory eliminates the need for external MAC memory, further reducing cost and saving valuable board space for small form factor devices. The LP1071 also provides the highest level of WLAN security by fully supporting WPA and AES.
1.3 Feature Highlights
Full compliance with 802.11a/b/g Ultra low power consumption, maximizing ba ttery life and minimizing heat dissipation Ultra small package: 9.0 x 9.0 x 1.0 (max) mm Fully embedded ARM7TDMI® micr oprocessor for no load on the host processor, leading to maximum flexibility in supporting different host platforms Implementations of 802.11e Draft, for support of Quality of Service (QoS) real-time applications 802.11i support, including WPA and AES, for enhanced security Automatic power management to reduce power consumption On-chip ADC and DAC to reduce sy stem BOM and save on board area On-Chip PLL for clock generation On-chip ROM/RAM eliminating the need for external MAC memory Direct memory access (DMA) to reduce CPU utilization High throughput achieved using DMA Support of SDIO host interface Serial EEPROM interface for in itialization and device booting Eight General Purpose I/O (GPI O) pins for added flexibility UART interface to support diagnostic tools and general data transfer JTAG Interface for testing and debugging Hardware engines for WEP, TKIP and AES support for less processor load
tested with RF from Maxim and Airoha. between competing performance metrics.
2 Specifications
Table 1. Specifications
8 GPIO pins
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3 Functional Description
Figure 1 is a functional block diagram of the LP1071, which is divided into three main subsystems. Figure 1. Functional Block Diagram
3.1 Embedded Processor Subsystem
3.1.1 UART
Table 1. Specifications (continued)
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3.1.2 JTAG
3.1.3 Serial EEPROM Interface
The LP1071 supports an external serial EEPROM for storing the boot loader, MAC address, calibration data and any other vendor-specific data. The LP1071 supports serial EEPROMs of sizes from 8 Kbit (organized as 1024 entries of 8 bits each, or 1024 x 8) up to 512 Kbit (organized as 65,536 x 8). Serial EEPROMs from the following vendors have been tested and verified to work with the LP1071: ATMEL (http://www.atmel.com) ST Microelectronics (http://www.st.com) Microchip Technology (http://www.microchip.com) Catalyst Semiconductor (h ttp://www.catsemi.com) Integrated Silicon Solutions, Inc. (http://www.issi.com) The EEPROM is supported through GPIOs. There is no dedicated hardware to support either I 2C or SPI serial EEPROMs. The operating frequency of the serial EEPROM port is 400 kHz with a supply voltage of 3.0 V .
3.1.4 GPIO
To support vendor-specific needs, the LP1071 provides eight bi-directional General Purpose Input Output (GPIO) pins. Each pin can be independently configured as an input, output or an interrupt source. On reset, the GPIOs default as inputs, i.e. output drivers enables will be inactive.
3.1.5 RMB Registers
This block contains all the reset logic for both CPUs contained in the BRC and chip-wide reset control. It also defines controls for memory address re-mapping.
3.1.6 Watchdog
3.1.7 Interrupt Controller
3.1.8 SDIO Registers
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3.1.9 Clock Control
3.1.10 Clock Gating
This block contains all the control logic required to gate individual sub-block clocks.
3.2 Media Access Control (MAC) Subsystem
3.2.1 Protocol Accelerator Subsystem (PAS)
The main function of the Protocol Accelerator Subsystem is to provide hardware acceleration functions for the MAC Software to perform the time critical aspects of the 802.11 protocol. The PAS contains the following: Shared Memory Controller – provides arbitrat ed access to the shared memory (MAC memory) WEP Hardware Engine AES Hardware Engine 802.11 Protocol Accelerator – for suppor t of time-critical MAC functions Generic Host Interface
3.2.2 AES Block
The contents of the AES block are: AES encryption/decryption core that performs AES encryption/decryption of a 128-bit block. Offset Codebook (OCB) mode encipher/deciphe r wrapper that performs OCB mode key generation for the AES core. DMA controller and Shared Memory Interface that controls the reading/writing of data blocks from/to the PAS shared memory controller. Control Registers, used to confi gure the operation of the AES block.
3.2.3 WEP Block
3.3 PHY Subsystem
3.4 Analog Front End (AFE)
Digital-to-Analog Converters (DACs) as given in Table 2.
3.4.1 I/Q ADC
I/Q ADC specifications are shown in Table 3. Table 2. AFE Components whose input is the differential signal from the RF (RX mode). differential signal for the RF (TX mode). Table 3. I/Q ADC Specifications
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3.4.2 I/Q DAC
I/Q DAC specifications are shown in Table 4.
3.4.3 RSSI ADC
RSSI ADC specifications are shown in Table 5. Table 4. I/Q DAC 1 See Analog input pin for definition of I/Q DAC output common-mode level. Table 5. RSSI ADC Specifications
3.4.4 Aux ADC
Aux ADC specifications are shown in Table 6.
3.4.5 Aux DAC
AUX DAC specifications are shown in Table 7. Table 6. Aux ADC Specifications Table 7. Aux DAC Specifications Table 5. RSSI ADC Specifications (continued)
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4 LP1071 Interfaces
4.1 SDIO Host Interface
SDIO host interface supports the I/O mode of the SD Card Specifications.
4.1.1 SDIO Supported Features
4.1.2 SDIO Function 0/1
128 Kbyte Memory Map and Table 8 details its registers. Table 7. Aux DAC Specifications (continued)
Figure 2. SDIO Function 1 128 Kbyte Memory Map
2 KByte Mailbox
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Table 8. SDIO Function 1 Registers
0 Wdog_reset This is a read only bit that when ‘1’ indicates that
requests from the SDIO Host to the device ARM. that particular bit in this register. a “1” to that particular bit in this register.
semaphore 1; and bit 2 is semaphore 2. is “01” then the host owns access to the mailbox. is “01” then the host owns access to the mailbox. Table 8. SDIO Function 1 Registers (continued)
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is “01” then the host owns access to the mailbox. between the SDIO device and the SDIO Host. mailbox semaphore 1 register described above. described in the mailbox semaphore 1 register.
1 Kbyte Mailbox RAM 2 (offset 0x2400 to 0x27FF)
between the SDIO device and the SDIO Host. mailbox semaphore 2 register described above. described in the mailbox semaphore 2 register.
4.2 RF Interface
4.2.1 Serial Programmable Interface (SPI)
- RF_SIF_0_SCLK (serial clock)
- RF_SIF_1_CS_N (chip select)
- RF_SIF_2_DIN (data input)
Programming clock edges are ignored until chip select goes active low. The interface can be program med in any operating mode. Serial information is clocked in with the most significant bit (MSB) first. The address bits for the internal registers are decoded on the rising edge of chip select. serially shifted-in data into the internal register.
5 Timers/Reset
The TCXO generates the 40 MHz RFIC 800 mV clipped sine wave reference clock. TCXO and PLL are powered down the only active clock source is the 32 kHz XTAL, a.k.a. the Slow Clock. reference to be driven by an external signal. Figure 3 illustrates the high level clocking of the LP1071 with the associated pins.
8 Kbyte Internal Memory Buffer RAM (offset 0x4000 to 0x5FFF)
memory under device (ARM) control.
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Figure 3. LP1071 Clocks
5.1 System Clock
oscillator (TCXO) running at 40MHz with a frequency resolution of ± 20 ppm or better.
5.2 PLL Block
5.3 Low Frequency Clock
The LP1071 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep.
6 Pinout and Footprint
6.1 Pinout
See Table 9 for the pin description. Table 9. Pin Description
40 MHz
44 MHz
20 MHz
22 MHz
88 MHz
Table 9. Pin Description (continued)
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VBG pdiana2p N/A Voltage reference pin for decoupling (equal to 1.25 V). Connect 1 uF (ceramic) + 100 nF (ceramic) to agndref.
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6.2 Pad Descriptions
secondary ESD protection circuit: ESND on these pads.
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6.3 Footprint
7.1 Absolute Maximum Ratings
Absolute maximum ratings are shown in Table 10. 1 2 3 4 5 6 7 8 9 10 11 12 A IBIAS AUXADCIN_2 PVSS3P_2 VREFN AVDDIQADC AGNDIQDAC_ IDACOUTN QDACOUTP PLL_ BYPASS PLL_ BYPASS_ CLK TCXO_ BYPASS_ CLK VDD_ CORE_5 B DVDD AUXDACOUT AVDD PVDD3P_2 NC IADCINP AVDDIQDAC VOCM FAST_CLK_ POWER TCXO_ BYPASS XTAL_ 32K_ XOUT XTAL_ 32K_XIN C PVSS3P_1 RSSIADCIN AUXADCIN_1 VBG QADCINN VREFP IADCINN IDACOUTP QDACOUTN NC VDD_ IO_6 XTAL_ BYPASS _CLK D AVSS_PLL AVDD_PLL EXT_BIAS AUXADCIN_ QADCINP AGND AGNDIQADC GND GND RESET_N XTAL_ BYPASS RF_ LOCK_ DETECT E TAVSSPOWER DVSS_PLL TAVDDPOWER DGND GND GND GND GND GND EMBEDDED _RESET_N RF_SIF_ 1_CS_N RF_ SIF_0_S CLK F AVDD_ TCXO CLKIN DVDD_PLL PVDD3P_1 GND GND GND GND GND RF_ ANTENNA_ SEL_N RF_SIF_ 2_DIN RF_ RXHP G VDD_ CORE_1 AVSS_ TCXO CHIP_ MODE_0 GND GND GND GND GND GND RF_VGA_0 RF_ ANTENNA _SEL VDD_ CORE_4 H CHIP_ MODE_2 CHIP_ MODE_1 CHIP_ MODE_3 GND GND GND GND GND GND RF_VGA_2 RF_VGA_ RF_ VGA_3 J SD_DAT_3 SD_DAT_2 SD_DAT_1 GND GND GND GND GND GND RF_ SPARE1 RF_VGA_ RF_ VGA_5 K VDD_IO_1 SD_DAT_0 SD_CMD ARM_ GPIO_2 ARM_ GPIO_6 ARM_ UART_0_DI ARM_ EEPROM_ CLK_GPIO JTAG_DO JTAG_ MODE VDD_IO_4 RF_ PAEN2 RF_ VGA_6 L SD_CLK VDD_IO_2 ARM_ GPIO_1 ARM_ GPIO_3 ARM_ GPIO_7 ARM_ EEPROM_ DAT_GPIO JTAG_ RESET JTAG_ CLOCK RF_ ANALOG_ LDO RF_EN VDD_ CORE_3 RF_ PAEN1 M VDD_IO_2 ARM_ GPIO_0 ARM_ GPIO_4 ARM_ GPIO_5 VDD_IO_3 ARM_ UART_0_ DO VDD_ CORE_2 JTAG_DI RF_RXEN RF_TXEN VDD_IO_ VDD_ CORE_3
while all other parameters are within their specified operating ranges.
7.2 Recommended Oper ating Conditions
Recommended operating conditions are shown in Table 11. Thermal dissipation (for multi-layer PCB) is shown in Table 12.
7.3 DC Characteristics
DC characteristics are shown in Table 13. Table 10. Absolute Maximum Ratings Table 11. Recommended Operating Conditions Table 12. Thermal Dissipation (for multi-layer PCB) Table 13. DC Characteristics
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Table 13. DC Characteristics (continued)
8 Timing Characteristics
8.1 AFE Interface
8.1.1 I/Q ADC
Figure 4. Timing of the Pipelining Operation in I/Q ADC
8.1.2 I/Q DAC
Figure 5. Timing Diagram of the I/Q DAC Inputs and Outputs
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8.1.3 RSSI ADC
Figure 6. Timing of the RSSI ADC Pipelining Operation
8.1.4 Auxiliary ADC
Figure 7. Timing of the Aux ADC Successive Approximation Operation
8.1.5 Auxiliary DAC
Figure 8. Conversion Cycle in Normal Operation for Aux DAC Table 14. Aux DAC Timing Parameters
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9 Mechanical Dimensions
The LP1071 is a 144-pin Very-thin Fine-pitch Ball Grid Array (VFBGA) package. All dimensions are mm. Figure 9. LP1071 Package
10 Development Support
demanding time-to-market requirements.
11 Appendix: Comparison of LP1071 and LP1072
Table 15. Comparison of LP1071 and LP1072
1 Using Maxim RF
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Revision History
This document’s updated format reflects that Freescale Semiconductor, Inc. acquired CommASIC on October 20, 2005. Since the release of the previous version of this document (Rev. 0.4), the technical content has not been updated.
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor 31 PRELIMINARY NOTES
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