LMZ10505TZE-ADJ/NO.A

LMZ10505 TI | Alldatasheet

Document overview

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Technical content

3 4, EP 6, 7 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMZ10505 SNVS633K –JANUARY 2010–REVISED APRIL 2019 LMZ105055-APowerModuleWith5.5-VMaximumInputVoltage

1 Features

1• Integrated Shielded Inductor

• Flexible Start-up Sequencing Using External Soft- Start, Tracking, and Precision Enable
• Protection Against In-Rush Currents and Faults such as Input UVLO and Output Short-Circuit
• Single Exposed Pad and Standard Pinout for Easy Mounting and Manufacturing
• Pin-to-Pin Compatible With – LMZ10503 (3-A/15-W Maximum) – LMZ10504 (4-A/20-W Maximum)
• Fully Enable for WEBENCH® and Power Designer
• Electrical Specifications – 25-W Maximum Total Output Power – Up to 5-A Output Current – Input Voltage Range 2.95 V to 5.5 V – Output Voltage Range 0.8 V to 5 V – ±1.63% Feedback Voltage Accuracy Over Temperature – Efficiency up to 96%
• Performance Benefits – Operates at High Ambient Temperatures – High Efficiency up to 96% Reduces System Heat Generation – Low Radiated Emissions (EMI) Tested to EN55022 Class B Standard (EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See Table 9 and Layout for Information on Device Under Test.) – Passes 10-V/m Radiated Immunity EMI Tested to Standard EN61000 4-3 – Fast Transient Response for Powering FPGAs and ASICs
• Create a Custom Design Using the LMZ10505 With the WEBENCH® Power Designer

2 Applications

• Point-of-Load Conversions from 3.3-V and 5-V Rails
• Space-Constrained Applications
• Noise-Sensitive Applications (Such as Transceiver, Medical)

3 Description

The LMZ10505 power module is a complete, easy-to- use, DC-DC solution capable of driving up to a 5-A load with exceptional power conversion efficiency, output voltage accuracy, line and load regulation. The LMZ10505 is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ10505 can accept an input voltage rail between 2.95 V and 5.5 V and can deliver an adjustable and highly accurate output voltage as low as 0.8 V. One megahertz fixed-frequency PWM switching provides a predictable EMI characteristic. Two external compensation components can be adjusted to set the fastest response time, while allowing the option to use ceramic or electrolytic output capacitors. Externally programmable soft-start capacitor facilitates controlled start-up. The LMZ10505 is a reliable and robust solution with the following features: lossless cycle-by-cycle peak current limit to protect for overcurrent or short-circuit fault, thermal shutdown, input undervoltage lockout, and prebiased start-up. Device Information(1)(2) PART NUMBER PACKAGE BODY SIZE (NOM) LMZ10505 TO-PMOD (7) 9.85 mm × 10.16 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Peak reflow temperature equals 245°C. See Design Summary LMZ1xxx and LMZ2xxx Power Module Family (SNAA214) for more details. Typical Application Circuit Efficiency VOUT = 3.3 V

SNVS633K –JANUARY 2010–REVISED APRIL 2019 www.ti.com Product Folder Links: LMZ10505 Submit Documentation Feedback Copyright © 2010–2019, Texas Instruments Incorporated Table of Contents

10.3 Estimate Power Dissipation and Thermal

11.3 Receiving Notification of Documentation Updates 29

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (June 2016) to Revision K Page Changes from Revision I (September 2015) to Revision J Page Changes from Revision H (October 2013) to Revision I Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision G (April 2013) to Revision H Page

6 VOUT

1 VIN

4 GND

7 VOUT

www.ti.com SNVS633K –JANUARY 2010–REVISED APRIL 2019 Product Folder Links: LMZ10505 Submit Documentation FeedbackCopyright © 2010–2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

NAME NO. EN 2 Analog Active-high enable input for the device. Exposed Pad — Ground Exposed pad is used as a thermal connection to remove heat from the device. Connect this pad to the PCB ground plane in order to reduce thermal resistance value. EP must also provide a direct electrical connection to the input and output capacitors ground terminals. Connect EP to pin 4. FB 5 Analog Feedback pin. This is the inverting input of the error amplifier used for sensing the output voltage. Keep the copper area of this node small. GND 4 Ground Power ground and signal ground. Provide a direct connection to the EP. Place the bottom feedback resistor as close as possible to GND and FB pin. SS 3 Analog Soft-start control pin. An internal 2-µA current source charges an external capacitor connected between SS and GND pins to set the output voltage ramp rate during start-up. The SS pin can also be used to configure the tracking feature. VIN 1 Power Power supply input. A low-ESR input capacitance should be located as close as possible to the VIN pin and exposed pad (EP). VOUT 6, 7 Power The output terminal of the internal inductor. Connect the output filter capacitor between VOUT pin and EP.

SNVS633K –JANUARY 2010–REVISED APRIL 2019 www.ti.com Product Folder Links: LMZ10505 Submit Documentation Feedback Copyright © 2010–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. (3) For soldering specifications, refer to the Absolute Maximum Ratings for Soldering (SNOA549).

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)(3)

VIN, VOUT, EN, FB, SS to GND –0.3 6 V Power Dissipation Internally Limited Junction Temperature 150 °C Peak Reflow Case Temperature (30 sec) 245 °C Storage Temperature, Tstg –65 150 °C (1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Test method is per JESD22-AI14S.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM)(1) ±2000 V

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN to GND 2.95 5.5 V Junction Temperature (TJ) –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. power dissipation. Refer to Layout Examples or Evaluation Board Application Note: AN-2022 LMZ1050x Evaluation Board (SNVA421).

6.4 Thermal Information

THERMAL METRIC(1) LMZ10505 UNITNDW (TO-PMOD)

7 PINS

RθJA Junction-to-ambient thermal resistance(2) 20 °C/W RθJC(top) Junction-to-case (top) thermal resistance (no air flow) 1.9 °C/W

www.ti.com SNVS633K –JANUARY 2010–REVISED APRIL 2019 Product Folder Links: LMZ10505 Submit Documentation FeedbackCopyright © 2010–2019, Texas Instruments Incorporated (1) Minimum and maximum limits are 100% production tested at an ambient temperature (TA) of 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). (2) Typical numbers are at 25°C and represent the most likely parametric norm.

6.5 Electrical Characteristics

Specifications are for TJ = 25°C unless otherwise specified. Minimum and maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = VEN = 3.3 V, unless otherwise indicated in the conditions column. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT SYSTEM PARAMETERS V FB Total Feedback Voltage Variation Including Line and Load Regulation VIN = 2.95 V to 5.5 V VOUT = 2.5 V IOUT = 0 A to 5 A 0.8 Vover the operating junction temperature range TJ of –55°C to 125°C 0.78 0.82 V FB Feedback Voltage Variation VIN = 3.3 V, VOUT = 2.5 V IOUT = 0 A 0.8 Vover the operating junction temperature range TJ of –55°C to 125°C 0.787 0.812 V FB Feedback Voltage Variation VIN = 3.3 V, VOUT = 2.5 V IOUT = 5 A 0.798 Vover the operating junction temperature range TJ of –55°C to 125°C 0.785 0.81 VIN(UVLO) Input UVLO Threshold (Measured at VIN pin) Rising 2.6 V over the operating junction temperature range TJ of –55°C to 125°C 2.95 Falling 2.4 over the operating junction temperature range TJ of –55°C to 125°C 1.95 ISS Soft-Start Current Charging Current 2 µA IQ Non-Switching Input Current VFB = 1 V 1.55 mAover the operating junction temperature range TJ of –55°C to 125°C ISD Shutdown Quiescent Current VIN = 5.5 V, VEN = 0 V 267 µAover the operating junction temperature range TJ of –55°C to 125°C 500 IOCL Output Current Limit (Average Current) VOUT = 2.5 V 7.3 Aover the operating junction temperature range TJ of –55°C to 125°C 5.1 8.7 fFB Frequency Fold-back In current limit 250 kHz PWM SECTION fSW Switching Frequency 1000 kHzover the operating junction temperature range TJ of –55°C to 125°C 750 1160 Drange PWM Duty Cycle Range over the operating junction temperature range TJ of –55°C to 125°C 0% 100% ENABLE CONTROL VEN-IH EN Pin Rising Threshold 1.23 Vover the operating junction temperature range TJ of –55°C to 125°C 1.8 VEN-IF EN Pin Falling Threshold 1.06 Vover the operating junction temperature range TJ of –55°C to 125°C 0.8

SNVS633K –JANUARY 2010–REVISED APRIL 2019 www.ti.com Product Folder Links: LMZ10505 Submit Documentation Feedback Copyright © 2010–2019, Texas Instruments Incorporated Electrical Characteristics (continued) Specifications are for TJ = 25°C unless otherwise specified. Minimum and maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = VEN = 3.3 V, unless otherwise indicated in the conditions column. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT THERMAL CONTROL TSD TJ for Thermal Shutdown 145 °C TSD-HYS Hysteresis for Thermal Shutdown 10 °C PERFORMANCE PARAMETERS ΔVOUT Output Voltage Ripple Refer to Table 1 VOUT = 2.5 V Bandwidth Limit = 2 MHz mVpk-pk ΔVOUT Output Voltage Ripple Refer to Table 5 Bandwidth Limit = 20 MHz 5 mVpk-pk ΔVFB / VFB Feedback Voltage Line Regulation ΔVIN = 2.95 V to 5.5 V IOUT = 0 A 0.04% ΔVOUT / VOUT Output Voltage Line Regulation ΔVIN = 2.95 V to 5.5 V IOUT = 0 A, VOUT = 2.5 V 0.04% ΔVFB / VFB Feedback Voltage Load Regulation IOUT = 0 A to 5 A 0.25% ΔVOUT / VOUT Output Voltage Load Regulation IOUT = 0 A to 5 A VOUT = 2.5 V 0.25% EFFICIENCY η Peak Efficiency (1A) VIN = 5 V VOUT = 3.3 V 96.1% VOUT = 2.5 V 94.8% VOUT = 1.8 V 93.1% VOUT = 1.5 V 92% VOUT = 1.2 V 90.4% VOUT = 0.8 V 86.8% η Peak Efficiency (1A) VIN = 3.3 V VOUT = 2.5 V 95.75 VOUT = 1.8 V 94.1% VOUT = 1.5 V 93.0% VOUT = 1.2 V 91.6% VOUT = 0.8 V 88.3% η Full Load Efficiency (3A) VIN = 5 V VOUT = 3.3 V 93.1% VOUT = 2.5 V 91.2% VOUT = 1.8 V 88.5% VOUT = 1.5 V 86.7% VOUT = 1.2 V 84.1% VOUT = 0.8 V 78.2% η Full Load Efficiency (3A) VIN = 3.3 V VOUT = 2.5 V 89.8% VOUT = 1.8 V 86.9% VOUT = 1.5 V 85.1% VOUT = 1.2 V 82.5% VOUT = 0.8 V 76.2%

6.6 Typical Characteristics

25°C for efficiency curves and waveforms. Figure 1. Efficiency Figure 2. Efficiency Figure 3. Efficiency Figure 4. Efficiency Figure 5. Efficiency Figure 6. Efficiency

IN(UVLO) enb R R V 1.23 V R u LMZ10505 SNVS633K –JANUARY 2010–REVISED APRIL 2019 www.ti.com Product Folder Links: LMZ10505 Submit Documentation Feedback Copyright © 2010–2019, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LMZ10505 power module is a complete, easy-to-use DC-DC solution capable of driving up to a 5-A load with exceptional power conversion efficiency, output voltage accuracy, line and load regulation. The LMZ10505 is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ10505 is a reliable and robust solution with the following features: lossless cycle-by-cycle peak current limit to protect for overcurrent or short-circuit fault, thermal shutdown, input undervoltage lockout, and prebiased start-up.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Enable

The LMZ10505 features an enable (EN) pin and associated comparator to allow the user to easily sequence the LMZ10505 from an external voltage rail, or to manually set the input UVLO threshold. The turnon or rising threshold and hysteresis for this comparator are typically 1.23 V and 0.15 V, respectively. The precise reference for the enable comparator allows the user to ensure that the LMZ10505 will be disabled when the system demands it to be. The EN pin should not be left floating. For always-on operation, connect EN to VIN.

7.3.2 Enable and UVLO

Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the part begins switching can be increased above the normal input UVLO level according to: (1) For example, suppose that the required input UVLO level is 3.69 V. Choosing Renb = 10 kΩ, then we calculate Rent = 20 kΩ.

Figure 16. Setting Enable and UVLO start based on the voltage level of a master system rail (VOUT1). Figure 17. Setting Enable and UVLO Using External Power Supply

7.3.3 Soft-Start

more control and flexibility when sequencing the LMZ10505 with other power supplies.

7.3.4 Soft-Start Capacitor

• VFB is the internal reference voltage (nominally 0.8 V),
• ISS is the soft-start charging current (nominally 2 µA),
• and CSS is the external soft-start capacitance. (2) Thus, the required soft-start capacitor per unit output voltage startup time is given by: (3) For example, a 4-ms soft-start time will yield a 10-nF capacitance. The minimum soft-start capacitance is 680 pF.

7.3.5 Tracking

Figure 18. Tracking Using External Power Supply

7.3.6 Tracking - Equal Soft-Start Time

example of tracking using the equal soft-start time. Figure 19. Timing Diagram for Tracking Using Equal Soft-Start Time

7.3.7 Tracking - Equal Slew Rates

the above equation to be 15.5 kΩ. Figure 20 shows an example of tracking using the equal slew rates. Figure 20. Timing Diagram for Tracking Using Equal Slew Rates

7.3.8 Current Limit

the low-side MOSFET is activated. The low-side MOSFET stays on for the entire next four switching cycles. part will resume normal operation smoothly.

7.3.9 Overtemperature Protection

part will re-initiate the soft-start sequence and begin switching once again.

7.4 Device Functional Modes

7.4.1 Prebias Start-Up Capability

LMZ10505 will not sink current during start-up until the soft-start voltage exceeds the voltage on the FB pin. is conducted through the parasitic paths of the load.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

components for the LMZ10505. Alternately, the WEBENCH software may be used to generate complete designs. comprehensive databases of components. Please go to www.ti.com for more details.

8.2 Typical Application

Figure 21. Typical Application Schematic

8.2.1 Design Requirements

For this example the following application parameters exist.

• VIN = 5 V
• VOUT = 2.5 V
• IOUT = 5 A
• ΔVOUT = 20 mVpk-pk
• ΔVo_tran = ±20 mVpk-pk

Table 1. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A,

Table 2. Bill of Materials, VIN = 3.3 V, VOUT = 0.8 V, IOUT (MAX) = 5 A,

8.2.2 Detailed Design Procedure

external components can be calculated by following the design procedure below.

1. Determine the input voltage and output voltage. Also, make note of the ripple voltage and voltage transient
2. Determine the necessary input and output capacitance.
3. Calculate the feedback resistor divider.
4. Select the optimized compensation component values.
5. Estimate the power dissipation and board thermal requirements.
6. Follow the PCB design guideline.
7. Learn about the LMZ10505 features such as enable, input UVLO, soft-start, tracking, prebiased start-up,

current limit, and thermal shutdown.

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZ10504 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

pricing and component availability.

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

L sw (V V ) Di L f u ' u > @ L O sw OUT L ESR iC 8 f V ( i R ) 't u u ' ' u Cin(RMS) 2.5 V 2.5 VI 5 A 1 2.5 A 5 V 5 V § · u ¨ ¸ © ¹ Cin(RMS) OUTI I D(1 D) u in 2.5 V 2.5 V5 A 1 5 V 5 VC 25 F 1 MHz 50mV © ¹ © ¹t t P u OUT IN VD V OUT in sw IN I D (1 D)C f V u u t u ' LMZ10505 SNVS633K –JANUARY 2010–REVISED APRIL 2019 www.ti.com Product Folder Links: LMZ10505 Submit Documentation Feedback Copyright © 2010–2019, Texas Instruments Incorporated

8.2.2.2 Input Capacitor Selection

A 22-µF or 47-µF high-quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum input voltage is typically sufficient. The input capacitor must be placed as close as possible to the VIN pin and GND exposed pad to substantially eliminate the parasitic effects of any stray inductance or resistance on the PCB and supply lines. Neglecting capacitor equivalent series resistance (ESR), the resultant input capacitor AC ripple voltage is a triangular waveform. The minimum input capacitance for a given peak-to-peak value (ΔVIN) of VIN is specified as follows: where

• the PWM duty cycle, D, is given by Equation 8: (7) (8) If ΔVIN is 1% of VIN, this equals to 50 mV and fSW = 1 MHz (9) A second criteria before finalizing the Cin bypass capacitor is the RMS current capability. The necessary RMS current rating of the input capacitor to a buck regulator can be estimated by: (10) (11) With this high AC current present in the input capacitor, the RMS current rating becomes an important parameter. The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. Select an input capacitor rated for at least the maximum calculated ICin(RMS). Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input capacitance and parasitic inductance.

8.2.2.3 Output Capacitor Selection

In general, 22-µF to 100-µF high-quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum output voltage is sufficient given the optimal high-frequency characteristics and low ESR of ceramic dielectrics. Although, the output capacitor can also be of electrolytic chemistry for increased capacitance density. Two output capacitance equations are required to determine the minimum output capacitance. One equation determines the output capacitance (CO) based on PWM ripple voltage. The second equation determines CO based on the load transient characteristics. Select the largest capacitance value of the two. The minimum capacitance, given the maximum output voltage ripple (ΔVOUT) requirement, is determined by Equation 12: where

• the peak to peak inductor current ripple (ΔiL) is equal to Equation 13: (12) (13)

Three mΩ is a typical RESR value for ceramic capacitors.

• Istep is the peak to peak load step (10% to 90% of the maximum load for this example),
• VFB = 0.8 V,
• and ΔVo_tran is the maximum output voltage deviation, which is ±20 mV. (17) Therefore the capacitance requirement for the given design parameters is: (18) (19) In this particular design the output capacitance is determined by the load transient requirements. Table 3 lists some examples of commercially available capacitors that can be used with the LMZ10505.

Table 3. Recommended Output Filter Capacitors

8.2.2.3.1 Output Voltage Setting

Rfbt is defined based on the voltage loop requirements and Rfbb is then selected for the desired output voltage.

every other switching cycle.

8.2.2.4 Loop Compensation

capacitance values above the suggested values will experience a lower bandwidth and increased phase margin. Figure 22. Loop Compensation Control Components Table 4. LMZ10505 Compensation Component Values

Table 4. LMZ10505 Compensation Component Values (continued)

8.2.3 Application Curves

Figure 23. Current Derating Figure 24. Efficiency Figure 25. Radiated Emissions (EN 55022, Class B)

8.3 System Examples

Figure 26. Schematic for 2.5-V Output Based on 3.3-V to 5-V Input Table 5. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A, Table 6. Output Voltage Setting (Rfbt = 75 kΩ)

1.8 V 59 kΩ

1.2 V 150 kΩ

0.9 V 590 kΩ

Figure 27. Schematic for 2.5-V Output Based on 3.3-V to 5-V Input Table 7. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A Table 8. Output Voltage Setting (Rfbt = 75 kΩ)

Figure 28. EMI Tested Schematic for 2.5-V Output Based on 3.3-V to 5-V Input Table 9. Bill of Materials, VIN = 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A, Table 10. Output Voltage Setting (Rfbt = 75 kΩ)

www.ti.com SNVS633K –JANUARY 2010–REVISED APRIL 2019 Product Folder Links: LMZ10505 Submit Documentation FeedbackCopyright © 2010–2019, Texas Instruments Incorporated

9 Power Supply Recommendations

The LMZ10505 device is designed to operate from an input voltage supply range between 2.95 V and 5.5 V. This input supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail should be low enough that an input current transient does not cause a high enough drop at the LMZ10505 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is more than a few inches from the LMZ10505, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47- μF or 100-μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths. The high current that does not overlap contains high di/dt, see Figure 29. Therefore physically place input capacitor (Cin1) as close as possible to the LMZ10505 VIN pin and GND exposed pad to avoid observable high frequency noise on the output pin. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed only to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly placed, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP. 3. Minimize trace length to the FB pin. Both feedback resistors, Rfbt and Rfbb, and the compensation components, Rcomp and Ccomp, should be located close to the FB pin. Since the FB node is high impedance, keep the copper area as small as possible. This is most important as relatively high-value resistors are used to set the output voltage. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made at the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.

10.2 Layout Examples

The PCB design is available in the LMZ10505 product folder at www.ti.com. Figure 29. Critical Current Loops to Minimize Figure 30. PCB Layout Guide

o o 2 500 C cmBoard Area_cm WC27.5W ut u o 2 CA

500 C cmBoard Area_cm W

125 C 85 C C C1.9 27.51.36 W W W T J(MAX) A(MAX) CA JC IC_LOSS T T P T t T LMZ10505 www.ti.com SNVS633K –JANUARY 2010–REVISED APRIL 2019 Product Folder Links: LMZ10505 Submit Documentation FeedbackCopyright © 2010–2019, Texas Instruments Incorporated

10.3 Estimate Power Dissipation and Thermal Considerations

Use the current derating curves in the Typical Characteristics section to obtain an estimate of power loss (PIC_LOSS). For the design case of VIN = 5 V, VOUT = 2.5 V, IOUT = 5 A, TA(MAX) = 85°C , and TJ(MAX) = 125°C, the device must see a thermal resistance from case to ambient (θCA) of less than: (21) (22) Given the typical thermal resistance from junction to case (θJC) to be 1.9°C/W (typ.). Continuously operating at a TJ greater than 125°C will have a shorten life span. To reach θCA = 27.5°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the required board area covered by 1-oz. copper on both the top and bottom metal layers is: (23) (24) As a result, approximately 18 square cm of 1-oz. copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad (EP). Approximately thirty six, 8 mils thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an extended discussion and formulations of thermal rules of thumb, refer to AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419). For an example of a high thermal performance PCB layout with θJA of 20°C/W, refer to the evaluation board application note AN-2022 LMZ1050x Evaluation Board (SNVA421) and for results of a study of the effects of the PCB designs, refer to AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424).

10.4 Power Module SMT Guidelines

• Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture – For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern – For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness – 0.125 to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
• Maximum number of reflows allowed is one
• Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information.

Figure 35. Sample Reflow Profile Table 11. Sample Reflow Profile Table

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

11.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZ10505 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following:

• AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module (SNVA425)
• Absolute Maximum Ratings for Soldering (SNOA549)
• AN-2022 LMZ1050x Evaluation Board (SNVA421)
• AN-2013 LMZ1050x/LMZ1050xEXT SIMPLE SWITCHER Power Module (SNVA417)
• AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422)
• AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)
• AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424)
• Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214)

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

SNVS633K –JANUARY 2010–REVISED APRIL 2019 www.ti.com Product Folder Links: LMZ10505 Submit Documentation Feedback Copyright © 2010–2019, Texas Instruments Incorporated Community Resources (continued) Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

www.ti.com SNVS633K –JANUARY 2010–REVISED APRIL 2019 Product Folder Links: LMZ10505 Submit Documentation FeedbackCopyright © 2010–2019, Texas Instruments Incorporated

11.5 Trademarks

E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMZ10505TZ-ADJ/NO.A Active Production TO-PMOD (NDW) | 7 250 | SMALL T&R Yes SN Level-3-245C-168 HR -40 to 125 LMZ10505 TZ-ADJ LMZ10505TZ-ADJ/NOPB Active Production TO-PMOD (NDW) | 7 250 | SMALL T&R Exempt SN Level-3-245C-168 HR -40 to 125 LMZ10505 TZ-ADJ LMZ10505TZE-ADJ/NO.A Active Production TO-PMOD (NDW) | 7 45 | TUBE Yes SN Level-3-245C-168 HR -40 to 125 LMZ10505 TZ-ADJ LMZ10505TZE-ADJ/NOPB Active Production TO-PMOD (NDW) | 7 45 | TUBE Exempt SN Level-3-245C-168 HR -40 to 125 LMZ10505 TZ-ADJ LMZ10505TZX-ADJ/NO.A Active Production TO-PMOD (NDW) | 7 500 | LARGE T&R Yes SN Level-3-245C-168 HR -40 to 125 LMZ10505 TZ-ADJ LMZ10505TZX-ADJ/NOPB Active Production TO-PMOD (NDW) | 7 500 | LARGE T&R Exempt SN Level-3-245C-168 HR -40 to 125 LMZ10505 TZ-ADJ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LMZ10505TZ-ADJ/NOPB TO- PMOD LMZ10505TZX- ADJ/NOPB TO- PMOD Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMZ10505TZ-ADJ/NOPB TO-PMOD NDW 7 250 356.0 356.0 45.0 LMZ10505TZX-ADJ/NOPB TO-PMOD NDW 7 500 356.0 356.0 45.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LMZ10505TZE-ADJ/NO.A NDW TO-PMOD 7 45 502 17 6700 8.4 LMZ10505TZE-ADJ/NOPB NDW TO-PMOD 7 45 502 17 6700 8.4 Pack Materials-Page 3

www.ti.com TZA07A (Rev D) TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE

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