LMZ10503EXTTZX/NOPB

Texas Instruments

3A SIMPLE SWITCHER Power Module With 5.5-V Maximum Input Voltage for Demanding and Rugged Applications

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LMZ10503EXT 3A SIMPLE SWITCHER Power Module with 5.5V Max Input Voltage (Rev. H)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SNVS668,H]
PDF pages: 36

Technical content

3 4, EP 6, 7 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LMZ10503EXT SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015 LMZ10503EXT3-ASIMPLESWITCHER®PowerModuleWith5.5-VMaximumInputVoltage forDemandingandRuggedApplications

1 Features 2 Applications

1• Integrated Shielded Inductor • Point-of-Load Conversions From 3.3-V and 5-V Rails• Flexible Start-up Sequencing Using External Soft- Start, Tracking, and Precision Enable • Space-Constrained Applications

Protection Against In-Rush Currents and Faults • Noise-Sensitive Applications (Such as Such as Input UVLO and Output Short-Circuit Transceiver, Medical)
Single Exposed Pad and Standard Pinout for Easy

3 DescriptionMounting and Manufacturing

The LMZ10503EXT SIMPLE SWITCHER® power• Pin-to-Pin Compatible With module is a complete, easy-to-use, DC-DC solution– LMZ10504EXT (4-A/20-W Maximum) capable of driving up to a 3-A load with exceptional – LMZ10505EXT (5-A/25-W Maximum) power conversion efficiency, output voltage accuracy, line and load regulation. The LMZ10503EXT is• Fast Transient Response for Powering FPGAs available in an innovative package that enhancesand ASICs thermal performance and allows for hand or machine• Electrical Specifications soldering. – 15-W Maximum Total Output Power The LMZ10503EXT can accept an input voltage rail– Up to 3-A Output Current between 2.95 V and 5.5 V, and can deliver an – Input Voltage Range 2.95 V to 5.5 V adjustable and highly accurate output voltage as low

Performance Benefits option to use ceramic or electrolytic output capacitors. Externally programmable soft-start capacitor– Operates at High Ambient Temperatures facilitates controlled start-up. The LMZ10503EXT is a– Low Radiated Emissions (EMI) Tested to reliable and robust solution with the followingEN55022 Class B Standard features: lossless cycle-by-cycle peak current limit to – Passes 10-V/m Radiated Immunity EMI Tested protect for over current or short-circuit fault, thermal shutdown, input undervoltage lockout, and prebiasedto Standard EN61000 4-3 start-up. The LMZ10503EXT is also fully-enabled for– Passes Vibration Standard WEBENCH® and Power Designer tools.– MIL-STD-883 Method 2007.2 Condition A Device Information(1)(2)– JESD22-B103B Condition 1 PART NUMBER PACKAGE BODY SIZE (NOM)– Passes Drop Standard LMZ10503EXT TO-PMOD (7) 9.85 mm × 10.16 mm– MIL-STD-883 Method 2002.3 Condition B (1) For all available packages, see the orderable addendum at– JESD22-B110 Condition B the end of the data sheet. NOTE: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. (2) Peak reflow temperature equals 245°C. See SNAA214 forSee Figure 21 and layout for information on device under more details.test. Typical Application Circuit Efficiency VOUT = 3.3 V An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (October 2013) to Revision H Page

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision F (April 2013) to Revision G Page

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6 VOUT

1 VIN

4 GND

7 VOUT

www.ti.com SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015

5 Pin Configuration and Functions

NAME NO. EN 2 Analog Active-high enable input for the device. Exposed pad thermal connection. Connect this pad to the PCB ground plane in order to Exposed Pad — Ground reduce thermal resistance value. It also provides an electrical connection to the input and output capacitors ground terminals. Feedback pin. This is the inverting input of the error amplifier used for sensing the outputFB 5 Analog voltage. Power ground and signal ground. Connect the bottom feedback resistor between this pin andGND 4 Ground the feedback pin. Soft-start control pin. An internal 2-µA current source charges and external capacitor SS 3 Analog connected between this pin and GND (pin 4) to set the output voltage ramp rate during start- up. This pin can also be used to configure the tracking feature. A low-ESR input capacitance should be located as close as possible to VIN pin and GNDVIN 1 Power pin. This is the output of the internal inductor. Connect an external resistor voltage divider fromVOUT 6, 7 Power VOUT to FB to ground. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMZ10503EXT

SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015 www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings (1)(2)

VIN, VOUT, EN, FB, SS to GND –0.3 6 V Power Dissipation Internally Limited Junction Temperature 150 °C Peak Reflow Case Temperature (30 sec) 245 °C Storage Temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) For soldering specifications, refer to the following document: SNOA549

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM)(1) ±2000 V (1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Test method is per JESD22-AI14S.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN to GND 2.95 5.5 V Junction Temperature (TJ) –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) NDW (TO-PMOD) UNIT

7 PINS

RθJA Junction-to-ambient thermal resistance(2) 20 °C/W RθJC(top) Junction-to-case (top) thermal resistance (no air flow) 1.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. power dissipation. Refer to Evaluation Board Application Note: AN-2074 (SNVA450).

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6.5 Electrical Characteristics

Specifications are for TJ = 25°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = VEN = 3.3 V, unless otherwise indicated in the conditions column. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT SYSTEM PARAMETERS 0.8 Total Feedback Voltage VIN = 2.95 V to 5.5 V over the operating junctionV FB Variation Including Line VOUT = 2.5 V V temperature range TJ of –55°C 0.78 0.82and Load Regulation IOUT = 0 A to 3 A to 125°C 0.8 VIN = 3.3 V, VOUT = 2.5Feedback Voltage over the operating junctionV FB V VVariation temperature range TJ of –55°C 0.787 0.812IOUT = 0 A to 125°C 0.798 VIN = 3.3 V, VOUT = 2.5Feedback Voltage over the operating junctionV FB V VVariation temperature range TJ of –55°C 0.785 0.81IOUT = 3 A to 125°C 2.6 over the operating junctionRising temperature range TJ of –55°C 2.95 to 125°CInput UVLO ThresholdVIN(UVLO) V(Measured at VIN pin) 2.4 over the operating junctionFalling temperature range TJ of –55°C 1.95 to 125°C ISS Soft-Start Current Charging Current 2 µA 1.7 Non-Switching Input over the operating junctionIQ VFB = 1 V mACurrent temperature range TJ of –55°C 3 to 125°C 260 Shutdown Quiescent over the operating junctionISD VIN = 5.5 V, VEN = 0 V µACurrent temperature range TJ of –55°C 500 to 125°C 5.2 Output Current Limit over the operating junctionIOCL VOUT = 2.5 V A(Average Current) temperature range TJ of –55°C 3.8 6.7 to 125°C fFB Frequency Fold-back In current limit 250 kHz PWM SECTION 1000 fSW Switching Frequency kHzover the operating junction temperature range TJ of –55°C 700 1160to 125°C PWM Duty Cycle over the operating junction temperature range TJ of –55°CDrange 0% 100%Range to 125°C ENABLE CONTROL 1.23 EN Pin RisingVEN-IH Vover the operating junction temperature range TJ of –55°CThreshold 1.8to 125°C 1.06 EN Pin FallingVEN-IF Vover the operating junction temperature range TJ of –55°CThreshold 0.8to 125°C (1) Minimum and maximum limits are 100% production tested at an ambient temperature (TA) of 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL). (2) Typical numbers are at 25°C and represent the most likely parametric norm. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMZ10503EXT

SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) Specifications are for TJ = 25°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = VEN = 3.3 V, unless otherwise indicated in the conditions column. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT THERMAL CONTROL TJ for ThermalTSD 145 °CShutdown Hysteresis for ThermalTSD-HYS 10 °CShutdown PERFORMANCE PARAMETERS Refer to Table 1 mVpk-pk ΔVOUT Output Voltage Ripple VOUT = 2.5 V 7 Bandwidth Limit = 2 MHz ΔVOUT Output Voltage Ripple Refer to Table 5 Bandwidth Limit = 20 MHz 5 mVpk-pk ΔVFB / Feedback Voltage Line ΔVIN = 2.95 V to 5.5 V 0.04%VFB Regulation IOUT = 0 A ΔVOUT / Output Voltage Line ΔVIN = 2.95 V to 5.5 V 0.04%VOUT Regulation IOUT = 0 A, VOUT = 2.5 V ΔVFB / Feedback Voltage Load IOUT = 0 A to 3 A 0.25%VFB Regulation ΔVOUT / Output Voltage Load IOUT = 0 A to 3 A 0.25%VOUT Regulation VOUT = 2.5 V EFFICIENCY VOUT = 3.3 V 96.3% VOUT = 2.5 V 94.9% VOUT = 1.8 V 93.3%Peak Efficiency (1A)η VIN = 5 V VOUT = 1.5 V 92.2% VOUT = 1.2 V 90.5% VOUT = 0.8 V 86.9% VOUT = 2.5 V 95.7% VOUT = 1.8 V 94.0% Peak Efficiency (1A)η VOUT = 1.5 V 92.9%VIN = 3.3 V VOUT = 1.2 V 91.3% VOUT = 0.8 V 87.9% VOUT = 3.3 V 94.8% VOUT = 2.5 V 93% VOUT = 1.8 V 90.8%Full Load Efficiencyη (3A) VIN = 5 V VOUT = 1.5 V 89.3% VOUT = 1.2 V 87.1% VOUT = 0.8 V 82.3% VOUT = 2.5 V 92.4% VOUT = 1.8 V 89.8% Full Load Efficiencyη VOUT = 1.5 V 88.2%(3A) VIN = 3.3 V VOUT = 1.2 V 85.9% VOUT = 0.8 V 80.8%

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6.6 Typical Characteristics

TA = 25°C for efficiency curves and waveforms. Figure 1. Efficiency Figure 2. Efficiency Figure 3. Efficiency Figure 4. Efficiency Figure 6. EfficiencyFigure 5. Efficiency

TA = 25°C for efficiency curves and waveforms. Figure 7. Current Derating Figure 8. Current Derating Figure 9. Radiated Emissions (EN55022, Class B) Figure 10. Start-Up Figure 12. Load Transient ResponseFigure 11. Prebiased Start-Up

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R RV V R( ) 1.23 /c180/c61 /c180 EN VIN Voltage Mode Control VOUT GND SS FB 2.2 PH 2.2 PF 2.2 PF 4, EP5 6, 7 Drivers P-MOSFETN-MOSFET LMZ10503EXT SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015 www.ti.com

7 Detailed Description

7.1 Overview

The LMZ10503EXT SIMPLE SWITCHER power module is a complete, easy-to-use DC-DC solution capable of driving up to a 3-A load with exceptional power conversion efficiency, output voltage accuracy, line and load regulation. The LMZ10503EXT is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ10503EXT is a reliable and robust solution with the following features: lossless cycle-by-cycle peak current limit to protect for overcurrent or short-circuit fault, thermal shutdown, input undervoltage lockout, and prebiased start-up.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Enable

The LMZ10503EXT features an enable (EN) pin and associated comparator to allow the user to easily sequence the LMZ10503EXT from an external voltage rail, or to manually set the input UVLO threshold. The turnon or rising threshold and hysteresis for this comparator are typically 1.23 V and 0.15 V, respectively. The precise reference for the enable comparator allows the user to ensure that the LMZ10503EXT will be disabled when the system demands it to be. The EN pin should not be left floating. For always-on operation, connect EN to VIN.

7.3.2 Enable and UVLO

Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the part begins switching can be increased above the normal input UVLO level according to: (1) For example, suppose that the required input UVLO level is 3.69 V. Choosing Renb = 10 kΩ, then we calculate Rent = 20 kΩ.

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Figure 16. Setting Enable and UVLO to start based on the voltage level of a master system rail (VOUT1). Figure 17. Setting Enable and UVLO Using External Power Supply

7.3.3 Soft-Start

more control and flexibility when sequencing the LMZ10503EXT with other power supplies.

7.3.4 Soft-Start Capacitor

VFB is the internal reference voltage (nominally 0.8 V),
ISS is the soft-start charging current (nominally 2 µA)
and CSS is the external soft-start capacitance. (2) Thus, the required soft-start capacitor per unit output voltage start-up time is given by: (3) For example, a 4-ms soft-start time will yield a 10-nF capacitance. The minimum soft-start capacitance is 680 pF. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LMZ10503EXT

7.3.5 Tracking

Figure 18. Tracking Using External Power Supply

7.3.6 Tracking - Equal Soft-Start Time

example of tracking using equal soft-start time. Figure 19. Timing Diagram for Tracking Using Equal Soft-Start Time

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7.3.7 Tracking - Equal Slew Rates

Equation 5 to be 15.5 kΩ. Figure 20 shows an example of tracking using equal slew rates. Figure 20. Timing Diagram for Tracking Using Equal Slew Rates

7.3.8 Current Limit

the low-side MOSFET is activated. The low-side MOSFET stays on for the entire next four switching cycles. part will resume normal operation smoothly.

7.3.9 Overtemperature Protection

the part will re-initiate the soft-start sequence and begin switching once again.

7.4 Device Functional Modes

7.4.1 Prebias Start-Up Capability

LMZ10503EXT will not sink current during start-up until the soft-start voltage exceeds the voltage on the FB pin. is conducted through the parasitic paths of the load.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

comprehensive databases of components. Please go to www.ti.com for more details.

8.2 Typical Application

Figure 21. Typical Applications Schematic

8.2.1 Design Requirements

For this example the following application parameters exist.

VIN = 5 V
VOUT = 2.5 V
IOUT = 3 A
ΔVOUT = 20 mVpk-pk
ΔVo_tran = ±20 mVpk-pk

Table 1. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 3 A,

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Table 2. Bill of Materials, VIN = 3.3 V, VOUT = 0.8 V, IOUT (MAX) = 3 A, Optimized for Solution Size and

8.2.2 Detailed Design Procedure

external components can be calculated by following the design procedure below.

Determine the input voltage and output voltage. Also, make note of the ripple voltage and voltage transient
Determine the necessary input and output capacitance.
Calculate the feedback resistor divider.
Select the optimized compensation component values.
Estimate the power dissipation and board thermal requirements.
Follow the PCB design guideline.
Learn about the LMZ10503EXT features such as enable, input UVLO, soft-start, tracking, prebiased start-up,

current limit, and thermal shutdown.

8.2.2.1 Input Capacitor Selection

the PWM duty cycle, D, is given by Equation 8: (7) Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LMZ10503EXT

O OUT IN OUT I V L V C V V V Vo tran4 ( ) _ /c180 /c180 /c180 /c179 /c180 /c180 /c45 /c180 /c68 OC F 4/c179 /c109 /c91 /c93 O mAC MHz mV mA m ) 568 8 1 20 (568 3/c179 /c180 /c180 /c45 /c180 /c87 L VV V Vi mA H MHz 2.5(5 2.2 ) 5 5682.2 1 /c45 /c180 /c68 /c61 /c61 /c109 /c180 IN OUT L sw V V Di L f ( ) /c45 /c180/c68 /c61 /c180 /c91 /c93 L O sw OUT L ESR iC f V i R8 ( ) /c68/c179 /c180 /c180 /c68 /c45 /c68 /c180 Cin RMS V VI A A V V( ) 2.5 2.53 1 1.5 5 5 /c230 /c246/c61 /c180 /c45 /c61 /c231 /c247 /c232 /c248 Cin RMS OUTI I D D( ) (1 )/c61 /c180 /c45 in V VA V VC F MHz mV 2.5 2.53 1 5 5 151 50 /c230 /c246 /c230 /c246/c180 /c180 /c45 /c231 /c247 /c231 /c247 /c232 /c248 /c232 /c248/c179 /c179 /c109 /c180 OUT IN VD V/c61 LMZ10503EXT SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015 www.ti.com (8) If ΔVIN is 1% of VIN, this equals to 50 mV and fSW = 1 MHz (9) A second criteria before finalizing the Cin bypass capacitor is the RMS current capability. The necessary RMS current rating of the input capacitor to a buck regulator can be estimated by: (10) (11) With this high AC current present in the input capacitor, the RMS current rating becomes an important parameter. The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. Select an input capacitor rated for at least the maximum calculated ICin(RMS). Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input capacitance and parasitic inductance.

8.2.2.2 Output Capacitor Selection

In general, 22-µF to 100-µF high-quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum output voltage is sufficient given the optimal high-frequency characteristics and low ESR of ceramic dielectrics. Although, the output capacitor can also be of electrolytic chemistry for increased capacitance density. Two output capacitance equations are required to determine the minimum output capacitance. One equation determines the output capacitance (CO) based on PWM ripple voltage. The second equation determines CO based on the load transient characteristics. Select the largest capacitance value of the two. The minimum capacitance, given the maximum output voltage ripple (ΔVOUT) requirement, is determined by Equation 12: where

the peak to peak inductor current ripple (ΔiL) is equal to Equation 13: (12) (13) RESR is the total output capacitor ESR, L is the inductance value of the internal power inductor, where L = 2.2 µH, and fSW = 1 MHz. Therefore, per the design example: (14) The minimum output capacitance requirement due to the PWM ripple voltage is: (15) (16) Three mΩ is a typical RESR value for ceramic capacitors. Equation 17 provides a good first pass capacitance requirement for a load transient:

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Istep is the peak to peak load step (for this example Istep = 10% to 90% of the maximum load),
VFB = 0.8 V, and ΔVo_tran is the maximum output voltage deviation, which is ±20 mV. (17) Therefore the capacitance requirement for the given design parameters is: (18) (19) In this particular design the output capacitance is determined by the load transient requirements. Table 3 lists some examples of commercially available capacitors that can be used with the LMZ10503EXT.

Table 3. Recommended Output Filter Capacitors

8.2.2.2.1 Output Voltage Setting

Rfbt is defined based on the voltage loop requirements and Rfbb is then selected for the desired output voltage. each evident every other switching cycle.

8.2.2.3 Loop Compensation

60° of phase margin, with a bandwidth of 100 kHz ±20 kHz. Figure 22. Loop Compensation Control Components Table 4. LMZ10503EXT Compensation Component Values(1)

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8.2.3 Application Curves

Figure 23. Current Derating Figure 24. Efficiency Figure 25. Radiated Emissions (EN 55022, Class B)

8.3 System Examples

input voltage operating point. Figure 26. Schematic for 2.5-V Output Based on 3.3-V to 5-V Input Table 5. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 3 A, (1) Optional components, include for low input and output voltage ripple. Table 6. Output Voltage Setting (Rfbt = 75 kΩ)

1.8 V 59 kΩ

1.2 V 150 kΩ

0.9 V 590 kΩ

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input voltage operating point. Figure 27. Schematic for 2.5-V Output Based on 3.3-V to 5-V Input Table 7. Bill of Materials for Evaluation Board, VIN = 3.3 V to 5 V, Table 8. Output Voltage Setting (Rfbt = 75 kΩ)

input voltage operating point. Figure 28. EMI Tested Schematic for 2.5-V Output Based on 3.3-V to 5-V Input Table 9. Bill of Materials, VIN = 5 V, VOUT = 2.5 V, IOUT (MAX) = 3 A, Table 10. Output Voltage Setting (Rfbt = 75 kΩ)

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9 Power Supply Recommendations

The LMZ10503EXT device is designed to operate from an input voltage supply range between 2.95 V and 5.5 V. This input supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail should be low enough that an input current transient does not cause a high enough drop at the LMZ10503EXT supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is more than a few inches from the LMZ10503EXT, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths. The high current that does not overlap contains high di/dt, see Figure 29. Therefore physically place input capacitor (Cin1) as close as possible to the LMZ10503EXT VIN pin and GND exposed pad to avoid observable high-frequency noise on the output pin. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed only to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly placed, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP. 3. Minimize trace length to the FB pin. Both feedback resistors, Rfbt and Rfbb, and the compensation components, Rcomp and Ccomp, should be located close to the FB pin. Because the FB node is high impedance, keep the copper area as small as possible. This is most important as relatively high-value resistors are used to set the output voltage. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made at the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: LMZ10503EXT

10.2 Layout Examples

The PCB design is available in the LMZ10503EXT product folder at www.ti.com. Figure 29. Critical Current Loops to Minimize Figure 30. PCB Layout Guide

Figure 33. Internal Layer 2 (Ground and Signal Traces) Figure 34. Bottom Copper

2 C cmBoard Area_cm WC

W 2500 69.5 /c180/c179 /c111 /c111/c103 CA C cmBoard Area_cm W 2 500 /c180/c179/c113 /c111 /c103 CA C C C C W W W 125 85 1.9 69.50.56 /c45/c113 /c60 /c45 /c60 /c111 /c111 /c111 /c111 J MAX A MAX CA JC IC LOSS T T P ( ) ( ) /c45 /c113 /c179 /c45 /c113 LMZ10503EXT www.ti.com SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015

10.3 Estimate Power Dissipation and Thermal Considerations

Use the current derating curves in the Typical Characteristics section to obtain an estimate of power loss (PIC_LOSS). For the design case of VIN = 5 V, VOUT = 2.5 V, IOUT = 3 A, TA(MAX) = 85°C , and TJ(MAX) = 125°C, the device must see a thermal resistance from case to ambient (θCA) of less than: (21) (22) Given the typical thermal resistance from junction to case (θJC) to be 1.9°C/W (typical). Continuously operating at a TJ greater than 125°C will have a shorten life span. To reach θCA = 69.5°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the required board area covered by 1-oz. copper on both the top and bottom metal layers is: (23) (24) As a result, approximately 7.2 square cm of 1-oz. copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad (EP). Approximately thirty six, 8 mils thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an extended discussion and formulations of thermal rules of thumb, refer to AN-2020 (SNVA419). For an example of a high thermal performance PCB layout with θJA of 20°C/W, refer to the evaluation board application note AN-2074 (SNVA450) and for results of a study of the effects of the PCB designs, refer to AN-2026 (SNVA424). Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LMZ10503EXT

10.4 Power Module SMT Guidelines

Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
Stencil Aperture – For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern – For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher
Stencil Thickness – 0.125 to 0.15 mm
Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
Maximum number of reflows allowed is one
Refer to AN Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information.

Figure 35. Sample Reflow Profile Table 11. Sample Reflow Profile Table

www.ti.com SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

For developmental support, see the following: WEBENCH Tool, http://www.ti.com/webench

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following:

AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, SNVA425)
Absolute Maximum Ratings for Soldering, (SNOA549)
AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422)
AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)
AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424)
Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214)

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: LMZ10503EXT

SNVS668H –JUNE 2010–REVISED SEPTEMBER 2015 www.ti.com

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LMZ10503EXT

www.ti.com 6-Aug-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMZ10503EXTTZ/NOPB ACTIVE TO-PMOD NDW 7 250 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 LMZ10503 EXT LMZ10503EXTTZE/NOPB ACTIVE TO-PMOD NDW 7 45 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 LMZ10503 EXT LMZ10503EXTTZX/NOPB ACTIVE TO-PMOD NDW 7 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 LMZ10503 EXT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 6-Aug-2015 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LMZ10503EXTTZ/NOPB TO- PMOD LMZ10503EXTTZX/NOPB TO- PMOD PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMZ10503EXTTZ/NOPB TO-PMOD NDW 7 250 367.0 367.0 45.0 LMZ10503EXTTZX/NOPB TO-PMOD NDW 7 500 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2015 Pack Materials-Page 2

www.ti.com TZA07A (Rev D) TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE

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