LMX3160

LMX3160 NSC | Alldatasheet

Document overview

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Technical content

Features

Y Single chip solution for DECT RF transceiver Y RF sensitivity to b93 dBm; RSSI sensitivity to b100 dBm Y Two regulated voltage outputs for discrete amplifier VCC Y High gain (85 dB) intermediate frequency strip Y Allows unregulated 3.0V–5.5V supply voltage range Y Power down mode for increased current savings Y System noise figure 5.4 dB (typ)

Applications

Y Digital European Cordless Telecommunications (DECT) Y Portable wireless communications (PCS/PCN, cordless) Y Wireless local area networks (WLANs) Y Other wireless communications systems TL/W/12493–1 This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. FastLockTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/W/12493–2 Pin No. Pin Name I/O

Description

Ð Power supply voltage input to mixer. Connect to VBAT MIXEROUT O IF output signal of the mixer. VCC Ð Power supply voltage input to mixer. Connect to VBAT GND Ð Ground. RFIN I RF input to the mixer. GND Ð Ground. Tx VREG O Supply voltage to external gain stage. VCC Ð Power supply voltage input to analog sections of doubler/PLL. Connect to VBAT GND Ð Ground. TxOUT O Doubler output. GND Ð Ground. VCC Ð Power supply voltage input to analog sections of doubler/PLL. Connect to VBAT GND Ð Ground. GND Ð Ground. fIN I RF Input to doubler and PLL. CE I Chip Enable. LOW powers down entire part. Before taking HIGH all mwire instructions should be loaded for R, N, F latches. Taking CE HIGH will power up the appropriate chip blocks depending on the state of bits F6, F7, F14, and F15. The CE state change will also load the PLL N and R counters to the correct divide ratios.

LMX3160 Pin Diagram (Continued) Pin No. Pin Name I/O Ð Power supply for charge pump. Do O Internal charge pump output. For connection to a loop filter for driving the input of an external VCO. VCC Ð Power supply input for CMOS section of PLL. Connect to VBAT GND Ground. Out 0/FLo I/O Programmable CMOS output. Can be used for FastLockTM output (See Programmable Modes). Out 1/Rx PD I/O Programmable CMOS output. Can be used for hardwire receiver power down (See Programmable Modes). Out 2/Tx PD I/O Programmable CMOS output. Can be used for hardwire transmitter power down (See Programmable Modes). PLL PD I PLL PD e LOW for PLL normal operations. PLL PD e HIGH for PLL power saving. Clock I High impedance CMOS clock input. Data I Binary serial data input. Data entered MSB first. High impedance CMOS input. LE I Load enable input. OSCIN I Oscillator input. S Field I DC compensation circuit enable. While LOW, the DC compensation circuit is enabled, and the threshold is updated through the DC compensation loop. While HIGH, the switch is opened, and the comparator is held by the external capacitor. RSSIOUT O Voltage output of the received signal strength indicator (RSSI). Thresh O Threshold level to external comparator. DC COMPIN I Input to DC compensation circuit. DISCOUT O Demodulated output of discriminator. GND Ð Ground. VCC Ð Power supply input to discriminator circuit. Connect to VBAT QUADIN I Quadrature input. VCC Ð Power supply input to limiter output stage. Connect to VBAT GND Ð Ground. LIMOUT O Limiter output to the quadrature tank. GND Ð Ground. VCC Ð Power supply input for limiter. Connect to VBAT LIMIN I IF input to the limiter. GND Ð Ground. GND Ð Ground. IFOUT O IF output to bandpass filter. VCC Ð Power supply input for IF amplifier. Connect to VBAT IFIN I IF input to IF amplifier. Rx VREG Ð Supply voltage to external LNA.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Power Supply Voltage (VCC) b0.3V to a6.5V VP b0.3V to a6.5V Voltage on Any Pin with GND e 0V (VI) b0.3V to a6.5V Storage Temperature Range (TS) b65§C to a150§C Lead Temp. (solder, 4 sec)(TL) a260§C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific perform- ance limits. For guaranteed specifications and test conditions, see the Elec- trical Characteristics. The guaranteed specifications apply only for the test conditions listed. Recommended Operating Conditions Supply Voltage (VCC) 3.0V to 5.5V Operating Temperature (TA) b10§C to a70§C

Electrical Characteristics

The following specifications are guaranteed over the recommended operating conditions unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Rx ICC Receive Mode Current Consumption Tx PLL Powered Down mA (Note 1) Tx ICC Transmit Mode Current Consumption Rx PLL Powered Down mA (Note 2) IPD Power Down Current Tx, Rx, PLL Off mA fRF RF Frequency Range 1.7 2.0 GHz fmax Maximum IF Input Frequency 120 150 MHz fmin Minimum IF Input Frequency MHz MIXER fIN e 1.9 GHz NF Single Side Band Noise Figure 5.9 dB GA Gain dB OIP3 Output Intercept Point dBm RF–RL RF Return Loss Zo e 50X dB IF–RL IF Return Loss Zo e 200X dB fIN–RF fIN to RF Isolation dB fIN–IF fIN to IF Isolation dB RF–IF RF to IF Isolation dB

Electrical Characteristics The following specifications are guaranteed over the recommended operating condi- tions unless otherwise specified (Continued) Symbol Parameter Conditions Min Typ Max Unit IF AMPLIFIER fIN e 120 MHz NF Noise Figure dB Av Gain dB OIP3 Output Intercept Point dBm ZIN Input Impedance 200 X ZOUT Output Impedance 200 X IF LIMITER fIN e 120 MHz NF IF Limiter Noise Figure dB Av Limiter Gain dB Sens Limiter/Disc. Sensitivity BER e 10b3 b65 dBm IFIN IF Limiter Input Impedance 200 X IFOUT IF Limiter Output Impedance 1000 X Vmax Maximum Input Voltage Level 500 mVPP VOUT Output Swing 500 mVPP Dynamic Range dB DISCRIMINATOR fIN e 120 MHz VOUT Discriminator Output Peak to Peak Voltage 250 400 mV VOS Disc. Output DC Voltage 1.4 1.7 V DISCOUT Disc. Output Impedance 150 X RSSI fIN e 120 MHz RSSI RSSI Dynamic Range dB RSSIOUT RSSI Output Voltage Pin e b85 dBm 0.1 0.25 0.4 V Pin e 0 dBm 1.15 1.5 1.8 V RSSI Slope Pin e b75 to b25 dBm mV/dB RSSI Linearity dB FREQUENCY DOUBLER fOUT e 1.89 GHz fIN Input Frequency Range 885 950 MHz VIN Input Signal Level ZIN e 200X b14 b11.5 dBm Zo Output Impedance X Fundamental Rejection (Note 3) VIN e 450 mVPP dB Harmonic Suppression (Note 3) VIN e 450 mVPP dB POUT Output Power b10 dBm

Electrical Characteristics The following specifications are guaranteed over the recommended operating condi- tions unless otherwise specified (Continued) Symbol Parameter Conditions Min Typ Max Unit FREQUENCY SYNTHESIZER VOSC Oscillator Sensitivity 0.5 1.0 VPP IDo-source Charge Pump Output Current Vdo e VP/2, Icpo e LOW (Note 4) b1.5 mA IDo-sink Vdo e VP/2, Icpo e LOW (Note 4) 1.5 mA IDo-source Vdo e VP/2, Icpo e HIGH (Note 4) b6.0 mA IDo-sink Vdo e VP/2, Icpo e HIGH (Note 4) 6.0 mA IDo-Tri 0.5 s Vdo s VP b0.5 b1.0 0.1 1.0 nA TA e 25§C VOH High-Level Output Voltage IOH e b1.0 mA VCC b0.4 V VOL Low-Level Output Voltage IOL e 1.0 mA 0.4 V VIH High-Level Input Voltage VCC b0.8 V VIL Low-Level Input Voltage 0.8 V IIN Input Current GND k VIN k VCC b1.0 1.0 mA tCS Data to Clock Set Up Time See Data Input Timing ns tCH Data to Clock Hold Time See Data Input Timing ns tCWH Clock Pulse Width High See Data Input Timing ns tCWL Clock Pulse Width Low See Data Input Timing ns tES Clock to Load Enable Set Up Time See Data Input Timing ns tEW Load Enable Pulse Width See Data Input Timing ns DC COMPENSATION SAMPLE AND HOLD CIRCUIT VOS Input Offset Voltage mV VI/O Input/Output Voltage Swing Centered at 1.5V 1.0 VPP RSH Sample and Hold Resistor 224 336 X DV Threshold Input Voltage Droop Chold e 2700 pF mV/ms Note 1: This includes 5 mA current sourced from the Rx VREG pin for the external receive LNA as shown in the application diagram. Note 2: This includes 5 mA current sourced from the Tx VREG pin for the external transmit buffer used before the power amplifier as shown in the application diagram. Note 3: Measured at the output of external gain stage. Note 4: See programmable modes for Icpo description.

TL/W/12493–3 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with PLL Functional Description The simplified block diagram below shows the 20-bit data register, 18-bit F latch, 12 bit N counter, and 6 bit R counter. TL/W/12493–4

PLL Functional Description (Continued) The data stream is clocked on the rising edge of LE into the DATA input, MSB first. The last two bits are the control bits. DATA is transferred into the counters as follows: Control Bits DATA Location N Counter R Counter X F Latch X e Dont Care Programmable Divider (N Counters) The N counter consists of the 6-bit swallow counter (A counter) and the 6-bit programmable counter (B counter). When the control bits are ‘‘00’’ data is transferred from the 20-bit shift register into two 6-bit latches. One latch sets the A counter while the other sets the B counter, MSB first. Serial data format is shown below. LSB MSB N10 N11 N12 X X X X X X Control Bits Divide Ratio of Programmable Divider, N Don’t Care 6-Bit Swallow Counter Divide Ratio (A Counter) Divide Ratio A Notes: Divide ratio: 0 to 63 B t A

6-Bit Programmable Counter Divide Ratio (B Counter) Divide Ratio B N12 N11 N10 Notes: Divide ratio: 3 to 63 B t A Programmable Reference Dividers (R Counters) If the control bits are ‘‘01’’ data is transferred from the 20-bit shift register into a latch which sets the 6-bit R counter. Serial data format is shown below. LSB MSB X X X X X X X X X X X X Control Bits Divide Ratio of Reference Divider Don’t Care Divide Ratio R Note: Divide ratio: 3 to 63 Pulse Swallow Function fvco e [(P x B) a A] x fosc/R fvco: Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of binary 6-bit programmable counter (3 to 63) Preset divide ratio of binary 6-bit swallow counter (0 s A s P, A s B) fOSC: Output frequency of the external reference frequency oscillator Preset divide ratio of binary 6-bit programmable reference counter (3 to 63) Preset modulus of dual modulus prescaler (32 or 64)

Receiver Functional Description The simplified block diagram below shows the mixer, IF amplifier, limiter, and discriminator. In addition, the DC compensation circuit, doubler, and voltage regulator (for external LNA) are shown. TL/W/12493–5 Note: Receiver power down can be controlled by software through the F Latch or hardwire through the Rx PD pin. This is determined by the state of F14 and F15 (See Programmable Modes). Transmitter Functional Description The simplified block diagram below shows the doubler and voltage regulator (for external transmit gain stage). TL/W/12493–6 Note: Transmitter power down can be controlled by software through the F Latch or hardwire through the Rx PD pin. This is determined by the state of F14 and F15 (See Programmable Modes). Programmable Function Latch (F Latch) If the control bits are ‘‘1X’’ data is transferred from the 20-bit shift register into the 18-bit F latch. Serial data format is shown below. LSB MSB F10 F11 F12 F13 F14 F15 F16 F17 F18 Control Bits

Several modes of operation can be programmed with the function register bits F1–F18, including the phase detector polarity, charge pump TRI-STATEÉ and CMOS outputs. In addition, software or hardwire power down modes may be selected with bits F14 and F15. The programmable modes are latched in when the control bits are: C1 e 1, C2 e X. Truth tables for the programmable modes are shown in Tables I–III. TABLE I. Programmable Modes Prescaler Mod Select (32/64) Phase Detector Polarity Charge Pump Current Charge Pump TRI-STATE Don’t Care Receive Section Power Down Transmit Section Power Down Out 0 CMOS Output/FastLock Output Out 1 CMOS Output/Receive Section Power Down Input F10 Out 2 CMOS Output/Transmit Section Power Down Input F11 Don’t Care F12 FastLock Auto/man select F13 Out 0 Normal CMOS/FastLock Switch F14 Mode Select. See Mode Select Table F15 Mode Select. See Mode Select Table F16 Auto FastLock Counter Bit Ý16 F17 Auto FastLock Counter Bit Ý32 F18 Auto FastLock Counter Bit Ý64 Functional Description Pre-scaler modules select. LOW selects 32/33 and HIGH selects 64/65. Phase Detector Polarity. F2 is used to reverse the polarity of the phase detector. Depending upon VCO characteristics, F2 should be set accordingly: When VCO characteristics are positive, F2 should be set HIGH; When VCO characteristics are negative, F2 should be set LOW. Charge pump current. LOW selects low charge pump current (1X Icpo). High selects HIGH charge pump current (4X Icpo). Charge Pump TRI-STATE. Don’t Care. F6–F7 Power down. When F14 e 0 and F15 e 0, F6 controls the state of the receive section and F7 controls the state of the transmit section. A LOW powers up the section while a HIGH powers down the section. F8–F10 CMOS Outputs. When F13 is LOW, F8 controls sets state of Out 0 (pin 21). When in normal power down mode (F14 e 0, F15 e 0), F9 and F10 sets the state of Out 1 (pin 22) and Out 2 (pin 23) respectively. F11 Don’t Care. F12 FastLock Auto/Manual Mode Select. When F13 HIGH, selects auto or manual FastLock mode. F13 Out 0 (pin 21) Normal/FastLock select. When LOW the state of Out 0 (pin 21) is controlled by F8. When HIGH Out 0 is used for FastLock. F14–F15 Power Down Mode Control. See Table III. F16–F18 FastLock Timeout Counter. See Table IV for counter values.

Table II. Mode Select Truth Table F6–F7 F8–F10 Pre-scaler Mod. Phase Det. polarity Icpo Do TRI-STATE Power Down Modes CMOS Outputs Negative LOW Normal Operation Powered UP LOW Positive HIGH TRI-STATE Powered Down HIGH TABLE IIIa. Power Down Modes Function F15 F14 Software Control Test Mode (See Note) Test Mode (See Note) Hardwire Power Down Note: Not used in application. TABLE IIIb. Power Control Modes High Low Software Receiver Off Receiver On Control Transmitter Off Transmitter On Hardwire Rx PD Receiver Off Reciever On Control Tx PD Transmitter Off Transmitter On PLDD PD PLL Off PLL On TABLE IV. Charge Pump Output, Out 0, and FastLock Decoding F12 F13 Function X Icpo e 1X, No FastLock, Out 0 e F8 X Icpo e 4X, No FastLock, Out 0 e F8 Icpo e 1X, Manual FastLock, Out 0 e FLo Icpo e 4X, Manual FastLock, Out 0 e FLo X Icpo e Set by Ý reference cycles present in F counter, Auto FastLock, Out 0 e FLo TABLE V. FastLock Timeout Counter Value Programming Time Out (Ý Reference Cycles) 104 120 F16 F17 F18 Example: To set FastLock timeout for 24 reference cycles, set F16 e HIGH, F17 e LOW, and F18 e LOW.

Typical Application Block Diagram TL/W/12493–7 Note 1: Connected when using FastLock. System: DECTÐSystem a3V Only Data Per Stage Cumulative Data Ý Component Gain N Fig OIP3 Ý Gain N Fig IIP3 OIP3 Filter/Switch b2.0 2.0 100.0 b2.0 2.0 97.9 95.9 Discrete LNA 10.0 2.0 7.0 8.0 4.0 b1.0 7.0 Filter b2.0 2.0 100.0 6.0 4.2 b1.0 5.0 Mixer 18.0 5.9 1.0 24.0 5.2 b23.0 1.0 SAW b11.0 11.0 100.0 13.0 5.3 b23.0 b10.0 IF Amplifier 25.0 4.0 57.0 38.0 5.4 b23.0 15.0 BPF (LC) b2.0 2.0 100.0 36.0 5.4 b23.0 13.0 IF Limiter 60.0 18.0 68.0 96.0 5.4 b29.2 66.8 SYSTEM CUMULATIVE VALUES Gain 96.0 dB N Fig 5.4 dB Sensitivity (@ 25§C) b93.1 dBm IIP3 b23.0 dBm Required Eb/No 14.0 dB OIP3 66.8 dbm Note: Assumes 50 dB attenuation of interferer by the SAW filter and 8 dB attenuation by the LC filter.

LMX3160 Single Chip Radio Transceiver Physical Dimensions (millimeters) 48-Lead (7mm x 7mm) Molded Plastic Quad Flat Package, JEDEC Order Number LMX3160 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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