LMX2331UTMX

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PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications

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LMX2332U NSC | Alldatasheet

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Technical content

Features

n Ultra Low Current Consumption n Upgrade and Compatible to LMX233xL Family n 2.7V to 5.5V Operation n Selectable Synchronous or Asynchronous Powerdown Mode: ICC-PWDN = 1 µA typical n Selectable Dual Modulus Prescaler: LMX2330U RF: 32/33 or 64/65 LMX2331U RF: 64/65 or 128/129 LMX2332U RF: 64/65 or 128/129 LMX2330U/31U/32U IF: 8/9 or 16/17 n Selectable Charge Pump TRI-STATE ® Mode n Programmable Charge Pump Current Levels RF and IF: 0.95 or 3.8 mA n Selectable Fastlock™ Mode for the RF Synthesizer n Push-Pull Analog Lock Detect Output n Available in 20-Pin TSSOP and 24-Pin Chip Scale Package (CSP)

Applications

(GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC, DCS) n Cordless Handsets (DECT, DCT) n Wireless Data n Cable TV Tuners Thin Shrink Small Outline Package (MTC20) Chip Scale Package (SLB24A) 10136680 10136681 PLLatinum™ is a trademark of National Semiconductor Corporation. July 2002 LMX2330U/LMX2331U/LMX2332U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications © 2002 National Semiconductor Corporation DS101366 www.national.com

LMX2330U/LMX2331U/LMX2332U www.national.com 2

Chip Scale Package (SLB) (Top View) Thin Shrink Small Outline Package (TM) (Top View) 10136639 10136602 Pin Descriptions Pin Name Pin No. 24-Pin CSP Pin No. 20-Pin TSSOP I/O Description VCC 24 1 — Power supply bias for the RF PLL analog and digital circuits. V CC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. V P RF 2 2 — RF PLL charge pump power supply. Must be ≥ VCC. Do RF 3 3 O RF PLL charge pump output. The output is connected to the external loop filter, which drives the input of the VCO. GND 4 4 — Ground for the RF PLL digital circuitry. fIN RF 5 5 I RF PLL prescaler input. Small signal input from the VCO. fIN RF 6 6 I RF PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX233xU RF PLL can be driven differentially when the bypass capacitor is omitted. GND 7 7 — Ground for the RF PLL analog circuitry. OSC in 8 8 I Reference oscillator input. The input has an approximate V CC/2 threshold and can be driven from an external CMOS or TTL logic gate. GND 10 9 — Ground for the IF PLL digital circuits, MICROWIRE ™ ,F oLD, and oscillator circuits. FoLD 11 10 O Programmable multiplexed output pin. Functions as a general purpose CMOS TRI-STATE output, RF/IF PLL push-pull analog lock detect output, N and R divider output or Fastlock output, which connects a parallel resistor to the external loop filter. Clock 12 11 I MICROWIRE Clock input. High impedance CMOS input. Data is clocked into the 22-bit shift register on the rising edge of Clock. Data 14 12 I MICROWIRE Data input. High impedance CMOS input. Binary serial data. The MSB of Data is shifted in first. The last two bits are the control bits. LE 15 13 I MICROWIRE Latch Enable input. High impedance CMOS input. When LE transitions HIGH, Data stored in the shift register is loaded into one of 4 internal control registers. GND 16 14 — Ground for the IF PLL analog circuitry. LMX2330U/LMX2331U/LMX2332U www.national.com3

Pin Descriptions (Continued) Pin Name Pin No. 24-Pin CSP Pin No. 20-Pin TSSOP I/O Description fIN IF 17 15 I IF PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX233xU IF PLL can be driven differentially when the bypass capacitor is omitted. f IN IF 18 16 I IF PLL prescaler input. Small signal input from the VCO. GND 19 17 — Ground for the IF PLL digital circuitry, MICROWIRE, F oLD, and oscillator circuits. Do IF 20 18 O IF PLL charge pump output. The output is connected to the external loop filter, which drives the input of the VCO. VP IF 22 19 — IF PLL charge pump power supply. Must be ≥ VCC. VCC 23 20 — Power supply bias for the IF PLL analog and digital circuits, MICROWIRE, FoLD, and oscillator circuits. V CC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. NC 1, 9, 13, 21 X — No connect.

Ordering Information

Model Temperature Range Package Description Packing NS Package Number LMX2330USLBX −40˚C to +85˚C Chip Scale Package (CSP) Tape and Reel

2500 Units Per Reel SLB24A

LMX2330UTM −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP)

73 Units Per Rail MTC20

LMX2330UTMX −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) Tape and Reel

2500 Units Per Reel MTC20

LMX2331USLBX −40˚C to +85˚C Chip Scale Package (CSP) Tape and Reel LMX2331UTM −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) LMX2331UTMX −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) Tape and Reel LMX2332USLBX −40˚C to +85˚C Chip Scale Package (CSP) Tape and Reel LMX2332UTM −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) LMX2332UTMX −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) Tape and Reel LMX2330U/LMX2331U/LMX2332U www.national.com 4

Notes: 1. A 64/65 or 128/129 prescaler ratio can be selected for the LMX2331U and LMX2332U RF synthesizers. A 32/33 or 64/65 prescaler ratio can be selected for the LMX2330U RF synthesizer. 2. V CC supplies power to the RF and IF prescalers, RF and IF feedback dividers, RF and IF reference dividers, RF and IF phase detectors, the OSC in buffer, MICROWIRE, and FoLD circuitry. 3. VP RF and VP IF supply power to the charge pumps. They can be run separately as long as V P RF ≥ VCC and VP IF ≥ VCC. LMX2330U/LMX2331U/LMX2332U www.national.com5

Absolute Maximum Ratings (Notes 1, 2, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage V CC to GND −0.3V to +6.5V VP RF to GND −0.3V to +6.5V VP IF to GND −0.3V to +6.5V Voltage on any pin to GND (V I) VI must be < +6.5V −0.3V to V CC+0.3V Storage Temperature Range (TS) −65˚C to +150˚C Lead Temperature (solder 4 s) (T L) +260˚C TSSOP θJA Thermal Impedance 114.5˚C/W CSP θJA Thermal Impedance 112˚C/W Recommended Operating Conditions (Note 1) Power Supply Voltage VCC to GND +2.7V to +5.5V VP RF to GND V CC to +5.5V VP IF to GND V CC to +5.5V Operating Temperature (TA) −40˚C to +85˚C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate condi- tions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test condi- tions, refer to the Electrical Characteristics section. The guaranteed specifi- cations apply only for the conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating <2 kV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected work stations. Note 3: G N D=0 V

Electrical Characteristics

VCC =V P R F=V P IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value UnitsMin Typ Max ICC PARAMETERS ICCR F+I F Power Supply Current, RF + IF Synthesizers LMX2330U Clock, Data and LE = GND OSC in = GND PWDN RF Bit = 0 PWDN IF Bit = 0 3.3 4.3 mA LMX2331U 2.9 3.8 mA LMX2332U 2.5 3.3 mA I CCRF Power Supply Current, RF Synthesizer Only LMX2330U Clock, Data and LE = GND OSC in = GND PWDN RF Bit = 0 PWDN IF Bit = 1 2.3 3.0 mA LMX2331U 1.9 2.5 mA LMX2332U 1.5 2.0 mA I CCIF Power Supply Current, IF Synthesizer Only LMX233xU Clock, Data and LE = GND OSC in = GND PWDN RF Bit = 1 PWDN IF Bit = 0 1.0 1.3 mA I CC-PWDN Powerdown Current LMX233xU Clock, Data and LE = GND OSCin = GND PWDN RF Bit = 1 PWDN IF Bit = 1 1.0 10.0 µA RF SYNTHESIZER PARAMETERS f IN RF RF Operating Frequency LMX2330U 500 2500 MHz LMX2331U 200 2000 MHz LMX2332U 100 1200 MHz N RF RF N Divider Range Prescaler = 32/33 (Note 4) 96 65631 Prescaler = 64/65 (Note 4) 192 131135 Prescaler = 128/129 (Note 4) 384 262143 RRF RF R Divider Range 3 32767 FφRF RF Phase Detector Frequency 10 MHz LMX2330U/LMX2331U/LMX2332U www.national.com 6

Electrical Characteristics (Continued) VCC =V P R F=V P IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value UnitsMin Typ Max RF SYNTHESIZER PARAMETERS Pf IN RF RF Input Sensitivity 2.7V ≤ VCC ≤ 3.0V (Note 5) −15 0 dBm 3.0 < VCC ≤ 5.5V (Note 5) −10 0 dBm IDo RF SOURCE RF Charge Pump Output Source Current VDo R F=V P RF/2 IDo RF Bit = 0 (Note 6) -0.95 mA VDo R F=V P RF/2 IDo RF Bit = 1 (Note 6) -3.80 mA IDo RF SINK RF Charge Pump Output Sink Current VD o R F=V P RF/2 IDo RF Bit = 0 (Note 6) 0.95 mA VDo R F=V P RF/2 IDo RF Bit = 1 (Note 6) 3.80 mA IDo RF TRI-STATE RF Charge Pump Output TRI-STATE Current 0.5V ≤ VDo RF ≤ VP RF - 0.5V (Note 6) -2.5 2.5 nA IDo RF SINK Vs ID o RF SOURCE RF Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch VD o R F=V P RF/2 TA = +25˚C (Note 7) 31 0 % IDo RF Vs VD o RF RF Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage 0.5V ≤ VD o RF ≤ VP RF - 0.5V TA = +25˚C (Note 7) 10 15 % IDo RF Vs T A RF Charge Pump Output Current Magnitude Variation Vs Temperature VD o R F=V P RF/2 (Note 7) 10 % IF SYNTHESIZER PARAMETERS fIN IF IF Operating Frequency LMX2330U 45 600 MHz LMX2331U 45 600 MHz LMX2332U 45 600 MHz N IF IF N Divider Range Prescaler = 8/9 (Note 4) 24 16391 Prescaler = 16/17 (Note 4) 48 32767 RIF IF R Divider Range 3 32767 FφIF IF Phase Detector Frequency 10 MHz PfIN IF IF Input Sensitivity 2.7V ≤ VCC ≤ 5.5V (Note 5) -10 0 dBm LMX2330U/LMX2331U/LMX2332U www.national.com7

Electrical Characteristics (Continued) VCC =V P R F=V P IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value UnitsMin Typ Max IF SYNTHESIZER PARAMETERS ID o IF SOURCE IF Charge Pump Output Source Current VDo I F=V P IF/2 IDo IF Bit = 0 (Note 6) -0.95 mA VDo I F=V P IF/2 IDo IF Bit = 1 (Note 6) -3.80 mA IDo IF SINK IF Charge Pump Output Sink Current VD o I F=V P IF/2 IDo IF Bit = 0 (Note 6) 0.95 mA VDo I F=V P IF/2 IDo IF Bit = 1 (Note 6) 3.80 mA IDo IF TRI-STATE IF Charge Pump Output TRI-STATE Current 0.5V ≤ VDo IF ≤ VP IF - 0.5V (Note 6) -2.5 2.5 nA IDo IF SINK Vs ID o IF SOURCE IF Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch VD o I F=V P IF/2 TA = +25˚C (Note 7) 31 0 % IDo IF Vs VD o IF IF Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage 0.5V ≤ VD o IF ≤ VP IF - 0.5V TA = +25˚C (Note 7) 10 15 % IDo IF Vs T A IF Charge Pump Output Current Magnitude Variation Vs Temperature VD o I F=V P IF/2 (Note 7) 10 % OSCILLATOR PARAMETERS FOSC Oscillator Operating Frequency 2 40 MHz VOSC Oscillator Sensitivity (Note 8) 0.5 V CC VPP IOSC Oscillator Input Current V OSC =V CC = 5.5V 100 µA VOSC = 0V, VCC = 5.5V -100 µA DIGITAL INTERFACE (Data, LE, Clock, F oLD) VIH High-Level Input Voltage 0.8 V CC V VIL Low-Level Input Voltage 0.2 VCC V IIH High-Level Input Current V IH =V CC = 5.5V −1.0 1.0 µA IIL Low-Level Input Current V IL = 0V, V CC = 5.5V −1.0 1.0 µA VOH High-Level Output Voltage I OH = −500 µA V CC − 0.4 V VOL Low-Level Output Voltage I OL = 500 µA 0.4 V MICROWIRE INTERFACE t CS Data to Clock Set Up Time (Note 9) 50 ns tCH Data to Clock Hold Time (Note 9) 10 ns tCWH Clock Pulse Width HIGH (Note 9) 50 ns tCWL Clock Pulse Width LOW (Note 9) 50 ns tES Clock to Load Enable Set Up Time (Note 9) 50 ns tEW Latch Enable Pulse Width (Note 9) 50 ns LMX2330U/LMX2331U/LMX2332U www.national.com 8

Electrical Characteristics (Continued) VCC =V P R F=V P IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value UnitsMin Typ Max PHASE NOISE CHARACTERISTICS L N(f) IF IF Synthesizer Normalized Phase Noise Contribution (Note 10) TCXO Reference Source ID o IF Bit = 1 -212.0 dBc/ Hz L(f) IF IF Synthesizer Single Side Band Phase Noise Measured LMX233xU f IN IF = 200 MHz f = 1 kHz Offset F φIF = 200 kHz Loop Bandwidth = 18 kHz N = 1000 F OSC =1 0M H z VOSC = 0.632 V PP IDo IF Bit = 1 PWDN RF Bit = 1 T A = +25˚C (Note 11) -99.00 dBc/ Hz Note 4: Some of the values in this range are illegal divide ratios (B < A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N ≥ P * (P−1), where P is the value of the prescaler selected. Note 5: Refer to the LMX233xU f IN Sensitivity Test Setup section Note 6: Refer to the LMX233xU Charge Pump Test Setup section Note 7: Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made. Note 8: Refer to the LMX233xU OSC in Sensitivity Test Setup section Note 9: Refer to the LMX233xU Serial Data Input Timing section Note 10: Normalized Phase Noise Contribution is defined as : L N(f) = L(f) − 20 log (N) − 10 log (F φ), where L(f) is defined as the single side band phase noise measured at an offset frequency, f, ina1H z bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL’s loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and F φ is the RF/IF phase detector comparison frequency. Note 11: The synthesizer phase noise is measured with the LMX2330TMEB/LMX2330SLBEB Evaluation boards and the HP8566B Spectrum Analyzer. LMX2330U/LMX2331U/LMX2332U www.national.com 10

Typical Performance Characteristics Sensitivity LMX2330U fIN RF Input Power Vs Frequency VCC =V P RF = 3.0V 10136642 LMX2330U fIN RF Input Power Vs Frequency VCC =V P RF = 5.5V 10136643 LMX2330U/LMX2331U/LMX2332U www.national.com11

Typical Performance Characteristics Sensitivity (Continued) LMX2331U fIN RF Input Power Vs Frequency VCC =V P RF = 3.0V 10136644 LMX2331U fIN RF Input Power Vs Frequency VCC =V P RF = 5.5V 10136645 LMX2330U/LMX2331U/LMX2332U www.national.com 12

Typical Performance Characteristics Sensitivity (Continued) LMX2332U fIN RF Input Power Vs Frequency VCC =V P RF = 3.0V 10136646 LMX2332U fIN RF Input Power Vs Frequency VCC =V P RF = 5.5V 10136647 LMX2330U/LMX2331U/LMX2332U www.national.com13

Typical Performance Characteristics Sensitivity (Continued) LMX233xU fIN IF Input Power Vs Frequency VCC =V P IF = 3.0V 10136648 LMX233xU fIN IF Input Power Vs Frequency VCC =V P IF = 5.5V 10136649 LMX2330U/LMX2331U/LMX2332U www.national.com 14

Typical Performance Characteristics Sensitivity (Continued) LMX233xU OSCin Input Voltage Vs Frequency VCC = 3.0V 10136652 LMX233xU OSCin Input Voltage Vs Frequency VCC = 5.5V 10136653 LMX2330U/LMX2331U/LMX2332U www.national.com15

Typical Performance Characteristics Charge Pump LMX233xU RF Charge Pump Sweeps 10136660 LMX2330U/LMX2331U/LMX2332U www.national.com 16

Typical Performance Characteristics Charge Pump (Continued) LMX233xU IF Charge Pump Sweeps 10136661 LMX2330U/LMX2331U/LMX2332U www.national.com17

Typical Performance Characteristics Input Impedance LMX233xU TSSOP fIN RF Input Impedance VCC= 3.0V, T A = +25˚C LMX233xU TSSOP fIN RF Input Impedance VCC= 5.5V, T A = +25˚C 10136666 10136667 LMX233xU CSP fIN RF Input Impedance VCC= 3.0V, T A = +25˚C LMX233xU CSP fIN RF Input Impedance VCC= 5.5V, T A = +25˚C 10136668 10136669 LMX2330U/LMX2331U/LMX2332U www.national.com 18

Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP and LMX233xU CSP f IN RF Input Impedance Table 10136670 LMX2330U/LMX2331U/LMX2332U www.national.com19

Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP fIN IF Input Impedance VCC= 3.0V, T A = +25˚C LMX233xU TSSOP fIN IF Input Impedance VCC= 5.5V, T A = +25˚C 10136671 10136672 LMX233xU CSP fIN IF Input Impedance VCC= 3.0V, T A = +25˚C LMX233xU CSP fIN IF Input Impedance VCC= 5.5V, T A = +25˚C 10136673 10136674 LMX2330U/LMX2331U/LMX2332U www.national.com 20

Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP and LMX233xU CSP f IN IF Input Impedance Table 10136675 LMX2330U/LMX2331U/LMX2332U www.national.com21

Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP OSCin Input Impedance Vs Frequency TA = +25˚C 10136676 LMX233xU CSP OSCin Input Impedance Vs Frequency TA = +25˚C 10136677 LMX2330U/LMX2331U/LMX2332U www.national.com 22

Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP and LMX233xU CSP OSC in Input Impedance Table 10136678 LMX2330U/LMX2331U/LMX2332U www.national.com23

Charge Pump Current Specification Definitions 10136637 I1 = Charge Pump Sink Current at VD o =V P − ∆V I2 = Charge Pump Sink Current at VD o =V P/2 I3 = Charge Pump Sink Current at VD o = ∆V I4 = Charge Pump Source Current at VD o =V P − ∆V I5 = Charge Pump Source Current at VD o =V P/2 I6 = Charge Pump Source Current at VD o = ∆V ∆V = Voltage offset from the positive and negative rails. Dependent on the VCO tuning range relative to V CC and GND. Typical values are between 0.5V and 1.0V. VP refers to either V P RF or VP IF VDo refers to either VD o RF or VDo IF IDo refers to either ID o RF or IDo IF Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage 10136663 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch 10136664 Charge Pump Output Current Magnitude Variation Vs Temperature 10136665 LMX2330U/LMX2331U/LMX2332U www.national.com 24

LMX233xU Charge Pump Test Setup 10136650 The block diagram above illustrates the setup required to measure the LMX233xU device’s RF charge pump sink cur- rent. The same setup is used for a LMX2330TMEB Evalua- tion Board. The IF charge pump measurement setup is similar to the RF charge pump measurement setup. The purpose of this test is to assess the functionality of the RF charge pump. This setup uses an open loop configuration. A power supply is connected to V cc and swept from 2.7V to 5.5V. By means of a signal generator, a 10 MHz signal is typically applied to the f IN RF pin. The signal is one of two inputs to the phase detector. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSC in pin is tied to V cc. This establishes the other input to the phase detector. Alter- natively, this input can be tied directly to the ground plane. With the D o RF pin connected to a Semiconductor Param- eter Analyzer in this way, the sink, source, and TRI-STATE currents can be measured by simply toggling the Phase Detector Polarity and Charge Pump State states in Code Loader. Similarly, the LOW and HIGH currents can be mea- sured by switching the Charge Pump Gain’sstate between 1X and 4X in Code Loader. Let F r represent the frequency of the signal applied to the OSCin pin, which is simply zero in this case (DC), and let F p represent the frequency of the signal applied to the f IN RF pin. The phase detector is sensitive to the rising edges of F r and Fp. Assuming positive VCO characteristics; the charge pump turns ON and sinks current when the first rising edge of F p is detected. Since F r has no rising edge, the charge pump continues to sink current indefinitely. Toggling the Phase Detector Polarity state to negative VCO characteristics allows the measurement of the RF charge pump source current. Likewise, selectingTRI-STATE (TRI-STATE ID o RF Bit = 1) for Charge Pump State in Code Loader facilitates the measurement of the TRI-STATE cur- rent. The measurements are repeated at different temperatures, namely T A = -40˚C, +25˚C, and +85˚C. LMX2330U/LMX2331U/LMX2332U www.national.com25

Test Setups (Continued) LMX233xU fIN Sensitivity Test Setup 10136640 The block diagram above illustrates the setup required to measure the LMX233xU device’s RF input sensitivity level. The same setup is used for a LMX2330TMEB Evaluation Board. The IF input sensitivity test setup is similar to the RF sensitivity test setup. The purpose of this test is to measure the acceptable signal level to the f IN RF input of the PLL chip. Outside the acceptable signal range, the feedback divider begins to divide incorrectly and miscount the frequency. The setup uses an open loop configuration. A power supply is connected to V cc and swept from 2.7V to 5.5V. The IF PLL is powered down (PWDN IF Bit = 1). By means of a signal generator, an RF signal is applied to the f IN RF pin. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSC in pin is tied to V cc. The N value is typically set to 10000 in Code Loader, i.e. RF N_CNTRB Word = 156 and RF N_CNTRA Word = 16 for PRE RF Bit = 1 (LMX2330U) or PRE RF = 0 (LMX2331U and LMX2332U). The feedback divider output is routed to the F oLD pin by selecting the RF PLL N Divider Output word (FoLD Word = 6 or 14) in Code Loader. A Universal Counter is connected to the FoLD pin and tied to the 10 MHz reference output of the signal generator. The output of the feedback divider is thus monitored and should be equal to f IN R F/N . The fIN RF input frequency and power level are then swept with the signal generator. The measurements are repeated at different temperatures, namely T A = -40˚C, +25˚C, and +85˚C. Sensitivity is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz. The power attenuation from the cable and the 3 dB pad must be ac- counted for. The feedback divider will actually miscount if too much or too little power is applied to the f IN RF input. Therefore, the allowed input power level will be bounded by the upper and lower sensitivity limits. In a typical application, if the power level to the f IN RF input approaches the sensi- tivity limits, this can introduce spurs and degradation in phase noise. When the power level gets even closer to these limits, or exceeds it, then the RF PLL loses lock. LMX2330U/LMX2331U/LMX2332U www.national.com 26

Test Setups (Continued) LMX233xU OSCin Sensitivity Test Setup 10136641 The block diagram above illustrates the setup required to measure the LMX233xU device’s OSC in buffer sensitivity level. The same setup is used for a LMX2330TMEB Evalu- ation Board. This setup is similar to the f IN sensitivity setup except that the signal generator is now connected to the OSC in pin and both fIN pins are tied to VCC. The 51 Ω shunt resistor matches the OSCin input to the signal generator. The R counter is typically set to 1000, i.e. RF R_CNTR Word = 1000 or IF R_CNTR Word = 1000. The reference divider output is routed to the F oLD pin by selecting the RF PLL R Divider Output word (FoLD Word = 2 or 10) or the IF PLL R Divider Output word (FoLD Word = 1 or 9) in Code Loader. Similarly, a Universal Counter is connected to the F oLD pin and is tied to the 10 MHz reference output from the signal generator. The output of the reference divider is monitored and should be equal to OSC in/ RF R_CNTR or OSC in/I F R_CNTR. Again, V CC is swept from 2.7V to 5.5V. The OSC in input frequency and voltage level are then swept with the signal generator. The measurements are repeated at different tem- peratures, namely T A = -40˚C, +25˚C, and +85˚C. Sensitivity is reached when the frequency error of the divided input signal is greater than or equal to 1 Hz. LMX2330U/LMX2331U/LMX2332U www.national.com27

Test Setups (Continued) LMX233xU fIN Impedance Test Setup 10136679 The block diagram above illustrates the setup required to measure the LMX233xU device’s RF input impedance. The IF input impedance and reference oscillator impedance set- ups are very much similar. The same setup is used for a LMX2330TMEB Evaluation Board. Measuring the device’s input impedance facilitates the design of appropriate match- ing networks to match the PLL to the VCO, or in more critical situations, to the characteristic impedance of the printed circuit board (PCB) trace, to prevent undesired transmission line effects. Before the actual measurements are taken, the Network Analyzer needs to be calibrated, i.e. the error coefficients need to be calculated. Therefore, three standards will be used to calculate these coefficients: an open, short and a matched load. A 1-port calibration is implemented here. To calculate the coefficients, the PLL chip is first removed from the PCB. The Network Analyzer port is then connected to the RF OUT connector of the evaluation board and the desired operating frequency is set. The typical frequency range selected for the LMX233xU device’s RF synthesizer is from 100 MHz to 2500 MHz. The standards will be located down the length of the RF OUT transmission line. The trans- mission line adds electrical length and acts as an offset from the reference plane of the Network Analyzer; therefore, it must be included in the calibration. Although not shown, 0 Ω resistors are used to complete the RF OUT transmission line (trace). To implement an open standard, the end of the RF OUT trace is simply left open. To implement ashort standard, a 0 Ω resistor is placed at the end of the RF OUT transmission line. Last of all, to implement a matched load standard, two 100 Ω resistors in parallel are placed at the end of the RF OUT transmission line. The Network Analyzer calculates the calibration coefficients based on the measured S 11 param- eters. With this all done, calibration is now complete. The PLL chip is then placed on the PCB. A power supply is connected to VCC and swept from 2.7V to 5.5V. The OSC in pin is tied to the ground plane. Alternatively, the OSC in pin can be tied to V CC. In this setup, the complementary input (fIN RF) is AC coupled to ground. With the Network Analyzer still connected to RF OUT, the measured f IN RF impedance is displayed. Note: The impedance of the reference oscillator is measured when the oscillator buffer is powered up (PWDN RF Bit = 0 or PWDN IF Bit = 0), and when the oscillator buffer is powered down (PWDN RF Bit = 1 and PWDN IF Bit = 1). LMX2330U/LMX2331U/LMX2332U www.national.com 28

LMX233xU Serial Data Input Timing 10136610 Notes: 1. Data is clocked into the 22-bit shift register on the rising edge of Clock 2. The MSB of Data is shifted in first. LMX2330U/LMX2331U/LMX2332U www.national.com29

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthe- sizer such as the National Semiconductor LMX233xU, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, cur- rent mode charge pump, programmable reference R and feedback N frequency dividers. The VCO frequency is es- tablished by dividing the crystal reference signal down via the reference divider to obtain a comparison reference fre- quency. This reference signal, F r, is then presented to the input of a phase/frequency detector and compared with the feedback signal, F p, which was obtained by dividing the VCO frequency down by way of the feedback divider. The phase/frequency detector measures the phase error be- tween the F r and Fp signals and outputs control signals that are directly proportional to the phase error. The charge pump then pumps charge into or out of the loop filter based on the magnitude and direction of the phase error. The loop filter converts the charge into a stable control voltage for the VCO. The phase/frequency detector’s function is to adjust the voltage presented to the VCO until the feedback signal’s frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO fre- quency will be N times that of the comparison frequency, where N is the feedback divider ratio.

1.1 REFERENCE OSCILLATOR INPUT

The reference oscillator frequency for both the RF and IF PLLs is provided from an external reference via the OSC in pin. The reference buffer circuit supports input frequencies from 5 to 40 MHz with a minimum input sensitivity of 0.5 V PP. The reference buffer circuit has an approximate V CC/2 input threshold and can be driven from an external CMOS or TTL logic gate. Typically, the OSC in pin is connected to the output of a crystal oscillator.

1.2 REFERENCE DIVIDERS (R COUNTERS)

The reference dividers divide the reference input signal, OSCin, by a factor of R. The output of the reference divider circuits feeds the reference input of the phase detector. This reference input to the phase detector is often referred to as the comparison frequency. The divide ratio should be chosen such that the maximum phase comparison frequency (F φRF or FφIF) of 10 MHz is not exceeded. The RF and IF reference dividers are each comprised of 15-bit CMOS binary counters that support a continuous in- teger divide ratio from 3 to 32767. The RF and IF reference divider circuits are clocked by the output of the reference buffer circuit which is common to both.

1.3 PRESCALERS

IN RF (fIN IF) and fIN RF (fIN IF) input pins drive the input of a bipolar, differential-pair amplifier. The output of the bi- polar, differential-pair amplifier drives a chain of ECL D-type flip-flops in a dual modulus configuration. The output of the prescaler is used to clock the subsequent feedback dividers. The RF and IF PLL complementary inputs can be driven differentially, or the negative input can be AC coupled to ground through an external capacitor for single ended con- figuration. A 32/33 or a 64/65 prescale ratio can be selected for the 2.5 GHz LMX2330U RF synthesizer. A 64/65 or a 128/129 prescale ratio can be selected for both the LMX2331U and LMX2332U RF synthesizers. The IF circuitry contains an 8/9 or a 16/17 prescaler.

1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N

COUNTERS) The programmable feedback dividers operate in concert with the prescalers to divide the input signal, f IN, by a factor of N. The output of the programmable reference divider is pro- vided to the feedback input of the phase detector circuit. The divide ratio should be chosen such that the maximum phase comparison frequency (F φRF or F φIF) of 10 MHz is not ex- ceeded. The programmable feedback divider circuit is comprised of an A counter (swallow counter) an d a B counter (program- mble binary counter). The RF N_CNTRA counter is a 7-bit CMOS swallow counter, programmable from 0 to 127. The IF N_CNTRA counter is also a 7-bit CMOS swallow counter, but programmable from 0 to 15. The three most significant bits are ’don’t cares’ in this case. The RF N_CNTRB and IF N_CNTRB counters are both 11-bit CMOS binary counters, programmable from 3 to 2047. A continuous integer divide ratio is achieved if N ≥ P * (P−1), where P is the value of the prescaler selected. Divide ratios less than the minimum con- tinuous divide ratio are achievable as long as the binary programmable counter value is greater than the swallow counter value (N_CNTRB ≥ N_CNTRA). Refer to Sections the N_CNTRA and N_CNTRB counters. The following equa- tions are useful in determining and programming a particular value of N: N = (P x N_CNTRB) + N_CNTRA f IN =NxF φ Definitions: Fφ: RF or IF phase detector comparison frequency fIN: RF or IF input frequency N_CNTRA: RF or IF A counter value N_CNTRB: RF or IF B counter value P: Preset modulus of the dual moduIus prescaler LMX2330U RF synthesizer: P = 32 or 64 LMX2331U RF synthesizer: P = 64 or 128 LMX2332U RF synthesizer: P = 64 or 128 LMX233xU IF synthesizer: P = 8 or 16

1.5 PHASE/FREQUENCY DETECTORS

The RF and IF phase/frequency detectors are driven from their respective N and R counter outputs. The maximum frequency for both the RF and IF phase detector inputs is 10 MHz. The phase/frequency detector outputs control the re- spective charge pumps. The polarity of the pump-up or pump-down control signals are programmed using the PD- _POL RF or PD_POL IF control bits, depending on whether the RF or IF VCO characteristics are positive or negative. phase/frequency detectors have a detection range of −2 π to +2π. The phase/frequency detectors also receive a feedback signal from the charge pump in order to eliminate dead zone. LMX2330U/LMX2331U/LMX2332U www.national.com 30

1.0 Functional Description (Continued)

PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 10136611 Notes: 1. The minimum width of the pump-up and pump-down current pulses occur at the D o RF or Do IF pins when the loop is phase locked. 2. The diagram assumes positive VCO characteristics, i.e. PD_POL RF or PD_POL IF = 1. 3. F r is the phase detector input from the reference divider (R counter). 4. F p is the phase detector input from the programmable feedback divder (N counter). 5. D o refers to either the RF or IF charge pump output.

1.6 CHARGE PUMPS

The charge pump directs charge into or out of an external loop filter. The loop filter converts the charge into a stable control voltage which is applied to the tuning input of the VCO. The charge pump steers the VCO control voltage towards V P RF or VP IF during pump-up events and towards GND during pump-down events. When locked, D o RF or Do IF are primarily in a TRI-STATE mode with small corrections occuring at the phase comparator rate. The charge pump output current magnitude can be selected by toggling theID o RF or IDo IF control bits.

1.7 MICROWIRE SERIAL INTERFACE

The programmable register set is accessed via the MI- CROWIRE serial interface. The interface is comprised of three signal pins: Clock, Data and LE (Latch Enable). Serial data is clocked into the 22-bit shift register on the rising edge of Clock. The last two bits decode the internal control regis- ter address. When LE transitions HIGH, data stored in the shift register is loaded into one of four control registers depending on the state of the address bits. The MSB of Data is loaded in first. The synthesizers can be programmed even in power down mode. A complete programming description is provided in Section 2.0 Programming Description .

1.8 MULTI-FUNCTION OUTPUTS

The LMX233xU device’s F oLD output pin is a multi-function output that can be configured as the RF FastLock output, a push-pull analog lock detect output, counter reset, or used to monitor the output of the various reference divider (R counter) or feedback divider (N counter) circuits. The F oLD control word is used to select the desired output function. When the PLL is in powerdown mode, the F oLD output is pulled to a LOW state. A complete programming description of the multi-function output is provided in Section 2.8 F oLD.

1.8.1 Push-Pull Analog Lock Detect Output

An analog lock detect status generated from the phase detector is available on the F oLD output pin if selected. The lock detect output goes HIGH when the charge pump is inactive. It goes LOW when the charge pump is active during a comparison cycle. When viewed with an oscilloscope, narrow negative pulses are observed when the charge pump turns on. The lock detect output signal is a push-pull con- figuration. Three separate lock detect signals are routed to the multi- plexer. Two of these monitor the ‘lock’ status of the individual synthesizers. The third detects the condition when both the RF and IF synthesizers are in a ‘locked state’. External circuitry however, is required to provide a steady DC signal to indicate when the PLL is in a locked state. Refer to Section 2.8 F oLD for details on how to program the different lock detect options. LMX2330U/LMX2331U/LMX2332U www.national.com31

1.8.2 Open Drain FastLock Output

The LMX233xU Fastlock feature allows faster loop response time during lock aquisition. The loop response time (lock time) can be approximately halved if the loop bandwidth is doubled. In order to achieve this, the same gain/ phase relationship at twice the loop bandwidth must be maintained. This can be achieved by increasing the charge pump current from 0.95 mA (ID o RF Bit = 0) in the steady state mode, to 3.8 mA (IDo RF Bit = 1) in Fastlock. When the FoLD output is configured as a FastLock output, an open drain device is enabled. The open drain device switches in a parallel resis- tor R2’ to ground, of equal value to resistor R2 of the external loop filter. The loop bandwidth is effectively doubled and stability is maintained. Once locked to the correct frequency, the PLL will return to a steady state condition. Refer to Section 2.8 F oLD for details on how to configure the F oLD output to an open drain Fastlock output.

1.8.3 Counter Reset

Three separate counter reset functions are provided. When the FoLD is programmed to Reset IF Counters, both the IF feedback divider and the IF reference divider are held at their load point. When the Reset RF Counters is programmed, both the RF feedback divider and the RF reference divider are held at their load point. When the Reset All Counters mode is enabled, all feedback dividers and reference divid- ers are held at their load point. When the device is pro- grammed to normal operation, both the feedback divider and reference divider are enabled and resume counting in ‘close’ alignment to each other. Refer toSection 2.8 F oLD for more details.

1.8.4 Reference Divider and Feedback Divider Output

The outputs of the various N and R dividers can be moni- tored by selecting the appropriate FoLD word. This is essen- tial when performing OSCin or fIN sensitivity measurements. Refer to the Test Setups section for more details. Refer to Section 2.8 F oLD for more details on how to route the appropriate divider output to the F oLD pin.

1.9 POWER CONTROL

Each synthesizer in the LMX233xU device is individually power controlled by device powerdown bits. The powerdown word is comprised of the PWDN RF (PWDN IF ) bit, in conjuction with the TRI-STATE ID o RF (TRI-STATE IDo IF) bit. The powerdown control word is used to set the operating and 2.7.4 for details on how to program the RF or IF power- down bits. When either the RF synthesizer or the IF synthesizer enters the powerdown mode, the respective prescaler, phase de- tector, and charge pump circuit are disabled. The D o RF (Do IF), fIN RF (fIN IF), and fIN RF (fIN IF) pins are all forced to a high impedance state. The reference divider and feedback divider circuits are held at the load point during powerdown. The oscillator buffer is disabled when both the RF and IF synthesizers are powered down. The OSC in pin is forced to a HIGH state through an approximate 100 k Ω resistance when this condition exists. When either synthesizer is acti- vated, the respective prescaler, phase detector, charge pump circuit, and the oscillator buffer are all powered up. The feedback divider, and the reference divider are held at load point. This allows the reference oscillator, feedback divider, reference divider and prescaler circuitry to reach proper bias levels. After a finite delay, the feedback and reference dividers are enabled and they resume counting in ‘close’ alignment (the maximum error is one prescaler cycle). The MICROWIRE control register remains active and ca- pable of loading and latching data while in the powerdown mode. Synchronous Powerdown Mode In this mode, the powerdown function is gated by the charge pump. When the device is configured for synchronous pow- erdown, the device will enter the powerdown mode upon completion of the next charge pump pulse event. Asynchronous Powerdown Mode In this mode, the powerdown function is NOT gated by the completion of a charge pump pulse event. When the device is configured for asynchronous powerdown, the part will go into powerdown mode immediately. TRI-STATE IDo PWDN Operating Mode 0 0 PLL Active, Normal Operation 1 0 PLL Active, Charge Pump Output in High Impedance State 0 1 Synchronous Powerdown 1 1 Asynchronous Powerdown Notes: 1. TRI-STATE ID o refers to either the TRI-STATE IDo RF or TRI-STATE IDo IF bit . 2. PWDN refers to either the PWDN RF or PWDN IF bit. LMX2330U/LMX2331U/LMX2332U www.national.com 32

2.0 Programming Description

2.1 MICROWIRE INTERFACE

The 22-bit shift register is loaded via the MICROWIRE interface. The shift register consists of a 20-bitData[19:0] Fieldand a 2-bit Address[1:0] Field as shown below. The Address Field is used to decode the internal control register address. When LE transitions HIGH, data stored in the shift register is loaded into one of 4 control registers depending on the state of the address bits. The MSB of Data is loaded in first. The Data Field assignments are shown inSection 2.3 CONTROL REGISTER CONTENT MAP. MSB LSB Data[19:0] Address[1:0] 21 2 1 0

2.2 CONTROL REGISTER LOCATION

The address bits Address[1:0] decode the internal register address. The table below shows how the address bits are mapped into the target control register. Address[1:0] Target Field Register 0 0 IF R 0 1 RF R 1 0 IF N 1 1 RF N

2.3 CONTROL REGISTER CONTENT MAP

The control register content map describes how the bits within each control register are allocated to specific control functions. LMX2330U/LMX2331U/LMX2332U www.national.com33

2.0 Programming Description (Continued)

Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Field Address Field IF R FoLD0 F oLD2 TRI- STATE IDo IF IDo IF PD_ POL IF IF R_CNTR[14:0] 0 0 RF R FoLD1 F oLD3 TRI- STATE IDo RF IDo RF PD_ POL RF RF R_CNTR[14:0] 0 1 IF N PWDN IF PRE IF IF N_CNTRB[10:0] IF N_CNTRA[6:0] 1 0 RF N PWDN RF PRE RF RF N_CNTRB[10:0] RF N_CNTRA[6:0] 1 1 LMX2330U/LMX2331U/LMX2332U www.national.com 34

2.4 IF R REGISTER

The IF R register contains the IF R_CNTR, PD_POL IF, ID o IF, and TRI-STATE IDo IF control words, in addition to two bits that compose the FoLD control word. The detailed descriptions and programming information for each control word is discussed in the following sections. IF R_CNTR[14:0] Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Data Field Address Field IF R FoLD0 FoLD2 TRI- STATE IDo IF IDo IF PD_ POL IF IF R_CNTR[14:0] 0 0

2.4.1 IF R_CNTR[14:0] IF SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) IF R[2:16]

The IF reference divider (IF R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are prohibited. Divide Ratio IF R_CNTR[14:0] 1 4 1 3 1 2 1 1 1 0 9876543210 3 000000000000011 4 000000000000100 32767 111111111111111

2.4.2 PD_POL IF IF SYNTHESIZER PHASE DETECTOR POLARITY IF R[17]

The PD_POL IF bit is used to control the IF synthesizer’s phase detector polarity based on the VCO tuning characteristics. Control Bit Register Location Description Function PD_POL IF IF R[17] IF Phase Detector Polarity IF VCO Negative Tuning Characteristics IF VCO Positive Tuning Characteristics IF VCO Characteristics 10136609

2.4.3 IDo IF IF SYNTHESIZER CHARGE PUMP CURRENT GAIN IF R[18]

The IDo IF bit controls the IF synthesizer’s charge pump gain. Two current levels are available. Control Bit Register Location Description Function IDo IF IF R[18] IF Charge Pump Current Gain LOW 0.95 mA HIGH 3.80 mA LMX2330U/LMX2331U/LMX2332U www.national.com35

2.4.4 TRI-STATE IDo IF IF SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT IF R[19]

The TRI-STATE IDo IF bit allows the charge pump to be switched between a normal operating mode and a high impedance output state. This happens asynchronously with the change in the TRI-STATE ID o IF bit. Furthermore, the TRI-STATE IDo IF bit operates in conjuction with the PWDN IF bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function TRI-STATE IDo IF IF R[19] IF Charge Pump TRI-STATE Current IF Charge Pump Normal Operation IF Charge Pump Output in High Impedance State

2.5 RF R REGISTER

The RF R register contains the RF R_CNTR, PD_POL RF, ID o RF, and TRI-STATE IDo RF control words, in addition to two bits that compose the FoLD control word. The detailed descriptions and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Data Field Address Field RF R FoLD1 FoLD3 TRI- STATE IDo RF IDo RF PD_ POL RF RF R_CNTR[14:0] 0 1

2.5.1 RF R_CNTR[14:0] RF SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) RF R[2:16]

The RF reference divider (RF R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are prohibited. Divide Ratio RF R_CNTR[14:0] 1 4 1 3 1 2 1 1 1 0 9876543210 3 000000000000011 4 000000000000100 32767 111111111111111

2.5.2 PD_POL RF RF SYNTHESIZER PHASE DETECTOR POLARITY RF R[17]

The PD_POL RF bit is used to control the RF synthesizer’s phase detector polarity based on the VCO tuning characteristics. Control Bit Register Location Description Function PD_POL RF RF R[17] RF Phase Detector Polarity RF VCO Negative Tuning Characteristics RF VCO Positive Tuning Characteristics RF VCO Characteristics 10136682 LMX2330U/LMX2331U/LMX2332U www.national.com 36

2.5.3 IDo RF RF SYNTHESIZER CHARGE PUMP CURRENT GAIN RF R[18]

The IDo RF bit controls the RF synthesizer’s charge pump gain. Two current levels are available. Control Bit Register Location Description Function IDo RF RF R[18] RF Charge Pump Current Gain LOW 0.95 mA HIGH 3.80 mA

2.5.4 TRI-STATE IDo RF RF SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT RF R[19]

The TRI-STATE IDo RF bit allows the charge pump to be switched between a normal operating mode and a high impedance output state. This happens asynchronously with the change in the TRI-STATE ID o RF bit. Furthermore, the TRI-STATE IDo RF bit operates in conjuction with the PWDN RF bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function TRI-STATE IDo RF RF R[19] RF Charge Pump TRI-STATE Current RF Charge Pump Normal Operation RF Charge Pump Output in High Impedance State

2.6 IF N REGISTER

The IF N register contains the IF N_CNTRA, IF N_CNTRB, PRE IF, and PWDN IF control words. The IF N_CNTRA and IF N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Data Field Address Field IF N PWDN IF PRE IF IF N_CNTRB[10:0] IF N_CNTRA[6:0] 1 0

2.6.1 IF N_CNTRA[6:0] IF SYNTHESIZER SWALLOW COUNTER (A COUNTER) IF N[2:8]

The IF N_CNTRA control word is used to setup the IF synthesizer’s A counter. The A counter is a 7-bit swallow counter used in the programmable feedback divider. The IF N_CNTRA control word can be programmed to values ranging from 0 to 15. The three most significant bits are ‘don’t care bits’ in this case. Divide Ratio IF N_CNTRA[6:0] 6543210 0XXX0000 1XXX0001 1 5 XXX1111

2.6.2 IF N_CNTRB[10:0] IF SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) IF N[9:19]

The IF N_CNTRB control word is used to setup the IF synthesizer’s B counter. The B counter is an 11-bit programmable binary counter used in the programmable feedback divider. The IF N_CNTRB control word can be programmed to values ranging from 3 to 2047. Divide Ratio IF N_CNTRB[10:0] 1 0 9876543210 300000000011 400000000100 2047 11111111111 LMX2330U/LMX2331U/LMX2332U www.national.com37

2.6.3 PRE IF IF SYNTHESIZER PRESCALER SELECT IF N[20]

The IF synthesizer utilizes a selectable dual modulus prescaler. Control Bit Register Location Description Function PRE IF IF N[20] IF Prescaler Select 8/9 Prescaler Selected 16/17 Prescaler Selected

2.6.4 PWDN IF IF SYNTHESIZER POWERDOWN IF N[21]

The PWDN IF bit is used to switch the IF PLL between a powered up and powered down mode. Furthermore, the PWDN IF bit operates in conjuction with the TRI-STATE ID o IF bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function PWDN IF IF N[21] IF Powerdown IF PLL Active IF PLL Powerdown

2.7 RF N REGISTER

The RF N register contains the RF N_CNTRA, RF N_CNTRB, PRE RF, and PWDN RF control words. The RF N_CNTRA and RF N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Data Field Address Field RF N PWDN RF PRE RF RF N_CNTRB[10:0] RF N_CNTRA[6:0] 1 1

2.7.1 RF N_CNTRA[6:0] RF SYNTHESIZER SWALLOW COUNTER (A COUNTER) RF N[2:8]

The RF N_CNTRA control word is used to setup the RF synthesizer’s A counter. The A counter is a 7-bit swallow counter used in the programmable feedback divider. The RF N_CNTRA control word can be programmed to values ranging from 0 to 127. Divide Ratio RF N_CNTRA[6:0] 6543210 00000000 10000001 1 2 7 1111111

2.7.2 RF N_CNTRB[10:0] RF SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) RF N[9:19]

The RF N_CNTRB control word is used to setup the RF synthesizer’s B counter. The B counter is an 11-bit programmable binary counter used in the programmable feedback divider. The RF N_CNTRB control word can be programmed to values ranging from 3 to 2047. Divide Ratio RF N_CNTRB[10:0] 1 0 9876543210 300000000011 400000000100 2047 11111111111 LMX2330U/LMX2331U/LMX2332U www.national.com 38

2.7.3 PRE RF RF SYNTHESIZER PRESCALER SELECT RF N[20]

The RF synthesizer utilizes a selectable dual modulus prescaler. LMX2330U RF Synthesizer Prescaler Select Control Bit Register Location Description Function PRE RF RF N[20] RF Prescaler Select 32/33 Prescaler Selected 64/65 Prescaler Selected LMX2331U and LMX2332U RF Synthesizer Prescaler Select Control Bit Register Location Description Function PRE RF RF N[20] RF Prescaler Select 64/65 Prescaler Selected 128/129 Prescaler Selected

2.7.4 PWDN RF RF SYNTHESIZER POWERDOWN RF N[21]

The PWDN RF bit is used to switch the RF PLL between a powered up and powered down mode. Furthermore, the PWDN RF bit operates in conjuction with the TRI-STATE ID o RF bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function PWDN RF RF N[21] RF Powerdown RF PLL Active RF PLL Powerdown LMX2330U/LMX2331U/LMX2332U www.national.com39

2.8 FoLD[3:0] MULTI-FUNCTION OUTPUT SELECT [RF R[20], IF R[20], RF R [21], IF R[21]]

The FoLD control word is used to select which signal is routed to the F oLD pin. FoLD3 F oLD2 F oLD1 F oLD0 F oLD Output State 0 0 0 0 LOW Logic State Output 0 0 0 1 IF PLL R Divider Output, Push-Pull Output 0 0 1 0 RF PLL R Divider Output, Push-Pull Output 0 0 1 1 Open Drain Fastlock Output 0 1 0 0 IF PLL Analog Lock Detect, Push-Pull Output 0 1 0 1 IF PLL N Divider Output, Push-Pull Output 0 1 1 0 RF PLL N Divider Output, Push-Pull Output 0 1 1 1 Reset IF Counters, LOW Logic State Output 1 0 0 0 RF Analog Lock Detect, Push-Pull Output 1 0 0 1 IF PLL R Divider Output, Push-Pull Output 1 0 1 0 RF PLL R Divider Output, Push-Pull Output 1 0 1 1 Reset RF Counters, LOW Logic State Output 1 1 0 0 RF and IF Analog Lock Detect, Push-Pull Output 1 1 0 1 IF PLL N Divider Output, Push-Pull Output 1 1 1 0 RF PLL N Divider Output, Push-Pull Output 1 1 1 1 Reset All Counters, LOW Logic State Output LMX2330U/LMX2331U/LMX2332U www.national.com 40

Physical Dimensions inches (millimeters) unless otherwise noted 20-Pin Thin Shrink Small Outline Package (TM) LMX2330U/LMX2331U/LMX2332U www.national.com41

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Pin Chip Scale Package (SLB) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com LMX2330U/LMX2331U/LMX2332U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.

Product Information

LMX2331UTMX specifications and overview.

Summary

PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications

Description

PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications

Source title LMX2331UTMX Datasheet(PDF) - National Semiconductor (TI)

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