LMX2330L NSC | Alldatasheet
Document overview
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Technical content
Features
n Ultra low current consumption n 2.7V to 5.5V operation n Selectable synchronous or asynchronous powerdown mode: ICC = 1 µA typical at 3V n Dual modulus prescaler: LMX2330L (RF) 32/33 or 64/65 LMX2331L/32L (RF) 64/65 or 128/129 LMX2330L/31L/32L (IF) 8/9 or 16/17 n Selectable charge pump TRI-STATE ® mode n Selectable charge pump current levels n Selectable Fastlock™ mode n Upgrade and compatible to LMX233XA family
Applications
n Portable Wireless Communications (PCS/PCN, cordless) n Cordless and cellular telephone systems n Wireless Local Area Networks (WLANs) n Cable TV tuners (CATV) n Other wireless communication systems Functional Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. Fastlock™ , MICROWIRE ™ and PLLatinum™ are trademarks of National Semiconductor Corporation. DS012806-1 June 1999 LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal Communications © 1999 National Semiconductor Corporation DS012806 www.national.com
Pin No. LMX233XLSLB 24-pinCSP Package Pin No. LMX233XLTM 20-pin TSSOP Package Pin Name I/O Description 24 1 V CC 1 — Power supply voltage input for RF analog and RF digital circuits. Input may range from 2.7V to 5.5V. VCC 1 must equal VCC 2. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 22 V P1 — Power Supply for RF charge pump. Must be ≥ VCC . 33 D o RF O Internal charge pump output. For connection to a loop filter for driving the input of an external VCO. 4 4 GND — Ground for RF digital circuitry. 55 f IN RF I RF prescaler input. Small signal input from the VCO. 66 f IN RF I RF prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. 7 7 GND — Ground for RF analog circuitry. 8 8 OSC in I Oscillator input. The input has a VCC /2 input threshold and can be driven from an external CMOS or TTL logic gate. 10 9 GND — Ground for IF digital, MICROWIRE ™ ,FoLD, and oscillator circuits. 11 10 F oLD O Multiplexed output of the RF/IF programmable or reference dividers, RF/IF lock detect signals and Fastlock mode. CMOS output(see Programmable Modes). 12 11 Clock I High impedance CMOS Clock input. Data for the various counters is clocked in on the rising edge, into the 22-bit shift register. 14 12 Data I Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. Chip Scale Package (SLB) (Top View) DS012806-39 Order Number LMX2330LSLB, LMX2331LSLB or LMX2332LSLB Thin Shrink Small Outline Package (TM) (Top View) DS012806-2 Order Number LMX2330LTM, LMX2331LTM or LMX2332LTM www.national.com 2
Pin Descriptions(Continued) Pin No. LMX233XLSLB 24-pinCSP Package Pin No. LMX233XLTM 20-pin TSSOP Package Pin Name I/O Description 15 13 LE I Load enable high impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 appropriate latches (control bit dependent). 16 14 GND — Ground for IF analog circuitry. 17 15 f IN IF I IF prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. 18 16 f IN IF I IF prescaler input. Small signal input from the VCO. 19 17 GND — Ground for IF digital, MICROWIRE, F oLD, and oscillator circuits. 20 18 D o IF O IF charge pump output. For connection to a loop filter for driving the input of an external VCO. 22 19 V P2 — Power Supply for IF charge pump. Must be ≥ VCC . 23 20 V CC 2 — Power supply voltage input for IF analog, IF digital, MICROWIRE, FoLD, and oscillator circuits. Input may range from 2.7V to 5.5V. VCC 2 must equal VCC 1. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 1, 9, 13, 21 X NC — No connect. www.national.com3
Note:The RF prescaler for the LMX2331L/32L is either 64/65 or 128/129, while the prescaler for the LMX2330L is 32/33 or 64/65. Note: VCC 1 supplies power to the RF prescaler, N-counter, R-counter and phase detector. VCC 2 supplies power to the IF prescaler, N-counter, phase detector, R-counter along with the OSCinbuffer, MICROWIRE, and FoLD. VCC 1 and VCC 2 are clamped to each other by diodes and must be run at the same voltage level. Note:VP1 and VP2 can be run separately as long as VP ≥ VCC . www.national.com 4
Absolute Maximum Ratings (Notes 1, If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage V CC −0.3V to +6.5V VP −0.3V to +6.5V Voltage on Any Pin with GND = 0V (VI) −0.3V to V CC +0.3V Storage Temperature Range (TS) −65˚C to +150˚C Lead Temperature (solder 4 sec.) (TL) +260˚C Recommended Operating Conditions Power Supply Voltage VCC 2.7V to 5.5V VP VCC to +5.5V Operating Temperature (TA) −40˚C to +85˚C Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate condi- tions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test condi- tions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2:This device is a high performance RF integrated circuit with an ESD rating <2 keV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected work stations.
Electrical Characteristics
VCC = 3.0V, VP = 3.0V; −40˚C< TA < 85˚C, except as specified Symbol Parameter Conditions Value UnitsMin Typ Max ICC Power LMX2330L RF + IF V CC = 2.7V to 5.5V 5.0 6.6 Supply LMX2330L RF Only 4.0 5.2 Current LMX2331L RF + IF 4.0 5.4 LMX2331L RF Only 3.0 4.0 mA LMX2332L IF + RF 3.0 4.1 LMX2332L RF Only 2.0 2.7 LMX233xL IF Only 1.0 1.4 I CC-PWDN Powerdown Current (Note 3) 1 10 µA fIN RF Operating LMX2330L 0.5 2.5 Frequency LMX2331L 0.2 2.0 GHz LMX2332L 0.1 1.2 fIN IF Operating LMX233xL 45 510 MHz Frequency fOSC Oscillator Frequency 5 40 MHz fφ Maximum Phase Detector 10 MHz Frequency Pf IN RF RF Input Sensitivity V CC = 3.0V −15 0 dBm VCC = 5.0V −10 0 dBm PfIN IF IF Input Sensitivity V CC = 2.7V to 5.5V −10 0 dBm VOSC Oscillator Sensitivity OSC in 0.5 V PP VIH High-Level Input Voltage (Note 4) 0.8 V CC V VIL Low-Level Input Voltage (Note 4) 0.2 V CC V IIH High-Level Input Current V IH = VCC = 5.5V (Note 4) −1.0 1.0 µA IIL Low-Level Input Current V IL = 0V, VCC = 5.5V (Note 4) −1.0 1.0 µA IIH Oscillator Input Current V IH = VCC = 5.5V 100 µA IIL Oscillator Input Current V IL = 0V, VCC = 5.5V −100 µA VOH High-Level Output Voltage (for FoLD, pin number 10) IOH = −500 µA V CC − 0.4 V VOL Low-Level Output Voltage (for FoLD, pin number 10) IOL = 500 µA 0.4 V tCS Data to Clock Set Up Time See Data Input Timing 50 ns tCH Data to Clock Hold Time See Data Input Timing 10 ns tCWH Clock Pulse Width High See Data Input Timing 50 ns tCWL Clock Pulse Width Low See Data Input Timing 50 ns www.national.com5
Electrical Characteristics(Continued) VCC = 3.0V, VP = 3.0V; −40˚C< TA < 85˚C, except as specified Symbol Parameter Conditions Value UnitsMin Typ Max tES Clock to Load Enable Set Up Time See Data Input Timing 50 ns tEW Load Enable Pulse Width See Data Input Timing 50 ns Note 3:Clock, Data and LE= GND or Vcc. Note 4:Clock, Data and LE does not include fIN RF, fIN IF and OSCIN. Charge Pump Characteristics VCC = 3.0V, VP = 3.0V; −40˚C< TA ≤ 85˚C, except as specified Symbol Parameter Conditions Value UnitsMin Typ Max IDo -SOURCE Charge Pump Output V Do = VP/2, ICPo = HIGH (Note 5) −4.0 mA IDo -SINK Current V Do = VP/2, ICPo = HIGH (Note 5) 4.0 mA IDo -SOURCE V Do = VP/2, ICPo = LOW (Note 5) −1 mA IDo -SINK V Do = VP/2, ICPo = LOW (Note 5) 1 mA IDo -TRI Charge Pump 0.5V ≤ VDo ≤ VP − 0.5V −2.5 2.5 nATRI-STATE Current −40˚C < TA < 85˚C IDo -SINK vs CP Sink vs V Do = VP/2 3 10 % IDo-SOURCE Source Mismatch (Note 7) T A = 25˚C IDo vs VDo CP Current vs Voltage 0.5 ≤ VDo ≤ VP − 0.5V 10 15 % (Note 6) T A = 25˚C IDo vs TA CP Current vs V Do = VP/2 10 % Temperature (Note 8) −40˚C ≤ TA ≤ 85˚C Note 5:See PROGRAMMABLE MODES for I CPo description. www.national.com 6
Charge Pump Current Specification Definitions Note 6:IDo vs VDo = Charge Pump Output Current magnitude variation vs Voltage= Note 7:IDo-sinkvs IDo-source= Charge Pump Output Current Sink vs Source Mismatch= Note 8:IDo vs TA = Charge Pump Output Current magnitude variation vs Temperature= DS012806-37 I1= CP sink current at VDo = VP − ΔV I2= CP sink current at VDo = VP/2 I3= CP sink current at VDo = ΔV I4= CP source current at VDo = VP − ΔV I5= CP source current at VDo = VP/2 I6= CP source current at VDo = ΔV www.national.com7
RF Sensitivity Test Block Diagram Typical Performance Characteristics DS012806-38 Note 1:N = 10,000 R = 50 P = 64 Note 2:Sensitivity limit is reached when the error of the divided RF output, FoLD, is≥ 1 Hz. ICC vs VCC LMX2330L DS012806-19 ICC vs VCC LMX2331L DS012806-20 ICC vs VCC LMX2332L DS012806-21 IDo TRI-STATE vs Do Voltage DS012806-22 www.national.com 8
Typical Performance Characteristics(Continued) Charge Pump Current vs Do Voltage ICP = HIGH DS012806-23 Charge Pump Current vs Do Voltage ICP = LOW DS012806-24 Charge Pump Current Variation (See (Note 6)under Charge Pump Current Specification Definitions) DS012806-25 Sink vs Source Mismatch (See (Note 7)under Charge Pump Current Specification Definitions) DS012806-26 www.national.com9
Typical Performance Characteristics(Continued) RF Input Impedance VCC = 2.7V to 5.5V, fIN = 50 MHz to 3 GHz DS012806-27 IF Input Impedance VCC = 2.7V to 5.5V, fIN = 50 MHz to 1000 MHz DS012806-28 LMX2330L RF Sensitivity vs Frequency DS012806-29 LMX2331L RF Sensitivity vs Frequency DS012806-30 www.national.com 10
Typical Performance Characteristics(Continued) LMX2332L RF Sensitivity vs Frequency DS012806-31 IF Input Sensitivity vs Frequency DS012806-32 Oscillator Input Sensitivity vs Frequency DS012806-33 www.national.com11
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters (in- termediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the Con- trol Bits. The DATA is transferred into the counters as follows: Control Bits DATA Location C1 C2 0 0 IF R Counter 0 1 RF R Counter 1 0 IF N Counter 1 1 RF N Counter PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS) If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) Divide RRRRRRRRRRRRRRR Ratio 15 14 13 12 11 10 987654321 3 000000000000011 4 000000000000100 32767 111111111111111 Notes: Divide ratios less than 3 are prohibited. Divide ratio: 3 to 32767 R1 to R15: These bits select the divide ratio of the programmable reference divider. Data is shifted in MSB first. DS012806-6 DS012806-7 www.national.com 12
Functional Description(Continued) PROGRAMMABLE DIVIDER (N COUNTER) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below.For the IF N counter bits 5, 6, and 7 are don’t care bits.The RF N counter does not have don’t care bits. 7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) RF Divide N N N N N N N 1Ratio A 0 0000000 1 0000001 1 2 7 1111111 Notes:Divide ratio: 0 to 127 B ≥ A IF Divide N N N N N N N 1Ratio A
0 XXX0000
1 XXX0001
X = DON’T CARE condition 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER) Divide N N N N N N N N N N N 8Ratio B 3 00000000011 4 00000000100 2047 11111111111 Note:Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited) B ≥ A PULSE SWALLOW FUNCTION fVCO = [ ( PxB )+A ]xfOSC /R fVCO : Output frequency of external voltage controlled oscillator (VCO) B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) A: Preset divide ratio of binary 7-bit swallow counter f OSC : Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) P: Preset modulus of dual moduIus prescaler (forIF;P = 8o r1 6 ; forRF ; LMX2330L: P= 32 or 64 LMX2331L/32L: P = 64 or 128) DS012806-8 www.national.com13
TABLE 1. Programmable Modes TABLE 2. Mode Select Truth Table
0 Negative Normal Operation LOW 8/9 32/33 64/65 Pwrd Up
1 Positive TRI-STATE HIGH 16/17 64/65 128/129 Pwrd Dn
Note 9:Refer to POWERDOWN OPERATION in Functional Description. Note 10:The ICPo LOW current state= 1 / 4xICPo HIGH current. When VCO characteristics are negative like (2), R16 should be set LOW.
TABLE 3. The FoLD (Pin 10) Output Truth Table
0000 Disabled (Note 12)
0100 I F Lock Detect (Note 13)
1000 R F Lock Detect (Note 13)
1100 RF/IF Lock Detect (Note 13)
0011 Fastlock (Note 14)
0111 I F Counter Reset (Note 15)
1011 R F Counter Reset (Note 15)
1111 I F a n d R F Counter Reset (Note 15)
Note 12:When the FoLD output is disabled, it is actively pulled to a low logic state. is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked. occurs whenever the RF loop’s lcpo magnitude bit#17 is selected HIGH (while the#19 and#20 mode bits are set for Fastlock). TRI-STATE) is LOW when its N20 bit (Pwdn) becomes HI. when its N20 bit becomes HI. charge pump reaches a TRI-STATE condition. LE latching LOW data into bit N20.
Functional Description(Continued) SERIAL DATA INPUT TIMING PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS DS012806-10 Note 1:Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Note 2:t cs = Data to Clock Set-Up Time tCH = Data to Clock Hold Time tCWH = Clock Pulse Width High tCWL = Clock Pulse Width Low tES = Clock to Load Enable Set-Up Time tEW = Load Enable Pulse Width Test Conditions:The Serial Data Input Timing is tested using a symmetrical waveform around VCC /2. The test waveform has an edge rate of 0.6 V/ns with DS012806-11 Notes:Phase difference detection range: −2π to +2π The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked. R16 = HIGH www.national.com 16
Typical Application Example DS012806-12 Operational Notes: * VCO is assumed AC coupled. R IN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO power level. fIN RF impedance ranges from 40Ω to 100Ω .fIN IF impedances are higher. * Adding RC filters to the VCC lines is recommended to reduce loop-to-loop noise coupling. DS012806-13 Application Hints: Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board layout. This is an electrostatic sensitive device. It should be handled only at static free work stations. www.national.com17
Physical Dimensionsinches (millimeters) unless otherwise noted 20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2330LTM, LMX2331LTM or LMX2332LTM *For Tape and Reel (2500 units per reel) Order Number LMX2330LTMX, LMX2331LTMX or LMX2332LTMX www.national.com 20
Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com 24-Pin Chip Scale Package Order Number LMX2330LSLB, LMX2331LSLB or LMX2332LSLB *For Tape and Reel (2500 Units per Reel) Order Number LMX2330LSLBX, LMX2331LSLBX or LMX2332LSLBX LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal Communications National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.