LMX2324ATMX

LMX2324A NSC | Alldatasheet

Document overview

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Technical content

Features

■ RF operation up to 2.2 GHz ■ 2.7V to 5.5V operation ■ Low current consumption: ICC = 3.5 mA (typ) at VCC = 3.0V ■ Dual modulus prescaler: 32/33 ■ Internal balanced, low leakage charge pump

Applications

■ Cellular telephone systems (GSM, NADC, CDMA, PDC) ■ Personal wireless communications (DCS-1800, DECT, CT-1+) ■ Wireless local area networks (WLANs) ■ Other wireless communication systems Functional Block Diagram 10124601 PLLatinum™ is a trademark of National Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 101246 www.national.com LMX2324A PLLatinum 2.2 GHz Frequency Synthesizer for RF Personal Communications (SL163188)

See NS Package Number MTC16 Pin Descriptions Pin No. Pin Name I/O DescriptionTSSOP16 CSP16 2 1 VP — Power supply for charge pump. Must be ≥ VCC 3 2 CPo O Internal charge pump output. For connection to a loop filter for driving the voltage control input of an external oscillator. 4 3 GND — Ground. 5 4 fINB I RF prescaler complimentary input. In single-ended mode, a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. The LMX2324 can be driven differentially when the bypass capacitor is omitted. 6 5 fIN I RF prescaler input. Small signal input from the voltage controlled oscillator. 7 6 NC No Connect 8 7 NC No Connect 9 8 OSCin I Oscillator input. A CMOS inverting gate input. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. 10 9 NC No Connect 12 10 Clock I High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various counters and registers. 13 11 Data I Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input. 14 12 LE I Load Enable input. When Load Enable transitions HIGH, data is loaded into either the N or R register (control bit dependent). See timing diagram. 15 13 NC No Connect 11 14 NC No Connect 16 15 CE I CHIP Enable. A LOW on CE powers down the device asynchronously and will TRI- STATE® the charge pump output. 1 16 VCC I Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. www.national.com 2 LMX2324A

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage (VCC) −0.3V to 6.5V Power Supply for Charge Pump (VP) VCC to 6.5V Voltage on Any Pin with GND = 0V (V I) −0.3V to VCC + 0.3V Storage Temperature Range (TS) −65°C to +150°C Lead Temperature (solder, 4 sec.) (TL) +260°C ESD - Whole Body Model (Note 2) 2 kV Recommended Operating Conditions (Note 1) Power Supply Voltage (VCC) 2.7V to 5.5V Power Supply for Charge Pump (VP) VCC to 5.5V Operating Temperature (TA) −40°C to +85°C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should on be done on ESD protected workstations. Electrical Characteristics (VCC = 5V, VP = 3V; 0°C < TA < 70°C except as specified). Symbol Parameter Conditions Min Typ Max Units GENERAL ICC Power Supply Current 3.5 25 mA ICC-PWDN Power Down Current 10 µA fIN fIN Operating Frequency 0.8 2.2 GHz OSCin Oscillator Operating Frequency 5 20 MHz fPD Phase Detector Frequency 10 MHz PfIN Input Sensitivity fINB grounded through a 10 pF capacitor −12 -3 dBm VOSC Oscillator Sensitivity 0.4 1.0 VCC−0.3 VPP CHARGE PUMP ICPo-source Charge Pump Output Current VCPo = VP/2 −4.0 mA ICPo-sink 4.0 mA ICPo-Tri Charge Pump TRI-STATE Current 0.5 ≤ VCPo ≤ VP - 0.5 T = 25°C −5 0.1 5 nA ICPo vs. VCPo Charge Pump Output Current Variation vs. Voltage (Note 4) 0.5 ≤ VCPo ≤ VP - 0.5 T = 25°C 10 % ICPo-sink vs. ICPo-source Charge Pump Output Current Sink vs. Source Mismatch (Note 4) VCPo = VP/2 T = 25°C 5 % ICPo vs. T Charge Pump Output Current Magnitude Variation vs. Temperature (Note 4) VCPo = VP/2 DIGITAL INTERFACE (DATA, CLK, LE, CE) VIH High-Level Input Voltage (Note 3) 0.8 VCC V VIL Low-Level Input Voltage (Note 3) 0.2 VCC V IIH High-Level Input Current VIH = VCC = 5.5V −1.0 1.0 µA IIL Low-Level Input Current VIL = 0, VCC = 5.5V −1.0 1.0 µA IIH Oscillator Input Current VIH = VCC = 5.5V 100 µA IIL VIL = 0, VCC = 5.5V −100 µA MICROWIRE TIMING tCS Data to Clock Set Up Time See Data Input Timing 50 ns tCH Data to Clock Hold Time See Data Input Timing 10 ns tCWH Clock Pulse Width High See Data Input Timing 50 ns tCWL Clock Pulse Width Low See Data Input Timing 50 ns tES Clock to Enable Set Up Time See Data Input Timing 50 ns tEW Enable Pulse Width See Data Input Timing 50 ns 3 www.national.com LMX2324A

Note 3: Except fIN and OSCin Note 4: See related equations in charge pump current specification definitions Charge Pump Current Specification Definitions 10124604 I1 = CP sink current at VCPo = VP − ΔV I2 = CP sink current at VCPo = VP/2 I3 = CP sink current at VCPo = ΔV I4 = CP source current at VCPo = VP − ΔV I5 = CP source current at VCPo = VP/2 I6 = CP source current at VCPo = ΔV 1. ICPo vs. VCPo = Charge Pump Output Current magnitude variation vs. Voltage = 2. ICPo-sink vs. ICPo-source = Charge Pump Output Current Sink vs. Source Mismatch = 3. ICPo vs. T = Charge Pump Output Current magnitude variation vs. Temperature = www.national.com 4 LMX2324A

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthe- sizer such as the National Semiconductor LMX2324A, a volt- age controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, as well as programmable reference [R] and feedback [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R counter to obtain a frequency that sets the comparison frequency. This reference signal, f r, is then presented to the input of a phase/frequency detector and compared with an- other signal, fp, the feedback signal, which was obtained by dividing the VCO frequency down by way of the N counter. The phase/frequency detector's current source outputs pump charge into the loop filter, which then converts the charge into the VCO's control voltage. The phase/frequency comparator's function is to adjust the voltage presented to the VCO until the feedback signal's frequency (and phase) match that of the reference signal. When this “phase-locked” condi- tion exists, the RF VCO's frequency will be N times that of the comparison frequency, where N is the divider ratio.

1.1 OSCILLATOR

The reference oscillator frequency for the PLL is provided by an external reference TCXO through the OSC in pin. OSC in block can operate to 40 MHz with a minimum input sensitivity of 0.4VPP. The inputs have a V CC/2 input threshold and can be driven from an external CMOS or TTL logic gate.

1.2 REFERENCE DIVIDERS (R COUNTER)

The R Counter is clocked through the oscillator block. The maximum frequency is 40 MHz. The R Counter is a 10 bit CMOS binary counters with a divide range from 2 to 1,023. See programming description 2.2.1.

1.3 PROGRAMMABLE DIVIDERS (N COUNTER)

The N counter is clocked by the small signal fIN and fINB input pins. The LMX2324A RF N counter is 15 bit integer divider. The N counter is configured as a 5 bit A Counter and a 10 bit B Counter, offering a continuous integer divide range from 992 to 32,767. The LMX2324A is capable of operating from 100 MHz to 2.0 GHz with a 32/33 prescaler.

1.3.1 Prescaler

The RF inputs to the prescaler consist of the fIN and fINB pins which are the complimentary inputs of a differential pair am- plifier. The differential fIN configuration can operate to 2 GHz with an input sensitivity of −15 dBm. The input buffer drives the N counter's ECL D-type flip flops in a dual modulus con- figuration. A 32/33 prescale ratio is provided for the LMX2324A. The prescaler clocks the subsequent CMOS flip- flop chain comprising the fully programmable A and B coun- ters.

1.4 PHASE/FREQUENCY DETECTOR

The phase(/frequency) detector is driven from the N and R counter outputs. The maximum frequency at the phase de- tector inputs is 10 MHz. The phase detector outputs control the charge pumps. The polarity of the pump-up or pump-down control is programmed using PD_POL, depending on whether RF VCO characteristics are positive or negative (see pro- gramming description 2.2.2). The phase detector also re- ceives a feedback signal from the charge pump, in order to eliminate dead zone.

1.5 CHARGE PUMP

The phase detector's current source output pumps charge in- to an external loop filter, which then converts the charge into the VCO's control voltage. The charge pumps steer the charge pump output, CPo, to VP (pump-up) or Ground (pump- down). When locked, CPo is primarily in a TRI-STATE mode with small corrections. The RF charge pump output current magnitude is set to 4.0 mA. The charge pump output can also be used to output divider signals as detailed in section 2.2.3.

1.6 MICROWIRE SERIAL INTERFACE

The programmable functions are accessed through the MICROWIRE serial interface. The interface is made of three functions: clock, data and latch enable (LE). Serial data for the various counters is clocked in from data on the rising edge of clock, into the 18-bit shift register. Data is entered MSB first. The last bit decodes the internal register address. On the ris- ing edge of LE, data stored in the shift register is loaded into one of the two appropriate latches (selected by address bits). A complete programming description is included in the fol- lowing sections.

1.7 POWER CONTROL

The PLL can be power controlled in two ways. The first method is by setting the CE pin LOW. This asynchronously powers down the PLL and TRI-STATE the charge pump out- put, regardless of the PWDN bit status. The second method is by programming through MICROWIRE, while keeping the CE HIGH. Programming the PWDN bit in the N register HIGH (CE=HIGH) will disable the N counter and de-bias the fIN input (to a high impedance state). The R counter functionality also becomes disabled. The reference oscillator block powers down when the power down bit is asserted. The OSCin pin reverts to a high impedance state when this condition exists. Power down forces the charge pump and phase comparator logic to a TRI-STATE condition. A power down counter reset function resets both N and R counters. Upon powering up the N counter resumes counting in “close” alignment with the R counter (The maximum error is one prescaler cycle). The MI- CROWIRE control register remains active and capable of loading and latching in data during all of the power down modes. 5 www.national.com LMX2324A

2.0 Programming Description

2.1 MICROWIRE INTERFACE

The LMX2324A register set can be accessed through the MICROWIRE interface. A 18-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a 17-bit DATA[16:0] field and a 1-bit address (ADDR) field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data stored in the shift register is loaded into the addressed latch. MSB LSB DATA[16:0] ADDR 17 1 0

2.1.1 Registers' Address Map

When Load Enable (LE) is transitioned high, data is transferred from the 18-bit shift register into the appropriate latch depending on the state of the ADDRESS bit. A multiplexing circuit decodes the address bit and writes the data field to the corresponding internal register. REGISTER ADDRESSED ADDRESS BIT ADDR R Register 1 N Register 0

2.1.2 Register Content Truth Table

MSB SHIFT REGISTER BIT LOCATION LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Data Field ADDR Field N NB_CNTR[9:0] NA_CNTR[4:0] CTL_WORD [1:0] 0 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 R X X X TES T RS PD_ POL CP_ TRI R_CNTR[9:0] R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

2.2 R REGISTER

If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into the 14-bit R register. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide ratio is programmed using the bits R_CNTR as shown in table 2.2.1. The ratio must be ≥ 2. The PD_POL, CP_TRI and TEST bits control the phase detector polarity, charge pump TRI-STATE, and test mode respectively, as shown in 2.2.2. The RS bit is reserved and should always be set to zero. X denotes a don't care condition. Data is clocked into the shift register MSB first. MSB SHIFT REGISTER BIT LOCATION LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Data Field ADDR Field R X X X TEST RS PD_ POL CP_ TRI R_CNTR[9:0] R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 www.national.com 6 LMX2324A

2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter) R_CNTR[9:0] Divide Ratio R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 2 0 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 1 1 1,023 1 1 1 1 1 1 1 1 1 1 Notes: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited) R_CNTR—These bits select the divide ratio of the programmable reference dividers.

2.2.2 R Register Truth Table

CP_TRI R[10] Charge Pump TRI- STATE Normal Operation TRI-STATE PD_POL R[11] Phase Detector Polarity Negative Positive TEST R[13] Test Mode Bit Normal Operation Test Mode If the test mode is NOT activated (R[13]=0), the charge pump is active when CP_TRI is set LOW. When CP_TRI is set HIGH, the charge pump output and phase comparator are forced to a TRI-STATE condition. This bit must be set HIGH if the test mode is ACTIVATED (R[13]=1). If the test mode is NOT activated (R[13]=0), PD_POL sets the VCO characteristics to positive when set HIGH. When PD_POL is set LOW, the VCO exhibits a negative characteristic where the VCO frequency decreases with increasing control voltage. If the test mode is ACTIVATED (R[13]=1), the outputs of the N and R counters are directed to the CPo output to allow for testing. The PD_POL bit selects which counter output according to Table 2.2.3.

2.2.3 Test Mode Truth Table (R[13] = 1)

CPo Output CP_TRI R[10] PD_POL R[11] R Divider Output 1 0 N Divider Output 1 1

2.3 N REGISTER

If the address bit is LOW (ADDR=0) when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit N register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the ratio is described in section 2.3.3. Data is clocked into the shift register MSB first. MSB SHIFT REGISTER BIT LOCATION LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Data Field ADDR Field N NB_CNTR[9:0] NA_CNTR[4:0] CTL_WORD [1:0] 0N1 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 7 www.national.com LMX2324A

2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter) Swallow Count NA_CNTR[4:0] (A) N6 N5 N4 N3 N2 0 0 0 0 0 0 1 0 0 0 0 1 31 1 1 1 1 1 Notes: Swallow Counter Value: 0 to 31 NB_CNTR ≥ NA_CNTR 2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter) NB_CNTR[10:0] Divide Ratio N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 3 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 1 0 0 1023 1 1 1 1 1 1 1 1 1 1 Notes: Divide ratio: 3 to 1,023 (Divide ratios less than 3 are prohibited) NB_CNTR ≥ NA_CNTR

2.3.3 Pulse Swallow Function

The N divider counts such that it divides the VCO RF frequency by (P+1) A times, and then divides by P (B - A) times. The B value (NB_CNTR) must be ≥ 3. The continuous divider ratio is from 992 to 32,767. Divider ratios less than 992 are achievable as long as the binary counter value is greater than the swallow counter value (NB_CNTR ≥ NA_CNTR). fVCO = N x (fOSC/R) N = (P x B) + A fVCO: Output frequency of external voltage controlled oscillator (VCO) fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 10-bit programmable reference counter (2 to 1023) N: Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767) B: Preset divide ratio of binary 10-bit programmable B counter (3 to 1023) A: Preset value of binary 5-bit swallow A counter (0 ≤ A ≤ 31, A ≤ B) P: Preset modulus of dual modulus prescaler (P=32)

2.3.4 CTL_WORD

CNT_RST PWDN

2.3.4.1 Control Word Truth Table

CE CNT_RST PWDN Function 1 0 0 Normal Operation 1 0 1 Synchronous Powerdown 1 1 0 Counter Reset 1 1 1 Asynchronous Powerdown

0 X X Asynchronous Powerdown

Notes: X denotes don't care. The Counter Reset enable bit when activated allows the reset of both N and R counters. Upon powering up the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle). www.national.com 8 LMX2324A

Both synchronous and asynchronous power down modes are available with the LMX2324A to be able to adapt to different types of applications. The MICROWIRE control register remains active and capable of loading and latching in data during all of the powerdown modes. Synchronous Power down Mode The PLL loops can be synchronously powered down by setting the counter reset mode bit to LOW (N[1] = 0) and its power down mode bit to HIGH (N[0] = 1). The power down function is gated by the charge pump. Once the power down mode and counter reset mode bits are loaded, the part will go into power down mode upon the completion of a charge pump pulse event. Asynchronous Power down Mode The PLL loops can be asynchronously powered down by setting the counter reset mode bit to HIGH (N[1] = 1) and its power down mode bit to HIGH (N[0] = 1), or by setting CE pin LOW. The power down function is NOT gated by the charge pump. Once the power down and counter reset mode bits are loaded, the part will go into power down mode immediately. The R and N counters are disabled and held at load point during the synchronous and asynchronous power down modes. This will allow a smooth acquisition of the RF signal when the PLL is programmed to power up. Upon powering up, both R and N counters will start at the ‘zero' state, and the relationship between R and N will not be random. Serial Data Input Timing 10124605 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V CC/2. The test waveform has an edge rate of 0.6 V/ns with Phase Comparator and Internal Charge Pump Characteristics 10124606 Notes: Phase difference detection range: −2π to +2π The minimum width pump up and pump down current pulses occur at the CPo pin when the loop is locked. PD_POL = 1 fR: Phase comparator input from the R Divider fN: Phase comparator input from the N divider CPo: Charge pump output 9 www.national.com LMX2324A

Physical Dimensions inches (millimeters) unless otherwise noted 16-Pin Thin Shrink Small Outline Package Order Number, LMX2324ATMX www.national.com 10 LMX2324A

11 www.national.com LMX2324A

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