LMX2306 NSC | Alldatasheet
Document overview
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Technical content
Features
n 2.3V to 5.5V operation n Ultra low current consumption n 2.5V VCC JEDEC standard compatible n Programmable or logical power down mode: —I CC = 1 µA typical at 3V n Dual modulus prescaler: — LMX2306 8/9 — LMX2316/26 32/33 n Selectable charge pump TRI-STATE ® mode n Selectable FastLock™ mode with timeout counter n MICROWIRE ™ Interface n Digital Lock Detect
Applications
n Portable wireless communications (PCS/PCN, cordless) n Wireless Local Area Networks (WLANs) n Cable TV tuners (CATV) n Pagers n Other wireless communication systems Functional Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. FastLock™ , PLLatinum™ and MICROWIRE ™ are trademarks of National Semiconductor Corporation. DS100127-1 April 2000 LMX2306/LMX2316/LMX2326 PLLatinum Low Power Frequency Synthesizer for RF Personal Communications © 2000 National Semiconductor Corporation DS100127 www.national.com
11 5F L o O FastLock Output. For connection of parallel resistor to the loop filter. (See Section 1.3.4 FASTLOCK MODES description.) 21 6 C P o O Charge Pump Output. For connection to a loop filter for driving the input of an external VCO. 3 1 GND Charge Pump Ground. 4 2 GND Analog Ground. 53 f IN I RF Prescaler Complementary Input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. The complementary input can be left unbypassed, with some degradation in RF sensitivity. 64 f IN I RF Prescaler Input. Small signal input from the VCO. 75 V CC1 Analog Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. VCC1 must equal VCC2 . 8 6 OSC IN I Oscillator Input. This input is a CMOS input with a threshold of approximately VCC /2 and an equivalent 100k input resistance. The oscillator input is driven from a reference oscillator. 9 7 GND Digital Ground. 10 8 CE I Chip Enable. A LOW on CE powers down the device and will TRI-STATE the charge pump output. Taking CE HIGH will power up the device depending on the status of the power down bit F2. (See Section 1.3.1 POWERDOWN OPERATION and Section 1.7.1 DEVICE PROGRAMMING AFTER FIRST APPLYING V CC .) 11 9 Clock I High Impedance CMOS Clock Input. Data for the various counters is clocked in on the rising edge into the 21-bit shift register. 12 10 Data I Binary Serial Data Input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. 13 11 LE I Load Enable CMOS Input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 3 appropriate latches (control bit dependent). 14 12 Fo/LD O Multiplexed Output of the RF Programmable or Reference Dividers and Lock Detect. CMOS output. (See Table 4.) 15 13 V CC2 Digital Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. VCC1 must equal VCC2 . 16 14 V P Power Supply for Charge Pump. Must be≥ VCC . LMX2306/16/26 DS100127-2 16-Lead (0.173” Wide) Thin Shrink Small Outline Package(TM) Order Number LMX2306TM, LMX2306TMX, LMX2316TM, LMX2316TMX, LMX2326TM or LMX2326TMX See NS Package Number MTC16 LMX2306/16/26 DS100127-19 16-pin Chip Scale Package Order Number LMX2306SLBX, LMX2316SLBX or LM2326SLBX See NS Package Number SLB16A LMX2306/LMX2316/LMX2326 www.national.com 2
Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage V CC1 −0.3V to +6.5V VCC2 −0.3V to +6.5V Vp −0.3V to +6.5V Voltage on Any Pin with GND = 0V (VI) −0.3V to V CC + 0.3V Storage Temperature Range (TS) −65˚C to +150˚C Lead Temperature (TL) (solder, 4 sec.) +260˚C Recommended Operating Conditions Min Max Units Power Supply Voltage VCC1 2.3 5.5 V VCC2 VCC1 VCC1 V Vp VCC 5.5 V Operating Temperature (TA) −40 +85 ˚C Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions indicate condi- tions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test condi- tions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2:This device is a high performance RF integrated circuit with an ESD rating < 2 keV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected work stations.
Electrical Characteristics
VCC = 3.0V, Vp = 3.0V; −40˚C< TA < 85˚C except as specified Symbol Parameter Conditions Values Units Min Typ Max ICC Power Supply Current LMX2306 V CC = 2.3V to 5.5 V 1.7 mA LMX2316 V CC = 2.3V to 5.5V 2.5 mA LMX2326 V CC = 2.3V to 5.5V 4.0 mA ICC-PWDN Powerdown Current V CC = 3.0V 1 µA fIN RF Input Operating Frequency LMX2306 V CC = 2.3V to 5.5V 25 550 MHz LMX2316 V CC = 2.3V to 5.5V 0.1 1.2 GHz LMX2326 V CC = 2.3V to 5.5V 0.1 2.1 GHz VCC = 2.6V to 5.5V 0.1 2.8 GHz fosc Maximum Oscillator Frequency 5 40 MHz fφ Maximum Phase Detector Frequency 10 MHz PfIN RF Input Sensitivity V CC = 3.0V −15 +0 dBm VCC = 5.0V −10 +0 dBm VCC =2.3V to 5.5V −10 +0 dBm Posc Oscillator Sensitivity OSC IN −5 dBm VIH High-Level Input Voltage (Note 4) 0.8 x V CC V VIL Low-Level Input Voltage (Note 4) 0.2 x VCC V IIH High-Level Input Current V IH =V CC = 5.5V (Note 4) −1.0 1.0 µA IIL Low-Level Input Current V IL = 0V, VCC = 5.5V (Note 4) −1.0 1.0 µA IIH Oscillator Input Current V IH =V CC = 5.5V 100 µA IIL Oscillator Input Current V IL = 0V, VCC = 5.5V −100 µA ICPo-source Charge Pump Output Current V Do =V p/2, ICPo = LOW (Note 3) −250 µA ICPo-sink VDo =V p/2, ICPo = LOW (Note 3) 250 µA ICPo-source VDo =V p/2, ICPo = HIGH (Note 3) −1.0 mA ICPo-sink VCPo =V p/2, ICPo = HIGH (Note 3) 1.0 mA ICPo-Tri Charge Pump TRI-STATE Current 0.5 ≤ VCPo ≤ Vp − 0.5 −1.0 1.0 nA ICPo-sink vs CP Sink vs Source Mismatch V CPo =V p/2 5 % ICPo-source TA = 25˚C LMX2306/LMX2316/LMX2326 www.national.com3
Electrical Characteristics(Continued) VCC = 3.0V, Vp = 3.0V; −40˚C< TA < 85˚C except as specified Symbol Parameter Conditions Values Units Min Typ Max ICPo vs VDo CP Current vs Voltage 0.5 ≤ VCPo ≤ Vp − 0.5 5 % TA = 25˚C ICPo vs T CP Current vs Temperature V CPo =V p/2 5 % VOH High-Level Output Voltage I OH = −500 µA V CC − 0.4 V VOL Low-Level Output Voltage I OL = 500 µA 0.4 V tCS Data to Clock Set Up Time See Data Input Timing 50 ns tCH Data to Clock Hold Time See Data Input Timing 10 ns tCWH Clock Pulse Width High See Data Input Timing 50 ns tCWL Clock Pulse Width Low See Data Input Timing 50 ns tES Clock to Load Enable Set Up Time See Data Input Timing 50 ns tEW Load Enable Pulse Width See Data Input Timing 50 ns Note 3:See PROGRAMMABLE MODES for ICP o description Note 4:Except fIN and OSC IN. LMX2306/LMX2316/LMX2326 www.national.com 4
Charge Pump Current Specification Definitions I1= CP sink current at VCPo =V p–ΔV I2= CP sink current at VCPo =V p/2 I3= CP sink current at VCPo = ΔV I4= CP source current at VCPo =V p–ΔV I5= CP source current at VCPo =V p/2 I6= CP source current at VCPo = ΔV ΔV = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V 1. ICP o vs VCPo = Charge Pump Output Current magnitude variation vs Voltage = 2. ICP o-sinkvs ICPo–source = Charge Pump Output Current Sink vs Source Mismatch = 3. ICP o vs T = Charge Pump Output Current magnitude variation vs Temperature = DS100127-3 LMX2306/LMX2316/LMX2326 www.national.com5
RF Sensitivity Test Block Diagram DS100127-15 Note 5:N=10,000 R=50 P=32 Note 6:Sensitivity limit is reached when the error of the divided RF output, FoLD, is greater than or equal to 1 Hz. LMX2306/LMX2316/LMX2326 www.national.com 6
1.0 Functional Description
The simplified block diagram below shows the 21-bit data register, a 14-bit R Counter, an 18-bit N Counter, and a 18-bit Function Latch (intermediate latches are not shown). The data stream is shifted (on the rising edge of LE) into the DATA input, MSB first. The last two bits are the Control Bits. The DATA is transferred into the counters as follows: Control DATA Location C1 C2 0 0 R Counter 1 0 N Counter 0 1 Function Latch 1 1 Initialization
1.1 PROGRAMMABLEREFERENCE DIVIDER
If the Control Bits are [C 1,C 2] = [0,0], data is transferred from the 21-bit shift register into a latch that sets the 14-bit R Counter. The 4 bits R15–R18 are for test modes, and should be set to 0 for normal use. The LD precision bit, R19, is described in the LOCK DETECT OUTPUT CHARACTERISTICS section. Serial data format is shown below. 1.1.1 14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) Divide RRRRR RRRRRRRRR Ratio 14 13 12 11 10 987654321 3 00000 000000011 4 00000 000000100 16383 11111 111111111 Notes:Divide ratios less than 3 are prohibited. Divide ratio: 3 to 16383 R1 to R14: These bits select the divide ratio of the programmable reference divider. DS100127-4 DS100127-5 Note:R15 to R18 are test modes and should be zero for normal operation. Data is shifted in MSB first. LMX2306/LMX2316/LMX2326 www.national.com7
1.0 Functional Description(Continued)
1.2 PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 5-bit swallow counter (A counter) and the 13-bit programmable counter (B counter). If the Control Bits are [C1,C 2] = [1,0], data is transferred from the 21-bit shift register into a 5-bit latch (which sets the Swallow (A) Counter), a 13-bit latch (which sets the 13-bit programmable (B) Counter), and the GO bit (See Section 1.3.4 FastLock MODES section) MSB first. For the LMX2306 the maximum N value is 65535 and the minimum N value is 56. For the LMX2316/26, the maximum N value is 262143 and the minimum N value is 992. Serial data format is shown below. 1.2.1 5-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) LMX2316/26 Divide NNNNN Ratio 54321 0 00000 1 00001 3 1 11111 Note:Divide ratio: 0 to 31 B ≥ A LMX2306 Divide NNNNN Ratio 54321
0 XX000
1 XX001
7 XX111
Note:Divide ratio: 0 to 7 B ≥ A X denotes a Don’t Care condition 1.2.2 13-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER) Divide NNNNNNNNN NNNN Ratio 18 17 16 15 14 13 12 11 10 9876 3 000000000 0011 4 000000000 0100 8191 111111111 1111 Divide ratio: 3 to 8191 (Divide ratios less than 3 are prohibited) B≥A
1.2.3 PULSE SWALLOW FUNCTION
fvco = [(P x B) + A] x fosc/R f vco: Output frequency of external voltage controlled oscillator (VCO) B: Preset divide ratio of binary 13-bit programmable counter (3 to 8191) A: Preset divide ratio of binary 5-bit swallow counter (0≤ A ≤ 31; A≤ B for LMX2316/26) or (0≤ A ≤ 7, A≤ B for LMX2306) f osc: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16383) P: Preset modulus of dual modulus prescaler for the LMX2306; P = 8 for the LMX2316/26; P = 32 DS100127-6 Note:Data is shifted in MSB first. LMX2306/LMX2316/LMX2326 www.national.com 8
1.3 FUNCTION AND INITIALIZATION LATCHES
TABLE 1. Programmable Modes TABLE 2. Mode Select Truth Table
0 RESET POWERED NEGATIVE NORMAL
1 RESET POWERED POSITIVE TRI-STATE
F2.Refer to Section 1.3.1 POWERDOWN OPERATION section. F7. Charge Pump TRI-STATE is set using bit F7. For normal operation this bit is set to zero. F10. Timeout Counter Enablebit is set to 1 to enable the timeout counter. SeeTable 5for truth table. F11–14. FastLock Timeout Counteris set using bits F11-14.Table 6for counter values. F15–17. Function bits F15–F17 are forTest Modes, and should be set to 0 for normal use. F18.Refer to Section 1.3.1 POWERDOWN OPERATION section.
1.3.1 POWERDOWN OPERATION
mediately disabled regardless of powerdown bit status. Refer toTable 3. if the F[18] bit is LOW when its F[2] bit becomes HIGH. In the asynchronous powerdown mode (F[18] = LOW), the device powers down immediately after latching LOW data into bit F[2].
- Removes all active DC current paths.
- Forces the R, N, and timeout counters to their load state conditions.
- Will TRI-STATE the charge pump.
- Resets the digital lock detect circuitry.
- Debiases the fIN input to a high impedance state.
- Disables the oscillator input buffer circuitry.
- The MICROWIRE control register remains active and ca- pable of loading the data.
TABLE 3. Power Down Truth Table TABLE 4. The Fo/LD (pin 14) Output Truth Table
1.3.2 LOCK DETECT OUTPUT CHARACTERISTICS
cycle. Setting the charge pump to TRI-STATE or power down (bits F2, F18) will reset the digital lock detect to the unlocked state.
1.3.3 LOCK DETECT FILTER CALCULATION
elapsed where the phase errors are a 1000 times shorter than the reference period (100 ns). Here, N = 5 and F = 1000. node Vc would fall below VCC /2 only after 5 consecutive phase errors whose average pulse width was greater than 100 ns.
1.3.4 FastLock MODES
in National Semiconductor’s LMX 233X series Dual Phase Locked Loops and are selected by F9, F10, and N19 when F8 is HIGH. FIGURE 1. Typical Lock Detect Circuit
TABLE 5. FastLock Decoding *., i.e., ICPo = 1x and FLo returned to TRI-STATE. FastLock Mode 2 Identical to mode 1, except the switching of the device out of FastLock is controlled by the Timeout counter. FastLock Mode 3 This mode is similar to mode 1 in that the output level of the FLo is low and the ICPo is switched to the 4x state. FastLock Mode 4 Identical to mode 3, except the switching of the device out of FastLock is controlled by the Timeout counter. *Normal OperationFastLock Normal Operation is defined as the device being in low current mode and standard divider values.
TABLE 6. FastLock Timeout Counter Value Programming Note 8:The timeout counter decrements after each phase detector comparison cycle.
1.4 SERIAL DATA INPUT TIMING
1.5 PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
Notes:Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. o pin when the loop is locked.
1.6 Typical Application Example
OPERATIONAL NOTES: *VCO is assumed AC coupled. R1 increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO power level. fIN RF impedance ranges from 40Ω to 100Ω . 50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating resistor is required. OSCIN may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (SeeFigurebelow.) DS100127-12 LMX2306/LMX2316/LMX2326 www.national.com 14
1.7 Application Information
1.7.1 DEVICE PROGRAMMING AFTER FIRST
Three MICROWIRE programming methods can be used to change the function latch, R counter latch, and N counter latch contents with close phase alignment of R and N counters to minimize lock up time after the cold power up.
1.7.2 INITIALIZATION SEQUENCE METHOD
Loading the function latch with [C1, C2] = [1, 1] immediately followed by an R counter load, then an N counter load, effi- ciently programs the MICROWIRE. Loading the function latch with [C1, C2] = [1, 1] programs the same function latch as a load with [C1, C2] = [0, 1] and additionally provides an internal reset pulse described below. This program se- quence insures that the counters are at load point when the N counter data is latched in and the part will begin counting in close phase alignment. The following results from latching the MICROWIRE with an F latch word, [C1, C2] = [1, 1]:
- The function latch contents are loaded.
- An internal pulse resets the R, N, and timeout counters to load state conditions and will TRI-STATE the charge pump. If the function latch is programmed for the syn- chronous powerdown case; CE = HIGH, F[2] = HIGH, F[18] = HIGH, this internal pulse triggers powerdown. Refer to Section 1.3.1 POWERDOWN OPERATION sec- tion for a synchronous powerdown description. Note that the prescaler bandgap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
- Latching the first N counter data after the initialization word will activate the same internal reset pulse. Succes- sive N counter data loads without an initialization load will not trigger the internal reset pulse.
1.7.3 CE METHOD
Programming the function latch, R counter latch and N counter latch while the part is being held in a powerdown state by CE allows lowest possible power dissipation. After the MICROWIRE contents have been programmed and the part is enabled, the R and N counter contents will resume counting in close phase alignment. Note that after CE transi- tions from LOW to HIGH, a duration of 1 µs may be required for the prescaler bandgap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the part up and down by pin control in order to check for channel activity. The MICROWIRE does not need to be reprogrammed each time the part is enabled and disabled as long as it has been programmed at least once after V CC was applied.
1.7.4 COUNTER RESET METHOD
This MICROWIRE programming method consists of a func- tion latch load, [C1, C2] = [0, 1], enabling the counter reset bit, F[1]. The R and N counter latches are then loaded fol- lowed by a final function latch load that disables the counter reset. This provides the same close phase alignment as the initialization sequence method with direct control over the in- ternal reset. Note that counter reset holds the counters at load point and will TRI-STATE the charge pump, but does not trigger synchronous powerdown. The counter reset method requires an extra function latch load compared to the initialization sequence method.
1.7.5 DEVICE PROGRAMMING
When programming the LMX2306, LMX2316, and LMX2326, first determine the frequencies and mode of op- eration desired. Data register is programmed with a 21-bit data stream shifted into the R counter, N counter, or the F latch. The Functional Description section shows the bits for the R counter, and the corresponding information for the N counter. The FL o programming information is given in the FUNCTION AND INITIALIZATION LATCHES section. Typi- cal numbers for a GSM application example are given. In the example, the RF output is locking at 950 MHz (f vco) with a 200 kHz channel spacing (fcomparison). The crystal oscillator reference input is 10 MHz (fosc) and the prescaler value (P) is 32. An example of both methods of FastLock will be shown. The last two bits (control bits C1 and C2) of each bit stream identify which counter or FL o mode will be programmed. For example, to program the R counter, C1 and C2 will be 0,0. Immediately proceeding these two bits is the N, R, or F bits providing the divide ratios and FastLock mode information. Control Bits DATA Location C1 C2 0 0 R Counter 1 0 N Counter 0 1 Function Latch 1 1 Initialization For example, to load the N counter, the last two bits C1 and C2 must be 10. Once the control bits have been determined, the frequency information must be determined. To begin, determine the N and R counter values as follows: N=f vco/fcomparison and R=f osc/fcomparison For this example R and N are determined as follows: R = 10 MHz/200 kHz = 50 and N = 950 MHz/200 kHz = 4750 LMX2306/LMX2316/LMX2326 www.national.com15
1.7 Application Information(Continued)
1.7.6 N COUNTER
The calculated value of N, and the value of P are now used to determine the values of A and B where A and B are both integer values: N=P * B+A where B is the divisor and A is the remainder. Therefore: B = div (N/P) and A=N−( B * P) For this example, B and A are calculated as follows: B = div (4750/32) = 148 = 0000010010100 and A = 4750 − (148* 3 2 )=1 4=0 1 1 1 0 To load the N counter with these values, the programming bit stream would be as follows. The first bit, the GO bit, (MSB) N[19] is used for FastLock operation and will be discussed in the F Latch section. The next 13 bits, (N[18]–N[6]) shifted in, are the B counter value, 0000010010100 b *. Bits N[5]–N[1] are the A counter and are 01110b in this example. The final two bits (the control bits) are 1,0 identifying the N counter. In programming the N counter, the value of B must be greater than or equal to A, and the value of B must be greater than or equal to 3. Note:*In programming the counter, data is shifted in MSB first.
1.7.7 R COUNTER
Programming the R counter is done by shifting in the binary value of R calculated previously (50d = 110010b). The first bit shifted in is R[19] the LD precision bit. The next 4 bits (R[18]–R[15]) shifted in, are used for testing and should always be loaded with zeros. The R[14]–R[1] bits are used to program the reference divider ratio and should be 00000000110010 b for this example. The final two bits, C[1] and C[2] denote the R counter and should be 0, 0. The resulting bit stream looks as follows:
1.7.8 F LATCH
To program the device for any of the FastLock modes, C[1] = 0 and C[2] = 1 which direct data to the F latch. The Section 1.3 FUNCTION AND INITIALIZATION LATCH section discusses the 4 modes of FastLock operation. The user must first determine which FastLock mode will be used. When using any of the FastLock modes, the programmer needs to experimentally determine the length of time to stay in high gain mode. This is done by looking at the transient response and determining the time at which the device has settled to within the appropriate frequency tolerance. FastLock mode should be terminated just prior to “lock” to place the switching phase glitch within the transient settling time. The counter reset mode (F[1] bit) holds both the N and R counters at load point when F[1] = HIGH. Upon setting F[1] = LOW, the N and R counters will resume counting in close phase alignment. Other functions of the F latch such as FoLD output control, Phase detector polarity, and charge pump TRI-STATE are defined in the 1.3 FUNCTION AND INITIALIZATION LATCH section also. DS100127-14 DS100127-16 LMX2306/LMX2316/LMX2326 www.national.com 16
1.7.9 FastLock MODE 1 PROGRAMMING
1.7.10 FastLock MODE 2 PROGRAMMING
*) but are dependent on the desired modes of the applicable functions. Table 6. For our example, we will use 27 phase detector cycles, i.e. bits F[11]–F[14] will be 0110b. After
Physical Dimensionsinches (millimeters) unless otherwise noted 16-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2306TM, LMX2316TM or LMX2326TM For Tape and Reel (2500 Units Per Reel) Order Number LMX2306TMX, LMX2316TMXor LMX2326TMX LMX2306/LMX2316/LMX2326 www.national.com 18
Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Order Number LMX2306SLBX, LM2316SLBX or LM2326SLBX LMX2306/LMX2316/LMX2326 PLLatinum Low Power Frequency Synthesizer for RF Personal Communications National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.