LMX2305TMX

LMX2305 NSC | Alldatasheet

Document overview

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Technical content

Features

Y RF operation up to 550 MHz Y 2.65V to 5.5V operation Y Low current consumption: I CC e 4.0 mA (typ) at V CC e 2.75V Y Dual modulus prescaler: 64/65 or 128/129 Y Internal balanced, low leakage charge pump Y Small-outline, plastic, surface mount TSSOP, 0.173 × wide package

Applications

Y Analog Cellular telephone systems (AMPS, ETACS, NMT) Y Portable wireless communications (PCS/PCN, cordless) Y Wireless local area networks (WLANs) Y Other wireless communication systems Y Pagers Block Diagram TL/W/12459–1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM and PLLatinum TM are trademarks of National Semiconductor Corporation.

TL/W/12459–2 20-Lead (0.173 × Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2305TM or LMX2305TMX See NS Package Number MTC20 Pin Descriptions Pin No. Pin Name I/O Description 1 OSC IN I Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for operation as an oscillator. The input has a V CC/2 input threshold and can be driven from an external CMOS or TTL logic gate. May also be from a reference oscillator. 3 OSC OUT O Oscillator output. 4V P Power supply for charge pump. Must be t VCC. 5V CC Power supply voltage input. Input may range from 2.65V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 6D o O Internal charge pump output. For connection to a loop filter for driving the input of an external VCO. 7 GND Ground. 8 LD O Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is locked, the pin’s output is HIGH with narrow low pulses. 10 f IN I Prescaler input. Small signal input from the VCO. 11 CLOCK I High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various counters and registers. 13 DATA I Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input. 14 LE I Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the shift registers is loaded into the appropriate latch (control bit dependent). Clock must be low when LE toggles high or low. See Serial Data Input Timing Diagram. 15 FC I Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase comparator and charge pump combination is reversed. 16 BISW O Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge pump output through BISW (as well as through D o). 17 f OUT O Monitor pin of phase comparator input. CMOS output. 18 wp O Output for external charge pump. wp is an open drain N-channel transistor and requires a pull-up resistor. 19 PWDN I Power Down (with internal pull-up resistor). PWDN e HIGH for normal operation. PWDN e LOW for power saving. Power down function is gated by the return of the charge pump to a TRI-STATE condition. 20 wr O Output for external charge pump. wr is a CMOS logic output. 2,9,12 NC No connect. http:/ /www.national.com 2

TL/W/12459–3 Note 1: The power down function is gated by the charge pump to prevent any unwanted frequency jumps. Once the power down pin is brought low the part will go into power down mode when the charge pump reaches a TRI-STATE condition. http:/ /www.national.com3

Absolute Maximum Ratings (Notes 1 and 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Power Supply Voltage V CC b0.3V to a6.5V VP b0.3V to a6.5V Voltage on Any Pin with GND e 0V (V I) b0.3V to V CC a0.3V Storage Temperature Range (T S) b65§Ct o a150§C Lead Temperature (T L) (solder, 4 sec.) a260§C Recommended Operating Conditions Power Supply Voltage VCC 2.65V to 5.5V VP VCC to a5.5V Operating Temperature (T A) b40§Ct o a85§C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific perform- ance limits. For guaranteed specifications and test conditions, see the Elec- trical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating k 2 keV and is ESD sensitive. Handling and assembly of this device should only be done at ESD workstations. Electrical Characteristics VCC e 2.75V, V P e 2.75V; b40§C k TA k 85§C, except as specified Symbol Parameter Conditions Min Typ Max Units ICC Power Supply Current 4 6 mA ICC-PWDN Power Down Current 30 180 mA fIN RF Input Operating Frequency 45 550 MHz fOSC Oscillator Input Operating Frequency 5 22 MHz fw Phase Detector Frequency 10 MHz PfIN Input Sensitivity V CC e 2.65V to 5.5V b10 a6 dBm VOSC Oscillator Sensitivity OSC IN 0.5 V PP VIH High-Level Input Voltage * 0.7 V CC V VIL Low-Level Input Voltage * 0.3 V CC V IIH High-Level Input Current (Clock, Data) V IH e VCC e 5.5V b1.0 1.0 mA IIL Low-Level Input Current (Clock, Data) V IL e 0V, V CC e 5.5V b1.0 1.0 mA IIH Oscillator Input Current V IH e VCC e 5.5V 100 mA IIL VIL e 0V, V CC e 5.5V b100 mA IIH High-Level Input Current (LE, FC) V IH e VCC e 5.5V b1.0 1.0 mA IIL Low-Level Input Current (LE, FC) V IL e 0V, V CC e 5.5V b100 1.0 mA *Except f IN and OSC IN http:/ /www.national.com 4

Electrical Characteristics VCC e 2.75V, V P e 2.75V; b40§C k TA k 85§C, except as specified (Continued) Symbol Parameter Conditions Min Typ Max Units IDo-source Charge Pump Output Current V Do e VP/2 b2.5 b1.0 mA IDo-sink VDo e VP/2 1.0 2.5 mA IDo-Tri Charge Pump TRI-STATE É Current 0.5V s VDo s VP b 0.5V b5.0 5.0 nATA eb 40§C k TA k 85§C VOH High-Level Output Voltage I OH eb 1.0 mA VCC b 0.8 V VOL Low-Level Output Voltage I OL e 1.0 mA 0.4 V VOH High-Level Output Voltage (OSC OUT)I OH eb 200 mAV CC b 0.8 V VOL Low-Level Output Voltage (OSC OUT)I OL e 200 mA 0.4 V IOL Open Drain Output Current ( wp)V OL e 0.4V 1.0 mA IOH Open Drain Output Current ( wp)V OH e 2.75V 100 mA tCS Data to Clock Set Up Time See Data Input Timing 50 ns tCH Data to Clock Hold Time See Data Input Timing 10 ns tCWH Clock Pulse Width High See Data Input Timing 50 ns tCWL Clock Pulse Width Low See Data Input Timing 50 ns tES Clock to Enable Set Up Time See Data Input Timing 50 ns tEW Enable Pulse Width See Data Input Timing 50 ns **Except OSC OUT http:/ /www.national.com5

The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the R15 Latch, and the 18-bit N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first. If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the S Latch (prescaler select: 64/65 or 128/129). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter (programmable divider). TL/W/12459–1 PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (R15 LATCH) If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit latch (which sets the 14-bit R Counter) and the 1-bit R15 Latch, which sets the prescaler: 64/65 or 128/129. Serial data format is shown below. TL/W/12459–14 14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) Divide R R R R RR R R R R R R R R 1Ratio R 3 0 0 0 0 0 000000011 4 0 0 0 0 0 000000100 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes: Divide ratios less than 3 are prohibited. Divide ratio: 3 to 16383 R1 to R14: These bits select the divide ratio of the programmable reference divider. C: Control bit (set to HIGH level to load R counter and R15 Latch) Data is shifted in MSB first. 1-BIT PRESCALER SELECT (R15 LATCH) Prescaler RSelect P 128/129 0 64/65 1 http:/ /www.national.com 6

Functional Description (Continued) PROGRAMMABLE DIVIDER (N COUNTER) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into a 7-bit latch, which sets the 7-bit Swallow (A) Counter, and an 11-bit latch, which sets the 11-bit programmable (B) Counter. Serial data format is shown below. TL/W/12459–15 Note: S8 to S18: Programmable counter divide ratio control bits (3 to 2047) 7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) Divide N N N N N N N 1Ratio A 0 0000000 1 0000001 1 2 7 1111111 Note: Divide ratio: 0 to 127 B t A 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER) Divide N N N N N N N N NN N 8Ratio B 3 000000000 1 1 4 000000001 0 0 2047 1 1 1 1 1 1 1 1 1 1 1 Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited) B t A PULSE SWALLOW FUNCTION fVCO e [(P c B) a A] c fOSC/R fVCO: Output frequency of external voltage controlled oscil- lator (VCO) B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) A: Preset divide ratio of binary 7-bit swallow counter (0 s A s 127, A s B) fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 14-bit programmable ref- erence counter (3 to 16383) P: Preset modulus of dual modulus prescaler (64 or 128) http:/ /www.national.com7

Functional Description (Continued) SERIAL DATA INPUT TIMING TL/W/12459–16 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V CC/2. The test waveform has an edge rate of 0.6 V/ns with Phase Characteristics In normal operation, the FC pin is used to reverse the polari- ty of the phase detector. Both the internal and any external charge pump are affected. Depending upon VCO characteristics, FC pin should be set accordingly: When VCO characteristics are like (1), FC should be set HIGH or OPEN CIRCUIT; When VCO characteristics are like (2), FC should be set LOW. When FC is set HIGH or OPEN CIRCUIT, the monitor pin of the phase comparator input, f out, is set to the reference divider output, f r. When FC is set LOW, f out is set to the programmable divider output, f p. VCO Characteristics TL/W/12459–17 PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS TL/W/12459–18 Notes: Phase difference detection range: b2q to a2q The minimum width pump up and pump down current pulses occur at the D o pin when the loop is locked. FC e HIGH http:/ /www.national.com 8

The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode. The purpose of the analog switch is to decrease the loop filter time constant, allowing the VCO to adjust to its new frequency in a shorter amount of time. This is achieved by adding another filter stage in parallel. The output of the charge pump is normally through the D o pin, but when LE is set HIGH, the charge pump output also becomes available at BISW. A typical circuit is shown below. The second filter stage (LPF-2) is effective only when the switch is closed (in the scanning mode). TL/W/12459–19 Typical Crystal Oscillator Circuit A typical circuit which can be used to implement a crystal oscillator is shown below. TL/W/12459–20 Typical Lock Detect Circuit A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state. A typical circuit is shown below. TL/W/12459–21 http:/ /www.national.com9

Typical Application Example Operational Notes: TL/W/12459–22 * VCO is assumed AC coupled. RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10 X to 200 X depending on the VCO power level. f IN RF impedance ranges from 40 X to 100 X. * 50X termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating resistor is required. OSC IN may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below) TL/W/12459–23 Application Hints: Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board layout. This is an electrostatic sensitive device. It should be handled only at static free work stations. http:/ /www.national.com 10

Application Information (Continued) Therefore, if we specify the loop bandwidth, 0p, and the phase margin, wp, Equations 1 through 6 allow us to calcu- late the two time constants, T1 and T2, as shown in equa- tions 7 and 8. A common rule of thumb is to begin your design with a 45 § phase margin. T1 e secwp b tanwp 0p (7) T2 e 1 0p2 # T1 (8) From the time constants T1, and T2, and the loop band- width, 0p, the values for C1, R2, and C2 are obtained in equations 9 to 11. C1 e T1 T2 # Kw # KVCO 0p2 # N 0 1 a (0p # T2)2 1 a (0p # T1)2 (9) C2 e C1 # # b 1 J (10) R2 e T2 C2 (11) KVCO (MHz/V) Voltage Controlled Oscillator (VCO) Tuning Voltage constant. The fre- quency vs voltage tuning ratio. Kw (mA) Phase detector/charge pump gain constant. The ratio of the current out- put to the input phase differential. N Main divider ratio. Equal to RF opt/fref RFopt (MHz) Radio Frequency output of the VCO at which the loop filter is optimized. fref (kHz) Frequency of the phase detector in- puts. Usually equivalent to the RF channel spacing. In choosing the loop filter components a trade off must be made between lock time, noise, stability, and reference spurs. The greater the loop bandwidth the faster the lock time will be, but a large loop bandwidth could result in higher reference spurs. Wider loop bandwidths generally improve close in phase noise but may increase integrated phase noise depending on the reference input, VCO and division ratios used. The reference spurs can be reduced by reduc- ing the loop bandwidth or by adding more low pass filter stages but the lock time will increase and stability will de- crease as a result. THIRD ORDER FILTER A low pass filter section may be needed for some applica- tions that require additional rejection of the reference side- bands, or spurs. This configuration is given in Figure 4 .I n order to compensate for the added low pass section, the component values are recalculated using the new open loop unity gain frequency. The degradation of phase margin caused by the added low pass is then mitigated by slightly increasing C1 and C2 while slightly decreasing R2. The added attenuation from the low pass filter is: ATTEN e 20 log [(2qfref # R3 # C3)2 a 1] (12) Defining the additional time constant as T3 e R3 # C3 (13) Then in terms of the attenuation of the reference spurs add- ed by the low pass pole we have T3 e 10ATTEN/20 b 1 (2q # fref)2 (14) We then use the calculated value for loop bandwidth 0c in equation 11, to determine the loop filter component values in equations 15–17. 0c is slightly less than 0p, therefore the frequency jump lock time will increase. T2 e 1 0c2 # (T1 a T3) (15) 0c e tanw # (T1 a T3) [(T1 a T3)2 a T1 # T3] # Ð0 1 a (T1 a T3)2 a T1 # T3 [tanw # (T1 a T3)]2 b 1 ( (16) C1 e T1 T2 # Kw # KVCO 0c2 # N # Ð (1 a 0c2 # T22) (1 a 0c2 # T12)( 1 a 0c2 # T32) ( (/2 (17) http:/ /www.national.com 12

LMX2305 PLLatinum 550 MHz Frequency Synthesizer for RF Personal Communications Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead (0.173 × Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2305TM For Tape and Reel Order Number LMX2305TMX (2500 Units per Reel) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Southeast Asia Japan Ltd. Fax: a49 (0) 180-530 85 86 Fax: (852) 2376 3901 Tel: 81-3-5620-7561Americas Email: europe.support @ nsc.com Email: sea.support @ nsc.com Fax: 81-3-5620-6179Tel: 1(800) 272-9959 Deutsch Tel: a49 (0) 180-530 85 85Fax: 1(800) 737-7018 English Tel: a49 (0) 180-532 78 32Email: support @ nsc.com Fran3ais Tel: a49 (0) 180-532 93 58 Italiano Tel: a49 (0) 180-534 16 80http:/ /www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.