LMV1022

LMV1022 TI1 | Alldatasheet

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LMV1022,LMV1023 LMV1022/LMV1023 PDM Output Pre-Amplifier for Electret Microphones Literature Number: SNAS383A

July 8, 2011 PDM Output Pre-Amplifier for Electret Microphones General Description The LMV1022 and LMV1023 integrate a pre-amplifier and ADC that can be mounted inside an electret condenser mi- crophone (ECM). The digital output signal is a pulse density modulation (PDM) bitstream that alows the microphone to connect directly to the DSP or baseband processor. Part of National Semiconductor’s Powerwise™ family of prod- ucts, the LMV1022/LMV1023 consume 900µW of power dur- ing operation, offering significant power savings over an analog microphone with an external ADC. The LMV1022 out- puts its data on the rising clock edge. The LMV1023 outputs its data on the falling clock edge. Both devices can share the same clock and data lines to create a 4-wire stereo solution. The external clock frequency sets the audio pass band fre- quency. An 800kHz clock sets the pass band to 7kHz. A 2.4MHz clock sets the pass band to 20kHz. The LMV1022 and LMV1023 are available in 6-bump micro SMD packages with 1kg adhesion properties. Key Specifications (Typical V DD = 1.8V, CLOCK = 1.2MHz, f INPUT = 1kHz, VINPUT = 18mVPP, unless otherwise specified) ■ SNR A-weighted 61dB ■ Analog A-weighted noise floor 5 µVRMS ■ Supply current 0.5mA ■ Total harmonic distortion 0.05% ■ Power supply rejection ratio 87dB

Features

■ Integrated 21 dB Pre-Amp and ADC for significant power and space savings ■ Integrated high-pass Filter to reduce 'Plop Noise' ■ Excellent RF immunity (e.g. buzz noise) ■ LMV1022 and LMV1023 combine to create 4-wire Stereo Solution ■ Very thin 0.35mm micro SMD packaging ■ Adhesion technology >1kg

Applications

■ Digital audio subsystems and stereo arrays ■ Electret condenser microphones with all digital output ■ Portable communications and small form factor devices ■ Digital audio computing or voice security ■ Automotive or array systems ■ Headphone and headset accessories Typical Application 20212475 For a stereo application, see STEREO OPERATION in the Application Section. © 2011 National Semiconductor Corporation 202124 www.national.com

202124 Version 2 Revision 1 Print Date/Time: 2011/07/08 14:36:52

LMV1022/LMV1023 PDM Output Preamp for Electret Microphones

6-Bump Ultra Thin micro SMD 20212427 Top View Pin Descriptions Pin Name Description Power Supply A2 VDD Positive supply voltage C1 GND Ground Input C2 Input The microphone is connected to this input pin. Reference B1 VREF A capacitor of 100nF is connected between VREF and ground. This capacitor is used to filter the internal converter reference voltage. Clock Input A1 Clock The user adjustable clock frequency ranges from 800kHz to 2.4MHz. Data Output B2 Data Over sampled bitstream output. Data is valid if clock is LOW (LMV1022). The data of the LMV1023 is valid when clock is HIGH. When the data is not valid the data output is high impedance. For exact specifications see application section.

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing 6-Bump Ultra Thin micro SMD lead free only LMV1022UR Z 250 Units Tape and Reel URA06GGALMV1022URX 3k Units Tape and Reel LMV1023UR 1 250 Units Tape and Reel LMV1023URX 3k Units Tape and Reel www.national.com 2

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 3.8V ESD Rating (Note 4) 2000V ESD Rating (Note 5) 200V Storage Temperature Range −65°C to 150°C Junction Temperature TJMAX(Note 3) 150°C max Mounting Temperature Infrared or Convection (20 sec.) 235°C Operating Ratings (Note 2) Supply Voltage(Note 2) 1.6V to 3.6V Input Clock Frequency 800kHz to 2.4MHz Duty Cycle 40% to 60% Operating Temperature Range −40°C to 85°C 1.8V Electrical Characteristics (Note 2) Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VDD = 1.8V, VIN = 18mVPP, fCLK = 1.2MHz, Duty Cycle = 50% and 100nF capacitor between VREF and GND. Symbol Parameter Conditions LMV1022/ LMV1023 Units (Limits)Typical (Note 6) Limit (Note 7) SNR Signal to Noise Ratio fIN = 1kHz, A-Weighted, output = -23.5dBFS 61 56 dB (min) eND Digital Noise floor of the ADC (Integrated ) Bandwidth = 10 kHz Non Weighted (Note 9) -96 dBFS eNA Noise Floor (Input Referred) Electrical A-Weighted 5 µVRMS Acoustic A-Weigthed (Note 10) -32 dBSPL DR Dynamic range 85 80 dB (min) THD Total Harmonic Distortion fIN = 1kHz, VIN = 18mVPP 0.05 % THD+N Total Harmonic Distortion and Noise fIN = 1kHz, VIN = 18mVPP A-Weighted 0.1 PSRR Power Supply Rejection Ratio VIN = GND, Test Signal on VDD, 217Hz, 400mVPP Input referred. 87 dB VIN Max Input Signal fIN = 1kHz, THD < 1% 150 mVPP Acoustic Overload Point fIN = 1kHz, THD < 10% (Note 10) 115 dBSPL VDOUT Max Digital Output level fIN = 1kHz, THD < 1% -5 dBFSAcoustic Overload Point fIN = 1kHz, THD < 10% (Note 10) -3 fLOW Lower -3dB Corner Frequency FCLK = 1.2MHz 17 Hz FCLK = 2.4MHz 33 Hz CIN Input Capacitance 2 pF RIN Input Impedance VIN = 0VDC >1000 MΩ IDD Supply Current VIN = GND, CLK = ON, High Impedance Load 0.5 0.75 mA (max) VIN = GND, CLK = OFF, High Impedance Load 0.45 0.6 mA (max) 3 www.national.com

3.3V Electrical Characteristics (Note 2) Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VDD = 3.3V, VIN = 18mVPP, fCLK = 2.4MHz, Duty Cycle = 50% and 100nF capacitor between VREF and GND. Symbol Parameter Conditions LMV1022/ LMV1023 Units (Limits)Typical (Note 6) Limit (Note 7) SNR Signal to Noise Ratio fIN = 1kHz, A-Weighted, output = -23.5dBFS 61 56 dB (min) eND Digital Noise floor of the ADC (Integrated ) Bandwidth = 20 kHz Non Weighted (Note 9) -96 dBFS eNA Noise Floor (Input Referred) Electrical A-Weighted 5 µVRMS Acoustic A-Weigthed (Note 10) -32 dBSPL DR Dynamic range 85 80 dB (max) THD Total Harmonic Distortion fIN = 1kHz, VIN = 18mVPP 0.05 % THD+N Total Harmonic Distortion and Noise fIN = 1kHz, VIN = 18mVPP A-Weighted 0.1 PSRR Power Supply Rejection Ratio VIN = GND, Test Signal on VDD, 217Hz, 400mVPP Input referred. 87 dB VIN Max Input Signal fIN = 1kHz, THD < 1% 150 mVPP Acoustic Overload Point fIN = 1kHz, THD < 10% (Note 10) 115 dBSPL VDOUT Max Digital Output level fIN = 1kHz, THD < 1% -5 dBFSAcoustic Overload Point fIN = 1kHz, THD < 10% (Note 10) -3 fLOW Lower -3dB Corner Frequency FCLK = 1.2MHz 17 Hz FCLK = 2.4MHz 33 Hz CIN Input Capacitance 2 pF RIN Input Impedance VIN = 0VDC >1000 MΩ IDD Supply Current VIN = GND, CLK = ON, High Impedance Load 0.6 0.9 mA (max) VIN = GND, CLK = OFF, High Impedance Load 0.5 0.65 mA (max) www.national.com 4

Digital Interface Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C, 1.6V < VDD < 3.6V, VIN = 18 mVPP, 800kHz < fCLK < 2.4 MHz, Duty Cycle = 50% and 100nF capacitor between VREF and GND. Symbol Parameter Conditions Typical (Note 6) Limits (Note 7) Units (min/ max) VLOW CLOCK Logic Low Level 0.1*VDD V (max) VHIGH CLOCK Logic High Level 0.9*VDD V (min VOL DATA Output Logic Low Level ISINK = 0.5mA 0.1 V (min) VOH DATA Output Logic High Level ISOURCE = 0.5mA VDD-0.1V V (max tHZ Time from CLOCK Transition to DATA Becoming High Impedance (See also Figure 10, Application Section) LMV1022: On Rising Edge of the CLOCK 65 nsLMV1023: On Falling Edge of the CLOCK tDV Time from CLOCK Transition to DATA Becoming Valid (See also Figure 10, Application Section) LMV1022: On Falling Edge of the CLOCK 90 nsLMV1023: On Rising Edge of the CLOCK Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LMV1022, LM1023 see power derating curves for additional information. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis. Note 8: The Supply Current depends on the applied Clock Frequency and the load on the DATA output. Note 9: Quantization Noise level of the modulator (verified by simulation) Note 10: Calculated for Typical microphone as described in the Application section Digital Microphone 5 www.national.com

Typical Performance Characteristics Unless otherwise specified, measurements are performed on an LMV1022/ LMV1023 with VDD = 1.8V, Clock Duty Cycle = 50% and a 100nF capacitor is placed between VREF and GND, TJ = 25° C, Vin =18 mVpp Output Spectrum at 16kBit/s, CLOCK Frequency = 0.8MHz 20212446 Output Spectrum at 48kbit/s, CLOCK Frequency = 2.4MHz 20212430 Output Spectrum, Stereo Operation at 48kbit/s, CLOCK Frequency = 2.4MHz 20212431 Output Noise Spectrum at16kbit/s and 48kbit/s 20212448 THD and Output Level vs. Frequency at 16bBit/s, CLOCK Frequency = 0.8MHz Vin = 50mVpp 20212449 THD and Output Level vs. Frequency at 24kbit/s, CLOCK Frequency = 1.2MHz Vin = 50mVpp 20212450 www.national.com 6

THD and Output Level vs. Frequency at 32kbit/s, CLOCK Frequency = 1.6MHz Vin = 50mVpp 20212432 THD and Output Level vs. Frequency at 48kbit/s, CLOCK Frequency = 2.4MHz , Vin = 50mVpp 20212452 THD vs. Input Level at 16kbit/s, CLOCK Frequency = 0.8MHz 20212453 THD vs. Input Level at 24kbit/s, CLOCK Frequency = 1.6MHz 20212454 THD vs. Input Level at 32kbit/s, CLOCK Frequency = 1.6MHz 20212433 THD vs. Input Level at 48kbit/s, CLOCK Frequency = 2.4MHz 20212456 7 www.national.com

PSRR vs. Frequency for VDD = 1.8V and 3.3V at 16kbit/s, CLOCK Frequency = 0.8MHz 20212457 PSRR vs. Frequency for VDD = 1.8V and 3.3V at 48kbit/s, CLOCK Frequency = 2.4MHz 20212458 IDD vs. VDD CLOCK Frequency = 0.8MHz and 2.4MHz 20212434 www.national.com 8

the DSP or Baseband decimates the audio signal. FIGURE 1. Typical Application portional to the input clock frequency of the part. FIGURE 2. Built-in Pre-Amplifier / ADC pads that connects VDD, Ground, DATA and the CLOCK.

FIGURE 3. Cross section of a Microphone

FIGURE 4. A-weighted Filter put for a given sound pressure. pressure in decibels referred to 1Pa instead of 20µPa. diagram of a microphone with a JFET is given in Figure 5. Example: Busy traffic has a sound pressure of 70dB SPL. This is equivalent to 1.13mVPP.

FIGURE 5. Microphone Sensitivity sensitivity of the electret plus the gain of the pre-amplifier. be used to replace the JFET inside the microphone canister. Microphone output = 70 - 94 - 29 = −53dBV. This is equivalent to 6.33mVPP. the microphone and the baseband.

microphone is therefore: −44 + 20.5 = −23.5dB(FS/Pa). ing DATA output as function of the input. FIGURE 6. DATA Output versus Input Amplitude and a couple of common Audio Bandwidths. TABLE 1. Audio Bandwidth vs. Clock Frequency where a 1 kHz signal is applied.

FIGURE 7. Frequency Spectrum chip or DSP eliminates the noise above the band of interest. the frequency spectrum after filtering. FIGURE 8. Frequency Spectrum after Filtering interface lines to minimize wiring (Figure 9). FIGURE 9. Stereo Application see the Electrical Characteristics table. FIGURE 10. Timing stereo application

any switching noise coupling directly into the input of the IC. connected to the reference pin of the LMV1022/ LMV1023. load the output driver and would degrade the performance. phones, where capacitors are needed to improve RFI. FIGURE 11. Application schematic for PCB Layout FIGURE 12. PCB Layout

Revision History

1.0 04/04/08 Initial release. www.national.com 16

Physical Dimensions inches (millimeters) unless otherwise noted NOTE: UNLESS OTHERWISE SPECIFIED. 1. FOR SOLDER BUMP COMPOSITION, SEE “SOLDER INFORMATION” IN THE PACKAGING SECTION OF THE NATIONAL SEMICONDUCTOR WEB PAGE (www.national.com). 2. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD. 3. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. 4. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS PACK- AGE HEIGHT. 5. NO JEDEC REGISTRATION AS OF MARCH 2003 6-Bump Ultra Thin micro SMD X1 = 1.128mm, X2 = 1.628mm, X3 = 0.35mm 17 www.national.com

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