LMR604404SBRAKRQ1

LMR60440-Q1_V01 TI2 | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 48

Technical content

LMR60440-Q1 3V to 36V, 4A, MINT 1 Automotive, Synchronous Buck Converter Optimized for Low EMI, High Power Density, and Low Output Capacitance

1 Features

• Mitigated interference and noise technology – architecture 1 (MINT 1): – Facilitates CISPR 25 class 5 compliance – Low inductance HotRod™ QFN package – Advanced spread spectrum options available
• AEC-Q100 qualified for automotive applications – Device temperature grade 1: –40°C to 125°C ambient operating temperature range
• Functional Safety-Capable – Documentation available to aid functional safety system design
• Wide operating input voltage: 3V to 36V (42V absolute maximum)
• Programmable output voltage options available in fixed 3.3V/ADJ, 3.8V/ADJ, and 5V/ADJ – Adjustable output voltage range from 1V to 20V
• Ultra-low quiescent current – Shutdown current: 0.7μA – No load standby current: 5μA
• Optimized control loop for low output capacitance
• Switching frequency from 200kHz – 2.2MHz
• Low minimum on time tON (30ns typical)
• FPWM, PFM, or external frequency synchronization available
• Designed for scalable power supplies – Pin compatible with LMR60406-Q1, LMR60410-Q1, LMR60420-Q1, LMR60430-Q1, LMR61430-Q1, LMR61440-Q1, LMR60441-Q1, LMR60450-Q1, and LMR60460-Q1
• Power-Good output for power sequencing

2 Applications

• Automotive camera applications
• Automotive driver assistance systems
• Automotive body applications LMR60440-Q1 PGND VIN EN MODE/ SYNC RT BOOT SW FB PG CIN PGND VIN PGND PGND PGND CBOOT COUT PGND VOUT RT Simplified Schematic – Fixed Output

3 Description

The LMR60440-Q1 is a 3V to 36V (42V transient), 4A, automotive-grade synchronous buck converter in an ultra compact 2.5mm × 2mm QFN-9 package or 3.5mm × 2.5mm QFN-11 package with wettable flanks. The HotRod™ QFN package with mitigated interference and noise technology using architecture 1 features (MINT 1) achieves low EMI performance to facilitate qualification of automotive and other noise- sensitive designs. All device variants are capable of output voltages ranging from 1V to 20V in adjustable output configuration. Each variant is also capable of delivering a fixed output voltage by connecting the output voltage node directly to the feedback pin. The Device Comparison Table provides details on the fixed output voltage options. The current-mode control architecture with 30ns minimum on-time allows high conversion ratios at high frequencies, fast transient response, and excellent load and line regulation. Open drain power-good output facilitates power sequencing requirements. The MODE/SYNC pin of the LMR60440-Q1 allows the user to select between forced pulse width modulation (FPWM), auto mode, or external synchronization mode of operation. The LMR60440-Q1 is designed to offer reduced output capacitance leading to compact PCB layout and system cost savings. The LMR60440-Q1 is a part of a family of pin-compatible devices ranging in current levels from 0.6A to 6A.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LMR60440-Q1 RAK (WQFN-HR, 9) 2.5mm × 2mm RBM (WQFN-HR, 11) 3.5mm × 2.5mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. EVM Layout - 2.2MHz 3.3V Fixed Output LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

2 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

4 Device Comparison Table

ORDERABLE PART NUMBER(1) OUTPUT VOLTAGE SPREAD SPECTRUM WETTABLE FLANKS PACKAGE SIZE LMR604403SBRAKRQ1 3.3V fixed / adjustable Yes Yes 2.5mm × 2mm LMR604404SBRAKRQ1 3.8V fixed / adjustable Yes Yes 2.5mm × 2mm LMR604405SBRAKRQ1 5V fixed / adjustable Yes Yes 2.5mm × 2mm LMR604403SRBMRQ1 3.3V fixed / adjustable Yes Yes 3.5mm × 2.5mm PLMR604405SRBMRQ1(2) 5V fixed / adjustable Yes Yes 3.5mm × 2.5mm (1) For other variant options, contact TI. (2) Advance information (not Production Data). www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMR60440-Q1

5 Pin Configuration and Functions

Figure 5-1. RAK Package 9-Pin WQFN-HR (Top View) PGND 11 3 MODE/ SYNC 69 5 FB PGRT NC BOOT SW EN NC VIN Figure 5-2. RBM Package 11-Pin WQFN-HR (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION RAK RBM NAME 1 1 VIN P Regulator input power pin to the high-side power MOSFET and internal VCC regulator. Connect to the input supply and the positive terminal of the input filter capacitor. The path from the VIN pin to the input capacitor must be as short as possible. 2 7 PGND G Power ground. This pin connects to the source of the low-side MOSFET internally. Connect to system ground, and the ground terminal of the CIN and COUT capacitors. The path to CIN must be as short as possible. 3 2 SW P Regulator switch node. Connect to the power inductor and bootstrap capacitor. 4 3 BOOT P High-side MOSFET driver supply for bootstrap gate drive. Connect a high quality 100nF capacitor between this pin and SW as close to the device as possible. 5 5 PG O Open drain power-good output. Connect to a suitable voltage supply through a current limiting pull up resistor. High = regulator 6 6 FB I Feedback pin. Connect this pin directly to the output voltage node for fixed VOUT operation. See Section 4 for the voltage level for each device variant. Connect to the center point of a feedback voltage divider placed between VOUT node and PGND to program an adjustable output voltage. 7 8 MODE/ SYNC I Operational mode input pin. Connect this pin to the RT pin to select FPWM switching or connect this pin to GND to select PFM switching in light loads. To synchronize to an external clock, connect a 100kΩ resistor to ground and drive directly from the clock. See the Electrical Characteristics table for acceptable voltage levels and timing requirements. 8 9 RT I Frequency programming pin. A resistor from RT to PGND sets the oscillator frequency between 200kHz and 2.2MHz. 9 10 EN I Enable pin for the regulator. Drive this pin high to enable the device and low to disable the device. If the enable function is not needed, connect this pin to the VIN pin. See the Electrical Characteristics table for more information on acceptable voltage levels. ‒ 4, 11 NC ‒ No internal connection to the device (1) G = Ground, I = Input, O = Output, P = Power LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

4 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

6 Specifications

6.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage VIN to PGND –0.3 42 V Input voltage EN/UVLO TO PGND –0.3 42 V Input voltage RT, MODE/SYNC to PGND –0.3 42 V Input voltage FB to PGND –0.3 20 V Output voltage PG to PGND –0.3 20 V Output voltage SW to PGND(2) –0.3 VIN + 0.3 V Output voltage BOOT to SW –0.3 5.5 V Temperature Operating junction temperature, TJ –40 150 °C Temperature Storage temperature, Tstg –55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Do not externally drive the SW pin. A voltage of 5V below PGND and peak voltage not exceeding 42V for less than 20ns is allowed during switching transitions

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 (1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted) MIN MAX UNIT Input voltage VIN 3 36 V Input voltage EN 0 36 V Input voltage PG 0 18 V Input voltage MODE/SYNC, RT 0 5.5 V Output voltage VOUT 1.0 20(1) V Output current IOUT (LMR60440-Q1) 0 4.0 A Temperature Operating junction temperature, TJ –40 150 °C (1) Contact TI for information regarding output voltages outside of this range. Under no conditions must the output voltage be allowed to fall below zero volts.

6.4 Thermal Information

THERMAL METRIC(1) DEVICE UNITRAK (WQFN-HR) RBM (WQFN-HR)

9 PINs 11 PINs

RθJA Junction-to-ambient thermal resistance (JESD 51-7)(2) 84.5 75.1 °C/W RθJA Junction-to-ambient thermal resistance 32.5 36.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.3 37.3 °C/W RθJB Junction-to-board thermal resistance 23.9 21.1 °C/W ΨJT Junction-to-top characterization parameter 2.9 0.5 °C/W www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMR60440-Q1

THERMAL METRIC(1) DEVICE UNITRAK (WQFN-HR) RBM (WQFN-HR) ΨJB Junction-to-board characterization parameter 23.2 21 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. (2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. This value does not represent the performance obtained in an actual application. For example, the EVM RθJA (for RAK package) = 32.5°C/W.

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, VEN = VIN, VOUT = 3.3V, FSW = 2MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY (VIN PIN) VINUVLO(R) VIN UVLO rising threshold VIN rising (needed to start up) 3.3 3.5 3.7 V VINUVLO(F) VIN UVLO falling threshold VIN falling (once operating) 2.65 V VINUVLO(H) VIN UVLO hysteresis 1 V VINOVP(R) VIN OVP rising threshold VIN rising needed to switch device into PFM operation 35 37 39 V VINOVP(F) VIN OVP falling threshold VIN falling needed to switch device from PFM to FPWM operation 34 36 38 V VINOVP(H) VIN OVP hysteresis 0.6 0.95 1.2 V IQ(FIX-3.3V) Total VIN quiescent current, fixed 3.3V output, no switching VIN = 13.5V, IOUT = 0A, VFB = 3.3V + 4%, TJ = 25°C, Auto mode enabled 3.8 5 µA IQ(ADJ-3.3V) Total VIN quiescent current, adjustable 3.3V output, no switching VIN = 13.5V, IOUT = 0A, VFB = 1V + 4%, TJ = 25°C, Auto mode enabled 3.8 5 µA IQ-SD VIN shutdown supply current VEN = 0V, TJ = 25°C 0.7 1 µA ENABLE (EN PIN) VEN-TH(R) Enable voltage rising threshold VEN rising 1.15 1.25 1.35 V VEN-TH(F) Enable input low threshold VEN falling 0.9 1 1.1 V VEN-HYS Enable voltage hysteresis 275 mV IEN-LKG Enable input leakage current VEN = VIN 1 665 nA VOLTAGE REFERENCE (FB PIN) VFB Internal feedback reference voltage FPWM mode 0.99 1.0 1.01 V IFB-LKG Feedback pin input leakage current VFB = 1V, adjustable output voltage 0.09 50 nA STARTUP tSS Internal fixed soft-start time Time from first SW pulse to VREF at 90% of set point 6 ms CURRENT LIMITS AND HICCUP IHS-LIM High side peak current limit Duty-cycle approaches 0% 5.1 6.9 8.2 A ILS-LIM Low side valley current limit Valley current limit on LS FET 3.4 4.4 5.5 A ILS-NEG-LIM Low side negative current limit Sinking current limit on LS FET, FPWM IL-ZC-LIM Zero-cross current limit Auto mode 80 mA VHIC Overcurrent hiccup threshold on FB pin LS FET On-time > 165ns, not during soft- start 0.14 0.2 0.25 V POWER GOOD (PG PIN) VPG-OVP(R) PG overvoltage rising threshold % of FB voltage (adj) 105 107 109.7 % VPG-OVP(F) PG overvoltage falling threshold % of FB voltage (adj) 104 106 108 % VPG-UVP(R) PG undervoltage rising threshold % of FB voltage (adj) 92 94 96.5 % LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

6 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, VEN = VIN, VOUT = 3.3V, FSW = 2MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VPG-UVP(F) PG undervoltage falling threshold % of FB voltage (adj) 91 93 95 % tPG-DEGLITCH Deglitch filter delay on PG falling edge 42 52 81 µs tPG-DEASSERT PG deassertion time 1.0 2.0 3.0 ms VIN(PG-VALID) Minimum VIN for valid PG output VOL(PG) < 0.4V, RPU = 10kΩ, VPU = 5V 1.25 V RON(PG) PG ON resistance IPG = 1mA 165 420 Ω SWITCHING FREQUENCY (RT PIN) fSW1(FPWM) Switching frequency, FPWM operation RRT = 15.2kΩ, 1% 1800 2000 2200 kHz fSW2(FPWM) Switching frequency, FPWM operation RRT = 32.8kΩ, 1% 900 1000 1100 kHz SYNCHRONIZATION (MODE/SYNC PIN) VIH_FPWM MODE/SYNC pin voltage to enter FPWM 0.5 0.85 V VIL_FPWM MODE/SYNC pin voltage to exit FPWM 0.35 0.7 V VIH_CLK External clock input high level threshold 1.3 V VIL_CLK External clock input low level threshold 0.35 V tCLKIN(TON) Minimum positive pulse width of external sync signal 150 ns tCLKIN(TOFF) Minimum negative pulse width of external sync signal 150 ns POWER STAGE RDS-ON-HS High-side FET ON resistance ISW = 500mA, VBOOT-SW = 3.8V 60 130 mΩ RDS-ON-LS Low-side FET ON resistance 40 85 mΩ tON-MIN (1) Minimum on-time 30 ns tOFF-MIN (1) Minimum off-time 100 ns THERMAL SHUTDOWN TSD Thermal shutdown(1) Shutdown threshold 155 165 176 ºC Recovery threshold 156 ºC (1) Not tested in production. www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMR60440-Q1

6.6 Typical Characteristics

VIN = 13.5V, TA = 25°C (unless otherwise noted). Specified temperatures are ambient. Temperature (°C) High Side Current Limit (A) -40 -20 0 20 40 60 80 100 120 140 6.9 6.91 6.92 6.93 6.94 6.95 6.96 6.97 6.98 6.99 Figure 6-1. High Side MOSFET Current Limit Temperature (°C) Low Side Current Limit (A) -40 -20 0 20 40 60 80 100 120 140 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 Figure 6-2. Low Side MOSFET Current Limit Temperature (°C) High Side RDSON (mOhm) -40 -20 0 20 40 60 80 100 120 140 100 Figure 6-3. High Side MOSFET RDS-ON Temperature (°C) Low Side RDSON (mOhm) -40 -20 0 20 40 60 80 100 120 140 70 Figure 6-4. Low Side MOSFET RDS-ON Temperature (°C) Output Voltage (V) -40 -20 0 20 40 60 80 100 120 140 3.2 3.22 3.24 3.26 3.28 3.3 3.32 3.34 3.36 3.38 3.4 3.3V Fixed Figure 6-5. Output Voltage Accuracy Temperature (°C) Soft Start Time (ms) -40 -20 0 20 40 60 80 100 120 140 5.5 5.6 5.7 5.8 5.9 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Figure 6-6. Soft-Start Time LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

8 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

6.6 Typical Characteristics (continued)

VIN = 13.5V, TA = 25°C (unless otherwise noted). Specified temperatures are ambient. T e m p e r a t u r e ( ° C ) Enable voltage threshold (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 9 0 . 9 5 1 . 0 5 1 . 1 1 . 1 5 1 . 2 1 . 2 5 1 . 3 1 . 3 5 1 . 4 R i s i n g F a l l i n g Figure 6-7. Enable Threshold Voltage T e m p e r a t u r e ( ° C ) FB voltage (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 9 3 0 . 9 4 0 . 9 5 0 . 9 6 0 . 9 7 0 . 9 8 0 . 9 9 1 . 0 1 1 . 0 2 1 . 0 3 1 . 0 4 1 . 0 5 Figure 6-8. Feedback Voltage Accuracy T e m p e r a t u r e ( ° C ) VIN UVLO (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 2 . 2 5 2 . 5 2 . 7 5 3 . 2 5 3 . 5 3 . 7 5 R i s i n g F a l l i n g Figure 6-9. Input Voltage UVLO T e m p e r a t u r e ( ° C ) PGOOD threshold (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 9 0 9 2 . 5 9 5 9 7 . 5 1 0 0 1 0 2 . 5 1 0 5 1 0 7 . 5 1 1 0 1 1 2 . 5 1 1 5 O V r i s i n g O V f a l l i n g U V r i s i n g U V f a l l i n g Figure 6-10. PGOOD Thresholds www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMR60440-Q1

7 Detailed Description

7.1 Overview

The LMR60440-Q1 is a highly-efficient, 3V to 36V, ultra-low IQ, synchronous buck converter that enables high power density and low EMI. The LMR60440-Q1 is designed to minimize the product cost and size by reducing the number of external passive components required to generate a stable design. Intended for demanding automotive applications, LMR60440-Q1 devices are AEC-Q100 qualified and have electrical characteristics specified up to a maximum junction temperature of 150ºC. The LMR60440-Q1 offers key features that allow for design flexibility depending on the desired operating conditions:

• Precision enable through the EN pin allows for accurate power on and power off of the device
• Switching frequency selection with the RT pin allows designers to select the switching frequency between 200kHz and 2.2MHz
• The MODE/SYNC pin allows for designers to select the mode of operation, or to synchronize to an external clock frequency
• The PG pin enables power supply sequencing and notification of the status of the output voltage without the need for external voltage supervisors Each converter features a pair of integrated power MOSFETs designed for delivering up to 4A of output current. All variants of the LMR60440-Q1 allow for every device to be configured to either a fixed output voltage or an adjustable output voltage depending on the presence of feedback resistors. The fixed output voltage setting is determined by the specific orderable part number, which can be found in the Device Comparison Table. The LMR60440-Q1 offers several protection features that make the device an excellent choice for demanding applications. The feedback pin has a voltage rating which makes sure the pin is able to withstand an output voltage short circuit to battery even when in fixed output voltage configuration. The device disables FPWM switching when the input voltage exceeds VIN OVP(R) which prevents negative currents from overcharging the input voltage in the event that the output voltage is shorted to the input supply. Thermal shutdown disables switching and allows the LMR60440-Q1 to cool before attempting to restart. The current-mode control architecture with 30ns minimum on-time allows high conversion ratios at high frequencies, easy loop compensation, fast transient response, and excellent load and line regulation. The converters also feature a HotRod™ package with enhanced spread spectrum that enables low-EMI performance and eases qualification of automotive and noise-sensitive designs. LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

10 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

7.2 Functional Block Diagram

+1V Soft-Start Logic COMP SW

7.3 Feature Description

7.3.1 Enable and Undervoltage Lockout (UVLO)

LMR60440-Q1 features a precision enable and undervoltage lockout (UVLO) feature which enables the user to select the voltage level at which the device powers on and off based on the voltage present at the EN pin. To power on the device the voltage between EN pin and PGND pin must exceed the enable voltage rising threshold VEN-TH(R) (1.25V typical). After V EN-TH(R) has been crossed, and the minimum supply voltage, VIN UVLO(R), have both been satisfied, the part begins the soft-start sequence described in Section 7.3.2. The EN pin can be used to power down the device by reducing the voltage between the EN pin and PGND pin below the enable input low threshold VEN-TH(F) 1V (typical). www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMR60440-Q1

A resistor divider between VIN and PGND with the center point connected to the EN pin can be used to implement the VIN UVLO. To begin, select the input voltage at which the device turns off, choose the value of RENT, then calculate the required R ENB. After RENB has been calculated, the resulting turn-on input voltage can be calculated. See Figure 7-1, Equation 1, and Equation 2 to determine the EN resistors required. If the VIN UVLO feature is not needed, the EN pin can be connected directly to VIN. R ENB = V EN − T H F VIN t u r n − of f − V EN − TH F × R E N T (1) VIN t ur n − on = 1 + R ENT R ENB × V EN − TH R (2) Where:

• VINturn-off represents the input voltage at which the LMR60440-Q1 turns off.
• VINturn-on represents the input voltage at which the LMR60440-Q1 turns on. EN RENT RENB VIN Figure 7-1. VIN UVLO Using the EN Pin

7.3.2 Soft Start and Recovery from Dropout

The LMR60440-Q1 uses soft-start to prevent output voltage overshoots and large inrush currents during start- up. The soft-start time is fixed internally at 6ms (typical). The LMR60440-Q1 device operates correctly even if there is a voltage present on the output before the device is enabled. To start-up the LMR60440-Q1 and initiate the soft-start sequence, the voltage applied to the VIN and EN pins must exceed VIN UVLO(R) and V EN-TH(R) respectively. After these conditions are met, the soft-start sequence initiates and the output voltage reaches the set-point in 6ms (typical). Dropout occurs when the input voltage falls below the voltage level of the output voltage setpoint. During this condition, the output voltage tracks the input voltage. PG (2V/DIV) VOUT (2V/DIV) EN (2V/DIV) 2ms/DIV Figure 7-2. Enable Soft Start LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

12 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

7.3.3 Frequency Selection With RT

A resistor placed between the RT pin and PGND is used to select the set point switching frequency of the LMR60440-Q1 typically between 200kHz and 2.2MHz. The set point switching frequency represents the switching frequency which can occur if the LMR60440-Q1 is operating in continuous conduction mode with spread spectrum disabled. See also Section 7.3.9 for more information on how spread spectrum affects the switching frequency. Use the following equation to determine the RT resistor value for a desired set point switching frequency. RT = f sw − 69.6 × 10 − 9 Where:

• RT: represents the RT resistor value in ohms (Ω)
• fsw: represents the set point switching frequency in hertz (Hz) S w i t c h i n g F r e q u e n c y ( k H z ) RT Resistor (k) 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0 1 8 0 0 2 0 0 0 2 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 Figure 7-3. RT Values vs Switching Frequency Table 8-2 lists the recommended RT values for 400kHz, 1MHz and 2MHz switching frequencies.

7.3.4 MODE/SYNC Pin Control

The MODE/SYNC pin of the LMR60440-Q1 is an input pin used to select the mode of operation of the device or to synchronize the switching frequency to an external clock frequency. In the absence of an external clock, the RT resistor determines the switching frequency. Do not float the MODE/SYNC pin. If this pin is driven by a high impedance source, connect a pull up or pull down resistor to prevent this pin from floating. For more information on the modes of operation, see also Section 7.4. The MODE/SYNC pin can be used to dynamically change the mode of operation for systems that require more than a single mode of operation. There are three selectable modes of operation:

• AUTO mode: pulse frequency modulation (PFM) operation is enabled during light load and diode emulation
• FPWM mode: in FPWM mode, diode emulation is disabled if the input voltage is less than VINOVP(R), allowing current to flow backwards through the inductor. This allows operation at full frequency even without load
• SYNC mode: the internal clock aligns to an external signal applied to the MODE/SYNC pin. The frequency of the external clock signal must be within the range of 1 × to 2 × the frequency set by the RT resistor. The high level of the external clock must be greater than or equal to VIH_CLK, and the low level of the external clock must be less than or equal to VIL_CLK. The external clock must not exceed the MODE/SYNC pin rating provided in Absolute Maximum Ratings table. As long as output voltage can be regulated at full frequency and is not limited by minimum off time or minimum on time, the clock frequency is matched to the frequency www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMR60440-Q1

of the signal applied to the MODE/SYNC pin. While the device is in SYNC mode, the device operates as though in FPWM mode. Diode emulation is disabled, allowing the frequency applied to the MODE/SYNC pin to be matched without a load. To dynamically change between modes of operation, a valid sync signal must be applied. The following table shows a summary of the pulse dependent mode selection settings. Table 7-1. Pulse-Dependent Mode Selection Settings MODE/SYNC INPUT MODE > VIH_FPWM FPWM with spread spectrum factory setting < VIL_FPWM AUTO mode with spread spectrum factory setting Synchronization clock SYNC MODE If dynamically switching between modes of operation is not needed, this pin can be held at a constant voltage resulting in a fixed mode of operation. For auto mode, this pin can be short circuited to PGND or pulled below VIL_FPWM. For FPWM mode, this pin can be short circuited to the RT pin or pulled up to V IH_FPWM with an external voltage source. See also Electrical Characteristics .

7.3.5 Output Voltage Selection

The LMR60440-Q1 allows users to configure the output voltage of the LMR60440-Q1 to be either fixed or adjustable depending on the presence of a feedback resistor divider connected to the FB pin. The fixed output voltage is determined based on the orderable part number. See also Section 4. If fixed output voltage is desired, the FB pin can be shorted directly to the output voltage rail. There must be less than 1 Ω between the FB pin and the output voltage rail for the device to enter into fixed output voltage. If an adjustable output voltage is desired, the parallel combination of the top and bottom feedback resistors must exceed 3k Ω. After the top feedback resistor is selected, RFBT, the following equation can be used to select the bottom feedback resistor, RFBB. R FBB = V FB V OUT − V FB × R FBT (4) Where VFB is typically 1V. RFBT RFBB FB PGND VOUT Figure 7-4. Feedback Resistor Setup for Adjustable VOUT

7.3.6 Current Limit

The LMR60440-Q1 uses two current limits to limit the total load current delivered to the output. These limits are known as the high side peak current limit (I HS-LIM) and the low side valley current limit (I LS-LIM). After IHS-LIM is reached on the inductor current, the high side MOSFET is turned off and the low side MOSFET is turned ON until the inductor current falls below I LS-LIM. This action can result in a reduction in switching frequency and can be referred to as soft current limit. Because the inductor current is limited to switch between I HS-LIM and ILS-LIM, the maximum output current is very close to the average between these two values. If the load demands a current that is greater than the maximum output current, the output voltage decreases. If the output voltage LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

14 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

decreases such that the voltage on the FB pin drops below V HIC, then the device enters into hiccup mode. See also Section 7.3.7. The high side current limit in LMR60440-Q1 varies as the duty cycle varies. This behavior is characteristic of peak current mode control and helps avoid subharmonic oscillation at higher duty cycles. Figure 7-5 shows the typical high side current limit. The LMR60440-Q1 also implements a negative current limit (I LS-NEG-LIM) to limit the amount of current the low-side MOSFET can sink. After the negative current limit is reached, the low-side MOSFET turns off. D u t y c y c l e High side current limit (A) 4 . 2 4 . 5 4 . 8 5 . 1 5 . 4 5 . 7 6 . 3 6 . 6 6 . 9 7 . 2 Figure 7-5. Typical high side current limit IHS-LIM as a function of duty cycle D

7.3.7 Hiccup Mode

To prevent excessive heating and power consumption under sustained short-circuit conditions, a hiccup mode is included. If an over current condition is maintained, the LMR60440-Q1 device shuts off the output and waits for approximately 85ms, after which the LMR60440-Q1 restarts operation by activating soft start. The LMR60440-Q1 enters into hiccup mode of operation after the following conditions are met:

• The soft-start sequence has completed
• The voltage on FB pin drops below VHIC Hiccup mode of operation is categorized by periods of non-switching followed by periods of switching where the device tries to startup and regulate the output voltage to the desired set point. After the fault on the output is removed, the device enters soft start and starts up normally. See also Section 7.3.2 for details on soft start.

7.3.8 Power-Good Function

The power-good function of the LMR60440-Q1 can be used to reset a system microprocessor whenever the output voltage is out of regulation or to facilitate power sequencing of down stream components. This feature is an optional feature that is implemented by including a pullup resistor between the PG pin and an excellent voltage supply. See also the Recommended Operating Conditions table for the recommended range of pullup reference voltage. The power-good output is valid after the soft-start sequence has completed and after the input voltage has risen above VIN(PG-VALID). After both of these conditions are met, the voltage between PG and GND indicates whether the output voltage is within regulation or not. A logic HIGH signal indicates that the output voltage is within regulation while a logic LOW signal represents that the output voltage is not in regulation. A deglitch filter has been included to make sure that spurious glitches on the output voltage do not effect the PG pin output. www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMR60440-Q1

The PG pin is pulled low under the following conditions:

• Output voltage is higher than the PGOOD over-voltage rising threshold (VPG-OVP(R)) for a duration of at least tPG-DEGLITCH
• Output voltage falls lower than the PGOOD under-voltage falling threshold (VPG-UV(F)) for a duration of at least tPG-DEGLITCH After the PG pin has been pulled low following a fault condition at the output, the PG pin voltage must remain low for at least t PG-DEASSERT or about 2ms (typical). After t PG-DEASSERT has passed, one of the following conditions must be satisfied for the PG pin voltage to be pulled up:
• Assuming recovery form an undervoltage fault, the output voltage must rise higher than the PGOOD undervoltage rising threshold (VPG-UV(R)) and remain below the over-voltage rising threshold (VPG-OVP(R)) for a duration of at least tPG-DEGLITCH.
• Assuming recovery from an overvoltage fault, the output voltage must fall lower than the PGOOD overvoltage falling threshold (VPG-OVP(F)) and remain above the undervoltage falling threshold for a duration of at least tPG-DEGLITCH. VOUT PG VPG-OVP(R) High = Power Good VPG-UVP(R) Low = Fault time time tPG-DEGLITCH tPG-DEGLITCH VPG-OVP(F) tPG-DEGLITCH tPG-DEGLITCH VPG-UVP(F) tPG-DEASSERT Figure 7-6. Power-Good Thresholds

7.3.9 Spread Spectrum

The purpose of the spread spectrum is to reduce peak emissions at specific frequencies by spreading emissions across a wider range of frequencies than a part with fixed frequency operation. In most systems containing the LMR60440-Q1 device, low frequency conducted emissions from the first few harmonics of the switching frequency can be easily filtered. The LMR60440-Q1 spreads the switching frequency 18% above of the set point switching frequency established by the RT resistor. This means that the set point switching frequency established by the RT resistor represents the lower bound of the switching frequency while the device is operating with spread spectrum. The following conditions overrides spread spectrum, turning spread spectrum off: 1. An external clock is applied to the MODE/SYNC terminal. 2. The clock is slowed due to operation at low input voltage − this action is operation in dropout. 3. The clock is slowed due to high input voltage − the on-time of the high side switch approached tON-MIN. 4. The clock is slowed under light load in auto mode – this action occurs when the device switches in PFM mode. In FPWM mode, spread spectrum is active even if there is no load. LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

16 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

7.4 Device Functional Modes

7.4.1 Shutdown

The LMR60440-Q1 shuts down most internal circuitry and both high side and low side power switches connected to the switch node under any of the following conditions: 1. EN is below VEN-TH(R) 2. VIN is below VINUVLO(R) 3. Junction temperature exceeds TSD Note that the above conditions have hysteresis. Also, PG remains active to a very low input voltage, VIN(PG-VALID).

7.4.2 Active Mode

The LMR60440-Q1 is in an active mode whenever the EN pin voltage has risen above V EN-TH(R), the input voltage exceeds VIN UVLO(R), and no other fault conditions are present. The simplest way to enable the LMR60440-Q1 is to connect the EN pin to VIN, which allows self start-up when the applied input voltage exceeds the VINUVLO(R). In active mode, the LMR60440-Q1 is in one of the following modes:

• Continuous conduction mode (CCM) with fixed switching frequency when the load current is above half of the inductor current ripple
• Auto mode - light load operation: pulse frequency modulation (PFM) where switching frequency is reduced at light load
• FPWM mode - light load operation: CCM mode when the load current is lower than half of the inductor current ripple
• Minimum on-time: at high input voltage and low output voltages, the switching frequency is reduced to maintain regulation
• Dropout mode: when switching frequency is reduced to minimize voltage dropout between input and output

7.4.2.1 Continuous Conduction Mode (CCM)

In CCM, the LMR60440-Q1 supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) switches with varying duty cycle (D). During the HS switch on time, the SW pin voltage, V SW, swings up to approximately V IN, and the inductor current, i L, increases with a linear slope. The HS switch is turned off by the control logic. During the HS switch off time, t OFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the V SW to swing below ground by the voltage drop across the LS switch. The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on time of the HS switch over the switching period: D = T ON T SW (5) In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = V OUT V IN (6) www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMR60440-Q1

D = t t SW Voltage tON tSW VIN tSW tON tOFF VOUT VIN Figure 7-7. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

7.4.2.2 Auto Mode - Light Load Operation

If MODE/SYNC voltage is below V IL(MODE/SYNC), reverse current in the inductor is not allowed – this feature is called diode emulation (DEM). DEM occurs when the load current is less than half of the inductor ripple current. After the inductor current falls below the zero-cross current limit, the LS FET turns off and inductor current flows through the body diode of the LS FET. After current is reduced to a low value with fixed input voltage, on time is constant. Regulation is then achieved by adjusting frequency. This mode of operation is called pulse frequency modulation (PFM) mode regulation. iL VSW ILPK IOUT Inductor Current D = t t SW Voltage tON tSW VIN tSW tON tOFF tHIGHZ VOUT VIN Figure 7-8. PFM Operation In PFM operation, a small positive DC offset can be observed on the output voltage as the output capacitors become overcharged due to lack of load. If this DC offset on V OUT is not acceptable, a dummy load at V OUT or FPWM mode can be used to reduce or eliminate this offset. This offset typically does not exceed 1% of V OUT that the device regulates to while heavily loaded. 1% Above Set point VOUT Set Point Output Voltage Current Limit VOUT Output Current IOUT0 Figure 7-9. Steady State Output Voltage vs Output Current in Auto Mode LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

18 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

7.4.2.3 FPWM Operation - Light Load Operation

In forced pulse width modulation (FPWM) mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry. See also Section 6.5 . iL VSW ILPK IOUT Iripple Inductor Current D = t t SW Voltage tON tSW VIN tSW tON tOFF VOUT VIN Figure 7-10. FPWM Mode Operation FPWM mode can be achieved in any of the following ways:

• Connect MODE/SYNC directly to RT pin.
• Apply an external voltage across MODE/SYNC and PGND that is greater than VIH(MODE/SYNC).
• Apply an appropriate external clock signal. See also Table 7-1. Under operating conditions where the minimum on-time or minimum off-time can be exceeded, the frequency reduces even while operating in FPWM to maintain minimum timing specifications. Additionally, in cases where the input voltage exceeds VIN OVP(R) the LMR60440-Q1 prevents negative currents from flowing through the inductor and the LMR60440-Q1 implements PFM switching. After the input voltage falls below VIN OVP(F), the device again operates in FPWM and allows negative inductor currents.

7.4.2.4 Minimum On-Time

Minimum on-time refers to the minimum amount of time the high side MOSFET can turn on. The LMR60440-Q1 regulates the output voltage even if the input-to-output voltage ratio requires an on-time less than the minimum on-time, t ON-MIN, for the given frequency setting. The LMR60440-Q1 accomplishes this by folding back the switching frequency to support the same input-to-output voltage ratio while maintaining an on-time of t ON-MIN. The LMR60440-Q1 can support a minimum on-time of 30ns (typical). Use Equation 7 to estimate the on-time for a given operating condition. t ON = V O U T V IN × f S W (7) Where:

• tON = high side MOSFET on-time
• VOUT = output voltage
• VIN = input voltage
• fSW = switching frequency

7.4.2.5 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the required duty cycle. At a given clock frequency, duty cycle is limited by minimum off time. After this limit is reached as Figure 7-11 shows, if clock frequency was to be maintained, the output voltage falls. Instead of allowing the output voltage to drop, the LMR60440-Q1 extends the high-side switch on time past the end of the clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle after www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMR60440-Q1

peak inductor current is achieved or after a predetermined maximum on time of approximately 10µs passes. As a result, after the needed duty cycle cannot be achieved at the selected clock frequency due to the existence of a minimum off time, frequency drops to maintain regulation. After the input voltage increases beyond the output voltage setpoint, the output voltage increases as though in soft start as described in Section 7.3.2. iL VSW IOUT Iripple Inductor Current - IOUT × RDSLS D = t t SW Voltage tON tSWVIN tSW > Clock setting tOFF = tOFF_MIN tON < tON_MAX VOUT VIN ILPK Figure 7-11. Dropout Waveforms LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

20 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The LMR60440-Q1 is a step-down DC–DC converter, typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 4A. The following design procedure can be used to select components for the LMR60440-Q1. Refer to the following figure for a reference schematic as well as the following table to assist in component selection.

8.2 Typical Application

Figure 8-1 shows a typical application circuit for the LMR60440-Q1. This device is designed to function over a wide range of external components and system parameters. As a quick-start guide, Table 8-2 provides typical component values for a range of the most common operating conditions. LMR60440-Q1 PGND VIN EN MODE/ SYNC RT BOOT SW FB PG CINHF PGND VIN PGND CBOOT COUT PGND VOUT PGND RENT RENB CIN PGND RT PGND PGNDPGND Option 1 Option 2 Option 3 PGND VPG RFBT RFBB VMODCLK Option 4 Figure 8-1. LMR60440-Q1 Reference Schematic Table 8-1. Description of MODE/SYNC Pin Options Option 1 To synchronize to an external clock, drive the MODE/SYNC pin directly from the clock. Option 2 An appropriate voltage VMOD can be used at the MODE/SYNC to dynamically change between auto and FPWM modes. Option 3 Ground the MODE/SYNC to run the device in auto mode. Option 4 Connect the MODE/SYNC to RT to run the device in FPWM mode. See also MODE/SYNC Pin Control. www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMR60440-Q1

Table 8-2. Recommended Passive Components FSW (kHz) VOUT (V) IOUT (A) L (μH) COUT (1) RFBT (kΩ) RFBB (kΩ) CIN (μF) CBOOT (nF) RT (kΩ) 400 3.3 4 4.7 54 SHUNT DNP 4.7 100 86.6 400 3.8 4 4.7 54 SHUNT DNP 4.7 100 86.6 400 5 4 5.6 54 SHUNT DNP 4.7 100 86.6 1000 3.3 4 2.2 44 SHUNT DNP 4.7 100 33.2 1000 3.8 4 2.2 44 SHUNT DNP 4.7 100 33.2 1000 5 4 2.2 44 SHUNT DNP 4.7 100 33.2 2000 3.3 4 1.5 20 SHUNT DNP 4.7 100 15 2000 3.8 4 1.5 20 SHUNT DNP 4.7 100 15 2000 5 4 1.5 20 SHUNT DNP 4.7 100 15 (1) Rated capacitance

8.2.1 Design Requirements

For this design example, use the parameters listed in the following table as the input parameters. Table 8-3. Design Parameters DESIGN PARAMETER VALUE COMMENT Input voltage range 12V (typical), 4V to 36V This converter runs continuously up to 36V. Output voltage 3.3V Fixed option used Output current range No load to 4A Switching frequency 2MHz Light load mode Switchable Spread spectrum Enabled Factory option

8.2.2 Detailed Design Procedure

8.2.2.1 Switching Frequency Selection

The choice of switching frequency is a compromise between conversion efficiency and overall design size. Lower switching frequency implies reduced switching losses and usually results in higher system efficiency. However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more

8.2.2.2 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum output current. Note that when selecting the ripple current for applications with much smaller maximum load than the maximum available from the device, use the maximum device current. Use Equation 8 to calculate the value of inductance. The constant K is the percentage of inductor current ripple. For this example, L = V IN − V O UT f sw × K × I O UT ma x × V OUT V I N (8) Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, IHS-LIM (see also Electrical Characteristics ). This size makes sure that the inductor does not saturate, even during a short circuit on the output. When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly. Although the valley current limit, I LS-LIM, is designed to reduce the risk of current runaway, a saturated inductor can cause the current to rise to high values very rapidly. This action can lead to component damage. Do not allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some relaxation in the current rating of the LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

22 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

inductor. However, powered iron cores have more core losses at frequencies above about 1MHz. In any case, the inductor saturation current must not be less than the maximum peak inductor current at full load. Use the following equation to find the minimum inductance value to avoid subharmonic oscillations: L mi n = M × V OUT f sw (9) Where:

• M = 0.27

8.2.2.3 Output Capacitor Selection

The LMR60440-Q1 is designed to optimize the required output capacitance while also allowing for high performance. This section describes the theory to calculate the required output capacitance to achieve a certain set of design parameters. The peak current mode control scheme of the LMR60440-Q1 device allows operation over a wide range of inductor and output capacitor combinations. The output capacitance is responsible for maintaining the desired output voltage during operation. The output capacitance impacts several key performance factors including:

• The amount of output voltage ripple during steady state operation
• The overshoot and undershoot of the output voltage when a load transient occurs
• Loop stability During steady state operation, the inductor supplies a triangular current to the load. The AC portion of this triangular current is filtered out by the output capacitance while the DC portion passes through to the load. The AC current through the output capacitance and the equivalent series resistance (ESR) of this capacitance both contribute to the output voltage ripple. Use the following equation to estimate the amount of peak to peak output voltage ripple required for a given output capacitance: V ri p ple ≈ ΔI L × ESR 2 + 1 8 × f s w × C OUT 2 (10) Where:
• ΔIL = the peak to peak inductor current Refer to Table 8-2 for typical output capacitor values for 3.3V and 5V output voltage applications. In this example, a single 22 μF multilayer ceramic capacitor is used. For other output voltage and switching frequency designs, WEBENCH can be used as a starting point for selecting the value of the output capacitor. In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic capacitor placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1nF to 100nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics. Most ceramic capacitors deliver far less capacitance than the rating of the capacitor indicates. Be sure to check any capacitor selected for initial accuracy, temperature derating, and voltage derating. Table 8-2 has been generated assuming typical derating of 16V, X7R, automotive grade capacitors. If lower voltage rated, non-automotive grade, or lower temperature rated capacitors are used, more capacitors than listed are likely to be needed.

8.2.2.4 Input Capacitor Selection

Input capacitors serve two important functions. The first is to reduce input voltage ripple into the LMR60440-Q1 and the input filter of the system. The second is to reduce high frequency noise. These two functions are implemented most effectively with separate capacitors. See Table 8-4. www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMR60440-Q1

Table 8-4. Input Capacitor CAPACITOR RECOMMENDED VALUE COMMENT CIN_HF 0.1µF This capacitor is used to suppress high frequency noise originating during switching events. Place the capacitor as close to the LMR60440-Q1 devices as design rules allow. Position is more important than exact capacity. After high frequency propagates into a system, suppressing or filtering can be hard. Because this capacitor is exposed to battery voltage in systems that operate directly off of battery, TI recommends 50V or greater rating. CIN 4.7µF This capacitance is used to suppress input ripple and transients due to output load transients. If CIN is too small, input voltage can dip during load transients resetting the system if the system is operated under low voltage conditions. TI recommends 4.7µF adjacent to the LMR60440-Q1 device. Because this capacitor is exposed to battery voltage in systems that operate directly off of battery, TI recommends 50V or greater rating. The values of C IN_HF and C IN presented in Table 8-4 can be used in most applications. If a certain amount of input voltage ripple is required, use the calculated input capacitance based on Equation 11, but not less than recommended in the above table. C I N ≥ D × 1 − D × I OUT ΔV IN _ PP × f s w (11) Where:

• D = Duty Cycle = VOUT/VIN
• IOUT = DC output current
• ΔVIN_PP = peak to peak input voltage ripple
• fSW = switching frequency Use Equation 12 to compare the RMS current rating of the selected input capacitors to make sure the input capacitors are capable of supplying the input switching current. I IN _ RMS _ max = I O UT × D × 1 − D + 1 12 × V OUT L × f sw × I O UT × 1 − D 2 × D (12)

8.2.2.5 Bootstrap Capacitor (CBOOT) Selection

The bootstrap capacitor (CBOOT) is connected between the BOOT and SW pins and provides the gate charge for the high side MOSFET. Place this capacitor as close to the LMR60440-Q1 as design rules allow. TI recommends a high quality ceramic capacitor of 100nF and at least 10V.

8.2.2.6 FB Voltage Divider for Adjustable Output Voltages

The LMR60440-Q1 device can be configured to operate in either fixed or adjustable output voltage modes. For fixed output voltages as specified by the device orderable part number, simply connect the output voltage rail directly to the FB pin. When other output voltages are required, a resistor divider between the output voltage rail and ground with the FB pin as the center point set the output. Use the following equation to calculate the output voltage given a specific feedback divider. V OUT = V F B × 1 + R FBT R F B B (13) Alternatively, if the output voltage and RFBT are already known, use the following equation to calculate the value of RFBB. R FBB = R FBT × V FB V O UT − V FB (14) Note that typically 100kΩ is used for RFBT. LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

24 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

8.2.2.6.1 Feedforward Capacitor (CFF) Selection

In cases where an adjustable output voltage configuration is required, a feedforward capacitor (CFF) can be placed in parallel with the RFBT to improve transient performance and loop-phase margin. Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor application note is helpful when experimenting with a feedforward capacitor.

8.2.2.7 RPG - PG Pullup Resistor

The PG pin is an open drain output that is used as a monitoring pin. If needed, a 100k Ω can be used to pull up to a suitable voltage supply. See also Section 6.3 for a range of recommended PG pin pullup voltages. Other considerations, such as power consumption, can increase any of the values listed above. www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMR60440-Q1

8.2.3 Application Curves

The following characteristics apply to the Figure 8-1 circuit. These parameters are not tested and represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, TA = 25°C. O u t p u t C u r r e n t ( A ) Efficiency (%) 7 0 7 2 7 4 7 6 7 8 8 0 8 2 8 4 8 6 8 8 9 0 9 2 9 4 V I N = 8 V V I N = 1 2 V V I N = 2 4 V VOUT = 3.3V Fsw = 2MHz Mode = Auto Figure 8-2. Efficiency O u t p u t C u r r e n t ( A ) Efficiency (%) 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 7 0 7 2 7 4 7 6 7 8 8 0 8 2 8 4 8 6 8 8 9 0 9 2 9 4 V I N = 8 V V I N = 1 2 V V I N = 2 4 V VOUT = 3.3V Fsw = 2MHz Mode = FPWM Figure 8-3. Efficiency O u t p u t C u r r e n t ( A ) Efficiency (%) 7 8 8 0 8 2 8 4 8 6 8 8 9 0 9 2 9 4 9 6 V I N = 8 V V I N = 1 2 V V I N = 2 4 V VOUT = 3.3V Fsw = 400kHz Mode = Auto Figure 8-4. Efficiency O u t p u t C u r r e n t ( A ) Efficiency (%) 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 8 0 8 2 8 4 8 6 8 8 9 0 9 2 9 4 9 6 V I N = 8 V V I N = 1 2 V V I N = 2 4 V VOUT = 3.3V Fsw = 400kHz Mode = FPWM Figure 8-5. Efficiency O u t p u t C u r r e n t ( A ) Efficiency (%) 7 2 7 4 7 6 7 8 8 0 8 2 8 4 8 6 8 8 9 0 9 2 9 4 9 6 V I N = 8 V V I N = 1 2 V V I N = 2 4 V VOUT = 5V Fsw = 2MHz Mode = Auto Figure 8-6. Efficiency O u t p u t C u r r e n t ( A ) Efficiency (%) 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 7 5 7 7 7 9 8 1 8 3 8 5 8 7 8 9 9 1 9 3 9 5 V I N = 8 V V I N = 1 2 V V I N = 2 4 V VOUT = 5V Fsw = 2MHz Mode = FPWM Figure 8-7. Efficiency LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

26 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

L o a d C u r r e n t ( A ) Output Voltage (V) 3 . 2 5 3 . 2 6 3 . 2 7 3 . 2 8 3 . 2 9 3 . 3 3 . 3 1 3 . 3 2 3 . 3 3 3 . 3 4 V I N = 8 V V I N = 1 3 . 5 V V I N = 2 4 V V I N = 3 6 V Device type = 4A 3.3V fixed output Mode = Auto FSW = 2MHz Figure 8-14. Load Regulation M a x i m u m A m b i e n t T e m p e r a t u r e ( ° C ) Output Current (A) 5 5 6 5 7 5 8 5 9 5 1 0 5 1 1 5 1 2 5 1 3 5 V I N = 1 2 V VOUT = 5V FSW = 400kHz IOUT = 4A LMR60440QEVM No air flow Figure 8-15. Output Current vs Maximum Ambient Temperature M a x i m u m A m b i e n t T e m p e r a t u r e ( ° C ) Output Current (A) 5 5 6 5 7 5 8 5 9 5 1 0 5 1 1 5 1 2 5 1 3 5 V I N = 1 2 V VOUT = 5V FSW = 2MHz IOUT = 4A LMR60440QEVM No air flow Figure 8-16. Output Current vs Maximum Ambient Temperature Device type = 4A 3.3V fixed output Mode = FPWM FSW = 2MHz Figure 8-17. 20mA to 4A Load Transient Device type = 4A 3.3V fixed output Mode = FPWM FSW = 2MHz Figure 8-18. 2A to 4A Load Transient Device type = 4A 3.3V fixed output Mode = Auto FSW = 2MHz Figure 8-19. Start-Up Operation LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

28 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

VOUT = 3.3V FSW = 2MHz IOUT = 4A Frequency tested: 150kHz to 30MHz Figure 8-26. Radiated EMI Monopole versus CISPR25 Limits, LMR60440QEVM VOUT = 3.3V FSW = 2MHz IOUT = 4A Frequency tested: 30MHz to 300MHz Figure 8-27. Radiated EMI Bicon Vertical versus CISPR25 Limits, LMR60440QEVM VOUT = 3.3V FSW = 2MHz IOUT = 4A Frequency tested: 30MHz to 300MHz Figure 8-28. Radiated EMI Bicon Horizontal versus CISPR25 Limits, LMR60440QEVM VOUT = 3.3V FSW = 2MHz IOUT = 4A Frequency tested: 300MHz to 1GHz Figure 8-29. Radiated EMI Log Vertical versus CISPR25 Limits, LMR60440QEVM VOUT = 3.3V FSW = 2MHz IOUT = 4A Frequency tested: 300MHz to 1GHz Figure 8-30. Radiated EMI Log Horizontal versus CISPR25 Limits, LMR60440QEVM GND VIN GND CFILT2CFILT1 CFILT3 CFILT4 LISN + LISN - CBULK LFILT Figure 8-31. Typical Input EMI Filter Schematic LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

30 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

Table 8-5. Typical EMI Filter Components FSW(kHz) CFILT1(μF) CFILT2(μF) CFILT3(μF) CFILT4(μF) LFILT(μH) CBULK(μF) 2000 2.2 2.2 DNP DNP 2.2 47 PGND VIN EN MODE/ SYNC RT BOOT SW FB PG 4.7µF PGND VIN PGND PGND PGND 100nF COUT PGND VOUT RT 100nF PGND 100kΩ VOUT Figure 8-32. Example Application Circuit Table 8-6. BOM for Typical Applications Curves U1 FSW (kHz) VOUT L1 (μH) NOMINAL COUT (μF) RT(kΩ) LMR604403SRAKRQ1 2000 3.3 1.5 2 × 10 15

8.3 Power Supply Recommendations

The characteristics of the input supply must be compatible with the specifications found in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded regulator. Use the following equation to calculate the average input current. I IN = V O UT × I OUT V I N × η (15) where η is the efficiency. If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily shut down and reset. The best way to solve these kinds of issues is to limit the distance from the input supply to the regulator or plan to use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors help dampen the input resonant circuit and reduce any overshoots. A value in the range of 20µF to 100µF is usually sufficient to provide input damping and help to hold the input voltage steady during large load transients. Sometimes, for other system considerations, an input filter is used in front of the regulator. This action can lead to instability, as well as some of the effects mentioned above, unless designed carefully. The AN-2162 www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LMR60440-Q1

Simple Success With Conducted EMI From DC/DC Converters application note provides helpful suggestions when designing an input filter for any switching regulator. In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device has a snap-back characteristic (thyristor type). TI does not recommend the use of a device with this type of characteristic. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the output voltage of the regulator, the output capacitors discharge through the device back to the input. This uncontrolled current flow can damage the device.

8.4 Layout

8.4.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the excellent performance of the design. Poor PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground, as shown in Figure 8-33 . This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Figure 8-34 shows a recommended layout for the critical components of the LMR60440-Q1.

• Place the input capacitors as close as possible to the VIN and GND terminals.
• Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the BOOT and SW pins.
• Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if used, physically close to the device. The connections to FB and GND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, the latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator.
• Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat dissipation path.
• Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
• Provide enough PCB area for proper heat-sinking. Enough copper area must be used to make sure a low RθJA, commensurate with the maximum load current and ambient temperature. The top and bottom PCB layers must be made with two ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes.
• Keep the switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI. See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies application note
• Simple Switcher PCB Layout Guidelines application note
• Construction Your Power Supply- Layout Considerations seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application note LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

32 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

Figure 8-33. Current Loops With Fast Edges

8.4.1.1 Ground and Thermal Plane Considerations

As mentioned above, TI recommends to use one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces. A ground plane also provides a quiet reference potential for the control circuitry. The PGND pin is connected to the source of the internal low side MOSFET switch. This pin must be connected directly to the ground of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load variations. TI recommends to provide adequate device heat sinking by using the PGND of the IC as the primary thermal path. Thermal vias must be evenly distributed under the PGND pin. Use as much copper as possible for system ground plane on the top and bottom layers for the best heat dissipation. TI recommends to use a four-layer board with the copper thickness, starting from the top, as: 2oz, 1oz, 1oz, 2oz. A four-layer board with enough copper thickness and proper layout provides low current conduction impedance, proper shielding and lower thermal resistance. Resources for thermal PCB design:

• AN-2020 Thermal Design By Insight, Not Hindsightapplication note
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application note
• Semiconductor and IC Package Thermal Metrics application note
• Thermal Design made Simple with LM43603 and LM43602 application note
• PowerPAD™ Thermally Enhanced Package application note
• PowerPAD Made Easy application note
• Using New Thermal Metrics application note www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LMR60440-Q1

8.4.2 Layout Example

Figure 8-34. Recommended Layout Example for RAK package (2.5mm × 2mm) RT CINHF CIN COUT RPGCBOOT RT MODE PGND FB PG BOOT SW EN VIN NC NC Figure 8-35. Recommended Layout Example for RBM Package (3.5mm × 2.5mm) LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

34 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.1.2 Device Nomenclature

Figure 9-1 shows the device naming nomenclature of the LMR60440-Q1. See the Device Comparison Table for the availability of each variant. Contact a TI sales representatives or visit TI's E2E support forum for detail and availability of other options; minimum order quantities apply. PACKAGE RAKR: WQFN-HR 9-pin large reel RBMR: WQFN-HR 11-pin large reel LMR604 X 0 X X X XXXR Q1 SPREAD SPECTRUM S: Enabled No Character: Disabled MAX OUTPUT CURRENT 2: 2A 3: 3A 4: 4A AUTOMOTIVE GRADE FIXED VOUT 1: 1.8V 3: 3.3V 4: 3.8V 5: 5V VARIANT No Character: A’ variant, or – RBM package B: ‘B’ variant Figure 9-1. Device Naming Nomenclature

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application note
• Texas Instruments, Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x application note
• Texas Instruments, Constructing Your Power Supply – Layout Considerations application note
• Texas Instruments, AN-1229 Simple Switcher PCB Layout Guidelines application note
• Texas Instruments, Using New Thermal Metrics application note
• Texas Instruments, PowerPAD™ Made Easy application note
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application note
• Texas Instruments, Thermal Design made Simple with LM43603 and LM43602 application note
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note
• Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application note
• Texas Instruments, AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application note
• Texas Instruments, Simple Success with Conducted EMI for DC-DC Converters application note
• Texas Instruments, Understanding and Applying Current-Mode Control Theory application note
• Texas Instruments, Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor application note www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LMR60440-Q1

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

HotRod™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 www.ti.com

36 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: LMR60440-Q1

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2026) to Revision B (June 2026) Page Changes from Revision * (December 2024) to Revision A (March 2026) Page

• Added a table note to cover the transient voltage specification on the SW pin to the Absolute Maximum
• Changed tOFF-MIN from 89ns to 100ns and added specification maximum value in the Electrical
• Updated the RT equation and the figure showing RT resistor values against switching frequency in Frequency
• Added a paragraph and figure showing variation of high-side current limit with duty cycle in Current Limit ...14
• Changed the typical switching frequency spread of spread spectrum from 16% to 18% in Spread Spectrum ...
• Deleted note from Figure 8-1 and updated the figure to include Option 4 on MODE/SYNC pin in Typical

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LMR60440-Q1 SNAS874B – DECEMBER 2024 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LMR60440-Q1

www.ti.com 2-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMR604403SBRAKRQ1 Active Production WQFN-HR (RAK) | 9 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 150 43SBQ LMR604403SRBMRQ1 Active Production WQFN-HR (RBM) | 11 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 150 43RBM LMR604404SBRAKRQ1 Active Production WQFN-HR (RAK) | 9 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 150 44SBQ LMR604405SBRAKRQ1 Active Production WQFN-HR (RAK) | 9 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 150 45SBQ PLMR604403SRBMRQ1 Active PreproductionWQFN-HR (RBM) | 11 3000 | LARGE T&R - Call TI Call TI -40 to 150 XLMR604403SRAKRQ1 Active Preproduction WQFN-HR (RAK) | 9 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 X43SQ XLMR604403SRAKRQ1.A Active Preproduction WQFN-HR (RAK) | 9 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 X43SQ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 2-Jul-2026 OTHER QUALIFIED VERSIONS OF LMR60440-Q1 :

• Catalog : LMR60440 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LMR604403SBRAKRQ1 WQFN- HR LMR604403SRBMRQ1 WQFN- HR LMR604404SBRAKRQ1 WQFN- HR LMR604405SBRAKRQ1 WQFN- HR XLMR604403SRAKRQ1 WQFN- HR Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR604403SBRAKRQ1 WQFN-HR RAK 9 3000 210.0 185.0 35.0 LMR604403SRBMRQ1 WQFN-HR RBM 11 3000 210.0 185.0 35.0 LMR604404SBRAKRQ1 WQFN-HR RAK 9 3000 210.0 185.0 35.0 LMR604405SBRAKRQ1 WQFN-HR RAK 9 3000 210.0 185.0 35.0 XLMR604403SRAKRQ1 WQFN-HR RAK 9 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 2.6 2.4 3.6 3.4 0.8 0.7 0.05 0.00 0.723 .000 PKG 0 1.448 0.723 1.448 2X 0.85 .000 PKG 0 2X 0.225 2X 0.275 2X 0.95 1.463 1.463 6X 0.5 0.4 0.29 0.19 0.35 0.25 2.074 1.974 2X 0.355 0.255 2X 0.35 0.25 2X 0.55 0.45 2X 0.325 0.225 6X 0.3 0.2

0.1 MIN

(1.223) (11 ) (0.1) TYP WQFN-HR - 0.8 mm max heightRBM0011A PLASTIC QUAD FLATPACK - NO LEAD 4231496/D 03/2026 0.08 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Minimum 0.1 mm solder wetting on pin side wall. Available for wettable flank version only. PIN 1 INDEX AREA SEATING PLANE

0.1 C A B

0.05 C 0.05 C 0.1 C A B 0.05 C 0.05 C 0.05 C 0.05 C SCALE 4.500 40.000 OPTIONAL: SIDE WALL PIN DETAIL NOTE 3 AB C

www.ti.com EXAMPLE BOARD LAYOUT .000 PKG 0 .000 PKG 0

0.05 MAX

0.05 MIN

( ) 0.723 ( ) 1.448 ( ) 0.723 ( ) 1.448 4X ( ) 1.95 4X ( ) 1.95 2X ( ) 1.45 2X ( ) 0.85 2X ( ) 0.225 2X ( ) 0.275 2X ( ) 0.95 5X ( ) 1.45 2X (0.5) 2X (0.85) ( ) 1.463 ( ) 1.463 ( ) 1.625 2X (0.275) 6X (0.25) 2X (0.65) (0.3) 2X (0.655) 2X (0.305) ( ) 1.125 6X (0.65) (2.224) (0.3) (R0.05) TYP WQFN-HR - 0.8 mm max heightRBM0011A PLASTIC QUAD FLATPACK - NO LEAD 4231496/D 03/2026 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 25X 3 4 1011 METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED SOLDER MASK DETAILS METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN .000 PKG 0 .000 PKG 0 2X ( ) 1.45 2X ( ) 0.85 2X ( ) 0.225 2X ( ) 0.275 2X ( ) 0.95 5X ( ) 1.45 ( ) 1.125 ( ) 0.944 ( ) 0.268 4X ( ) 1.95 ( ) 1.625 ( ) 1.448 ( ) 0.723 ( ) 0.723 ( ) 1.448 ( ) 1.625 4X ( ) 1.95 ( ) 1.463 ( ) 1.463 2X (0.5) 2X (0.85) 2X (0.625) 2X (0.275) 6X (0.25) (0.3) 2X (0.65) 2X (0.655) 2X (0.3)2X (1.012) WQFN-HR - 0.8 mm max heightRBM0011A PLASTIC QUAD FLATPACK - NO LEAD 4231496/D 03/2026 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 25X 3 4 1011

www.ti.com PACKAGE OUTLINE 2.1 1.9 2.6 2.4 .000 PKG 0 .000 PKG 0 6X 0.3 0.2 2X 0.395 0.295 2X 0.35 0.25 2X 0.25 0.15 0.5 0.4 4X 0.55 0.35 0.8 0.7 0.05 0.00 2X 0.725 2X 0.075 2X 0.7 0.9275 0.9275 1 0.525 0.525 0.35 0.25 2X ( ) 0.042 2X (0.125) (0.15) TYP (0.152) TYP (0.4) WQFN-HR - 0.8 mm max heightRAK0009A PLASTIC QUAD FLATPACK - NO LEAD 4229353/J 04/2025 0.08 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Minimum 0.1 mm solder wetting on pin side wall. Available for wettable flank version only. PIN 1 INDEX AREA SEATING PLANE 0.05 C 0.05 C 0.05 C 0.05 C PIN 1 ID (45 X 0.1) 9 8 SCALE 5.000 OPTIONAL: SIDE WALL PIN DETAIL NOTE 4 AB C

www.ti.com EXAMPLE BOARD LAYOUT .000 PKG 0 .000 PKG 0 ALL AROUND 0.05 MIN ALL AROUND (0.45) ( ) 0.9275 ( ) 1.125 ( ) 1.125 ( ) 0.9275 3X ( ) 1.45 3X ( ) 1.45 ( ) 1 ( ) 0.525 ( ) 0.525 ( ) 1 3X ( ) 1.2 2X ( ) 0.725 2X ( ) 0.075 2X ( ) 0.7 5X ( ) 1.2 ( ) 0.875 4X (0.65) 4X (0.25) 2X (0.3) 2X (0.2) 2X (0.25) 2X (0.345) 2X ( ) 0.051 2X ( ) 0.041 ( ) 0.7 ( ) 0.7 ( 0.2) TYP VIA (0.3) WQFN-HR - 0.8 mm max heightRAK0009A PLASTIC QUAD FLATPACK - NO LEAD 4229353/J 04/2025 NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 30X METAL UNDER SOLDER MASK SOLDER MASK OPENING METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN .000 PKG 0 .000 PKG 0 ( ) 1.125 ( ) 0.9275 ( ) 0.9275 ( ) 1.125 3X ( ) 1.45 3X ( ) 1.45 ( ) 1 ( ) 0.525 ( ) 0.525 ( ) 1 2X ( ) 0.075 2X ( ) 0.745 2X ( ) 0.7 3X ( ) 1.2 5X ( ) 1.2 ( ) 0.875 ( ) 0.65 ( ) 0.65 2X (0.21) 2X (0.345) 4X (0.25) 2X (0.3) 2X (0.2) 4X (0.65) 2X (0.3) (1.1) (1.1) (0.41) WQFN-HR - 0.8 mm max heightRAK0009A PLASTIC QUAD FLATPACK - NO LEAD 4229353/J 04/2025 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 30X PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE PADS: 1 & 3: 91% PAD 2: 84% METAL UNDER SOLDER MASK SOLDER MASK OPENING

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated Last updated 10/2025