LMR23610AQDDARQ1.A

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LMR23610-Q1 SIMPLE SWITCHER® 36 V, 1 A Synchronous Step-Down Converter REVISED APRIL 2017

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IOUT (A) Efficiency (%) 0.0001 0.001 0.01 0.1 1 100 D000 VOUT = 5 V VOUT = 3.3 V BOOT SW LC BOOT FB VIN VIN up to 36 V PGND C OUT EN/SYNC C IN VCC AGND VOUT C VCC R FBT R FBB Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMR23610-Q1 SNVSAR4A –DECEMBER 2016–REVISED APRIL 2017 LMR23610-Q1SIMPLESWITCHER®36V,1ASynchronousStep-DownConverter

1 Features

1• Qualified for Automotive Applications

AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40 °C to 125 °C Ambient Operating Temperature Range - Device HBM ESD Classification Level H1C - Device CDM ESD Classification Level C4A
4 V to 36 V Input Range
1 A Continuous Output Current
Integrated Synchronous Rectification
Current Mode Control
Minimum Switch-On Time: 60 ns
Internal Compensation for Ease of Use
400 kHz Switching Frequency With PFM Mode
Frequency Synchronization to External Clock
75 µA Quiescent Current at No Load
Soft-Start into a Pre-Biased Load
High Duty Cycle Operation Supported
Output Short-Circuit Protection with Hiccup Mode
8-Pin HSOIC with PowerPAD™ Package Options
Create a Custom Design Using the LMR23610-Q1 With the WEBENCH® Power Designer

2 Applications

Automotive Battery Regulation
Industrial Power Supplies
Telecom and Datacom Systems
General Purpose Wide Vin Regulation space

3 Description

The LMR23610-Q1 SIMPLE SWITCHER® is an easy to use 36 V, 1 A synchronous step down regulator. With a wide input range from 4 V to 36 V, it is suitable for various applications from industrial to automotive for power conditioning from unregulated sources. Peak current mode control is employed to achieve simple control loop compensation and cycle- by-cycle current limiting. A quiescent current of 75 µA makes it suitable for battery powered systems. Internal loop compensation means that the user is free from the tedious task of loop compensation design. This also minimizes the external components. An extended family is available in 1.5 A (LMR23615- Q1), 2.5 A (LMR23625-Q1) and 3 A (LMR23630-Q1) load current options in pin-to-pin compatible packages which allows simple, optimum PCB layout. A precision enable input allows simplification of regulator control and system power sequencing. Protection features include cycle-by-cycle current limit, hiccup mode short circuit protection and thermal shutdown due to excessive power dissipation. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMR23610AQDDARQ1 HSOIC (8) 4.9 mm x 3.9 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Efficiency vs Load, VIN = 12 V

11.2 Receiving Notification of Documentation Updates 27

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (December 2016) to Revision A Page

(9) 4 5 LMR23610-Q1 www.ti.com SNVSAR4A –DECEMBER 2016–REVISED APRIL 2017 Product Folder Links: LMR23610-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) A = Analog, P = Power, G = Ground

5 Pin Configuration and Functions

I/O (1) DESCRIPTION NAME NO. SW 1 P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power inductor. BOOT 2 P Boot-strap capacitor connection for high-side driver. Connect a high quality 100 nF capacitor from BOOT to SW. VCC 3 P Internal bias supply output for bypassing. Connect a 2.2 μF/ 16 V or higher capacitance bypass capacitor from this pin to AGND. Do not connect external loading to this pin. Never short this pin to ground during operation. FB 4 A Feedback input to regulator, connect the feedback resistor divider tap to this pin. EN/SYNC 5 A Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float. Adjust the input under voltage lockout with two resistors. The internal oscillator can be synchronized to an external clock by coupling a positive pulse into this pin through a small coupling capacitor. See Enable/Sync for detail. AGND 6 G Analog ground pin. Ground reference for internal references and logic. Connect to system ground. VIN 7 P Input supply voltage. PGND 8 G Power ground pin, connected internally to the low side power FET. Connect to system ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible. PAD 9 G Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die. Must be used for heat sinking to ground plane on PCB.

SNVSAR4A –DECEMBER 2016–REVISED APRIL 2017 www.ti.com Product Folder Links: LMR23610-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) In shutdown mode, the VCC to AGND maximum value is 5.25 V.

6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted) (1) PARAMETER MIN MAX UNIT Input Voltages VIN to PGND -0.3 42 V EN/SYNC to AGND -5.5 VIN + 0.3 FB to AGND -0.3 4.5 AGND to PGND -0.3 0.3 Output Voltages SW to PGND -1 VIN + 0.3 V SW to PGND less than 10 ns transients -5 42 BOOT to SW -0.3 5.5 VCC to AGND -0.3 4.5 (2) TJ Junction temperature -40 150 °C Tstg Storage temperature -65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM) (1) ±2000 V Charged-device model (CDM) ±1000 (1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics.

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted) (1) MIN MAX UNIT Input Voltage VIN 4 36 VEN/SYNC -5 36 FB -0.3 1.2 Output Voltage VOUT 1 28 V Output Current IOUT 0 1 A Temperature Operating junction temperature, TJ -40 125 °C

www.ti.com SNVSAR4A –DECEMBER 2016–REVISED APRIL 2017 Product Folder Links: LMR23610-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Power rating at a specific ambient temperature TA should be determined with a maximum junction temperature (TJ) of 125 °C, which is illustrated in Recommended Operating Conditions section.

6.4 Thermal Information

THERMAL METRIC (1) (2) DDA (8 PINS) UNIT RθJA Junction-to-ambient thermal resistance 42.0 °C/W ψJT Junction-to-top characterization parameter 5.9 ψJB Junction-to-board characterization parameter 23.4 RθJC(top) Junction-to-case (top) thermal resistance 45.8 RθJC(bot) Junction-to-case (bottom) thermal resistance 3.6 RθJB Junction-to-board thermal resistance 23.4

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of -40 °C to +125 °C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY (VIN PIN) VIN Operation input voltage 4 36 V VIN_UVLO Under voltage lockout thresholds Rising threshold 3.3 3.7 3.9 V Falling threshold 2.9 3.3 3.5 ISHDN Shutdown supply current VEN = 0 V, VIN = 12 V, TJ = -40 °C to 125 2.0 4.0 μA IQ Operating quiescent current (non- switching) VIN =12 V, VFB = 1.1 V, TJ = -40 °C to 125 °C, PFM mode 75 μA ENABLE (EN PIN) VEN_H Enable rising threshold Voltage 1.4 1.55 1.7 V VEN_HYS Enable hysteresis voltage 0.4 V VWAKE Wake-up threshold 0.4 V IEN Input leakage current at EN pin VIN = 4 V to 36 V, VEN= 2 V 10 100 nA VIN = 4 V to 36 V, VEN= 36 V 1 μA VOLTAGE REFERENCE (FB PIN) VREF Reference voltage VIN = 4 V to 36 V, TJ = 25 °C 0.985 1.0 1.015 V VIN = 4 V to 36 V, TJ = -40 °C to 125 °C 0.980 1.0 1.020 ILKG_FB Input leakage current at FB pin VFB= 1 V 10 nA INTERNAL LDO (VCC PIN) VCC Internal LDO output voltage 4.1 V VCC_UVLO VCC under voltage lockout thresholds Rising threshold 2.8 3.2 3.6 V Falling threshold 2.4 2.8 3.2 CURRENT LIMIT IHS_LIMIT Peak inductor current limit 1.4 2.0 2.6 A ILS_LIMIT Valley inductor current limit 1.0 1.5 2.1 A IL_ZC Zero cross current limit -0.04 A INTEGRATED MOSFETS RDS_ON_HS High-side MOSFET ON-resistance VIN = 12 V, IOUT = 1 A 185 mΩ RDS_ON_LS Low-side MOSFET ON-resistance VIN = 12 V, IOUT = 1 A 105 mΩ THERMAL SHUTDOWN TSHDN Thermal shutdown threshold 162 170 178 °C THYS Hysteresis 15 °C

6.6 Timing Characteristics

Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HICCUP MODE NOC(1) Number of cycles that LS current limit is tripped to enter Hiccup mode

64 Cycles

TOC Hiccup retry delay time 5 ms SOFT START TSS Internal soft-start time The time of internal reference to increase from 0 V to 1.0 V 1 2 3 ms

6.7 Switching Characteristics

Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted) PARAMETER MIN TYP MAX UNIT SW (SW PIN) fSW Default switching frequency 340 400 460 kHz TON_MIN Minimum turn-on time 60 90 ns TOFF_MIN(1) Minimum turn-off time 100 ns SYNC (EN/SYNC PIN) fSYNC SYNC frequency range 200 2200 kHz VSYNC Amplitude of SYNC clock AC signal (measured at SYNC pin) 2.8 5.5 V TSYNC_MIN Minimum sync clock ON and OFF time 100 ns

6.8 Typical Characteristics

Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 22 µH, COUT = 47 µF × 2, TA = 25°C. Figure 1. Efficiency vs. Load Current Figure 2. Efficiency vs. Load Current Figure 3. Efficiency vs. Load Current Figure 4. Efficiency vs. Load Current Figure 5. Load Regulation Figure 6. Line Regulation

7 Detailed Description

7.1 Overview

The LMR23610-Q1 SIMPLE SWITCHER® regulator is an easy to use synchronous step-down DC-DC converter operating from 4 V to 36 V supply voltage. It is capable of delivering up to 1 A DC load current with good thermal performance in a small solution size. An extended family is available in multiple current options from 1 A to 3 A in pin-to-pin compatible packages. The LMR23610-Q1 employs fixed frequency peak current mode control. The device enters PFM mode at light load to achieve high efficiency. The device is internally compensated, which reduces design time, and requires few external components. The LMR23610-Q1 is capable of synchronization to an external clock within the range of 200 kHz to 2.2 MHz. Additional features such as precision enable and internal soft-start provide a flexible and easy to use solution for a wide range of applications. Protection features include thermal shutdown, VIN and VCC under-voltage lockout, cycle-by-cycle current limit, and hiccup mode short-circuit protection. The family requires very few external components and has a pin-out designed for simple, optimum PCB layout.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Fixed Frequency Peak Current Mode Control

proportional to the input voltage: D = VOUT / VIN. Figure 13. SW Node and Inductor Current Waveforms in condition, the LMR23610-Q1 will operate in PFM mode to maintain high efficiency.

7.3.2 Adjustable Output Voltage

loading is desired to reduce VOUT offset in PFM operation. Lower RFBT will reduce efficiency at very light load. Less static current goes through a larger RFBT and might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise. variation of the resistor dividers affect the output voltage regulation.

Figure 14. Output Voltage Setting

7.3.3 Enable/Sync

connect the EN to VIN. This allows self-start-up of the LMR23610-Q1 when VIN is within the operation range. Figure 15. System UVLO by Enable Divider

Figure 16. Synchronize to external clock Figure 17. Synchronizing in PWM Mode Figure 18. Synchronizing in PFM Mode

7.3.4 VCC, UVLO

7.3.5 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Drop-out Conditions

ns in the LMR23610-Q1. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be off. conversion range given a selected switching frequency.

much lower supply voltage VIN. This leads to a lower effective drop-out voltage. calculated in Equation 4. With frequency foldback, VIN_MIN is lowered by decreased fSW. Figure 19. Frequency Foldback at Dropout (VOUT = 5 V, fSW = 400 kHz)

7.3.6 Internal Compensation and CFF

is designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. for optimum transient performance. Figure 20. Feedforward Capacitor for Loop Compensation

OUT _MAX LS _LIMIT SW IN V V VI I 2 f L V u u u Z _ESR OUT 1f 2 C ESR Su u P _ CFF FF FBT FBB 1f 2 C R //R Su u Z _ CFF FF FBT 1f 2 C R Su u LMR23610-Q1 www.ti.com SNVSAR4A –DECEMBER 2016–REVISED APRIL 2017 Product Folder Links: LMR23610-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated Feature Description (continued) The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the cross over frequency of the control loop to boost phase margin. The zero frequency can be found by (6) An additional pole is also introduced with CFF at the frequency of (7) The zero fZ_CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps maintaining proper gain margin at frequency beyond the crossover. Table 1 lists the combination of COUT, CFF and RFBT for typical applications, designs with similar COUT but RFBT other than recommended value, please adjust CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged. Designs with different combinations of output capacitors need different CFF. Different types of capacitors have different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF. Electrolytic capacitors have much larger ESR and the ESR zero frequency (8) would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not need any CFF. The CFF creates a time constant with RFBT that couples in the attenuate output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. Therefore, CFF should be calculated based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced.

7.3.7 Bootstrap Voltage (BOOT)

The LMR23610-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16V or higher is recommended for stable performance over temperature and voltage.

7.3.8 Over Current and Short Circuit Protection

The LMR23610-Q1 is protected from over-current conditions by cycle-by-cycle current limit on both the peak and valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over-heating. High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Please refer to Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum peak current threshold IHS_LIMIT which is constant. So the peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range. The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is above the LS current limit ILS_LIMIT. The LS switch will be kept ON so that inductor current keeps ramping down, until the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch will be turned OFF and the HS switch will be turned on after a dead time. This is somewhat different than the more typical peak current limit, and results in Equation 9 for the maximum load current. (9)

SNVSAR4A –DECEMBER 2016–REVISED APRIL 2017 www.ti.com Product Folder Links: LMR23610-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Feature Description (continued) If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup current protection mode will be activated. In hiccup mode, the regulator will be shut down and kept off for 5 ms typically before the LMR23610-Q1 tries to start again. If over-current or short-circuit fault condition still exist, hiccup will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-current conditions, prevents over-heating and potential damage to the device.

7.3.9 Thermal Shutdown

The LMR23610-Q1 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 170 °C (typ). The device is turned off when thermal shutdown activates. Once the die temperature falls below 155 °C (typ), the device reinitiates the power up sequence controlled by the internal soft-start circuitry.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LMR23610-Q1. When VEN is below 1 V (typ), the device is in shutdown mode. The LMR23610-Q1 also employs VIN and VCC under voltage lock out protection. If VIN or VCC voltage is below their respective UVLO level, the regulator will be turned off.

7.4.2 Active Mode

The LMR23610-Q1 is in Active Mode when VEN is above the precision enable threshold, VIN and VCC are above their respective UVLO level. The simplest way to enable the LMR23610-Q1 is to connect the EN pin to VIN pin. This allows self startup when the input voltage is in the operating range: 4 V to 36 V. Please refer to VCC, UVLO and Enable/Sync for details on setting these operating levels. In Active Mode, depending on the load current, the LMR23610-Q1 will be in one of three modes: 1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple. 2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation. 3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load.

7.4.3 CCM Mode

CCM operation is employed in the LMR23610-Q1 when the load current is higher than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple will be at a minimum in this mode and the maximum output current of 1 A can be supplied by the LMR23610-Q1.

7.4.4 Light Load Operation

When the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR23610-Q1 will operate in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In DCM, the LS switch is turned off when the inductor current drops to IL_ZC (-40 mA typ). Both switching losses and conduction losses are reduced in DCM, compared to forced PWM operation at light load. At even lighter current loads, Pulse Frequency Modulation (PFM) is activated to maintain high efficiency operation. When either the minimum HS switch ON time (tON_MIN ) or the minimum peak inductor current IPEAK_MIN (300 mA typ) is reached, the switching frequency will decrease to maintain regulation. In PFM, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM operation due to less frequent switching actions. The external clock synchronizing will not be valid when LMR23610-Q1 enters into PFM mode.

5 V/1 A

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

comprehensive databases of components. Please go to ti.com for more details.

8.2 Typical Applications

fixed output voltage. Figure 21 shows a basic schematic. Figure 21. Application Circuit control loop. Table 1 can be used to simplify the output filter component selection. Table 1. L, COUT and CFF Typical Values

Inductance value is calculated based on VIN = 36 V.
All the COUT values are after derating. Add more when using ceramic capacitors.
RFBT = 0 Ω for VOUT = 1 V. RFBB = 22.1 kΩ for all other VOUT setting.
For designs with RFBT other than recommended value, please adjust CFF such that (CFF × RFBT) is

unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged.

High ESR COUT will give enough phase boost and CFF not needed.

8.2.1 Design Requirements

parameters listed in Table 2 as the input parameters.

Table 2. Design Example Parameters

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR23610-Q1 device with the WEBENCH® Power Designer.

Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
Compare the generated design with other possible solutions from Texas Instruments.

pricing and component availability.

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Set-Point

RFBB value can then be calculated using Equation 10. The formula yields to a value 88.7 kΩ.

8.2.2.3 Switching Frequency

be synchronized to an external clock, please refer to Enable/Sync for more details.

8.2.2.4 Inductor Selection

inductor current can be high. The inductor current rating should be higher than the current limit of the device.

! u u OH OL OUT SW US

6 I IC f V

u ! u IND OUTL OUT _ C SW OUT SW OUT K I iV 8 f C 8 f C u'' u u u u OUT_ESR L IND OUTV i ESR K I ESR' ' u u u IN_MAX OUT OUT MIN OUT IND IN_MAX SW V V VL I K V f u u u LMR23610-Q1 SNVSAR4A –DECEMBER 2016–REVISED APRIL 2017 www.ti.com Product Folder Links: LMR23610-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (12) In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can generate too large of an inductor current ripple such that over current protection at the full load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple improves the comparator signal to noise ratio. For this design example, choose KIND = 0.5, the minimum inductor value is calculated to be 20.5 µH. Choose the nearest standard 22 μH ferrite inductor with a capability of 2 A RMS current and 2.5 A saturation current.

8.2.2.5 Output Capacitor Selection

The output capacitor(s), COUT, should be chosen with care since it directly affects the steady state output voltage ripple, loop stability and the voltage over/undershoot during load current transients. The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors: (13) The other is caused by the inductor current ripple charging and discharging the output capacitors: (14) The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks. Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The regulator’s control loop usually needs six or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for six clock cycles to maintain the output voltage within the specified range. Equation 15 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor. which results in an output voltage overshoot. Equation 16 calculates the minimum capacitance required to keep the voltage overshoot within a specified range. (15) (16) where

KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT)
IOL = Low level output current during load transient
IOH = High level output current during load transient
VUS = Target output voltage undershoot
VOS = Target output voltage overshoot For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and chose KIND = 0.5. Equation 13 yields ESR no larger than 100 mΩ and Equation 14 yields COUT no smaller than 3.1 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be calculated to be no smaller than 54 μF and 8.5 μF by Equation 15 and Equation 16 respectively. Consider of derating, one 82 μF, 16 V ceramic capacitor with 5 mΩ ESR is used.

IN_FALLING ENH EN_HYS ENB R R V V V R u IN_RISING ENT ENB ENH V R 1 R V § · u¨ ¸ ¨ ¸ © ¹ ENT ENB IN_RISING ENH ENB R R V V R u FF X FBT 1C 2 f R Su u X OUT OUT 8.32f V C u LMR23610-Q1 www.ti.com SNVSAR4A –DECEMBER 2016–REVISED APRIL 2017 Product Folder Links: LMR23610-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

8.2.2.6 Feed-Forward Capacitor

The LMR23610-Q1 is internally compensated. Depending on the VOUT and frequency fSW, if the output capacitor COUT is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover frequency (fX) without CFF is shown in Equation 17, assuming COUT has very small ESR, and COUT value is after derating. (17) The following equation for CFF was tested: (18) For designs with higher ESR, CFF is not needed when COUT has very high ESR and CFF calculated from Equation 18 should be reduced with medium ESR. Table 1 can be used as a quick starting point. For the application in this design example, a 75 pF, 50 V, COG capacitor is selected.

8.2.2.7 Input Capacitor Selection

The LMR23610-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor, depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7 μF to 10 μF. A high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating is recommended. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required, especially if the LMR23610-Q1 circuit is not located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7 μF, 50 V, X7R ceramic capacitors are used. A 0.1 μF for high-frequency filtering and place it as close as possible to the device pins.

8.2.2.8 Bootstrap Capacitor Selection

Every LMR23610-Q1 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

8.2.2.9 VCC Capacitor Selection

The VCC pin is the output of an internal LDO for LMR23610-Q1. To insure stability of the device, place a minimum of 2.2 μF, 16 V, X7R capacitor from this pin to ground.

8.2.2.10 Under Voltage Lockout Set-Point

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO level. (19) The EN rising threshold (VENH) for LMR23610-Q1 is set to be 1.55 V (typ). Choose the value of RENB to be 287 kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 6.0 V, then the value of RENT can be calculated using the equation below: (20) The above equation yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by below equation, where EN hysteresis (VEN_HYS) is 0.4 V (typ). (21)

8.2.3 Application Curves

Figure 22. CCM Mode Figure 23. PFM Mode Figure 24. Start Up by VIN Figure 25. Start Up by EN Figure 26. Load Transient Figure 27. Line Transient

9 Power Supply Recommendations

The LMR23610-Q1 is designed to operate from an input voltage supply range between 4 V and 36 V. This input supply should be able to withstand the maximum input current and maintain a stable voltage. The resistance of the input supply rail should be low enough that an input current transient does not cause a high enough drop at the LMR23610-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the LMR23610-Q1, additional bulk capacitance may be required in addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47 μF or 100 μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. 1. The input bypass capacitor CIN must be placed as close as possible to the VIN and PGND pins. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the PGND pin and PAD. 2. Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground. 3. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB should be located close to the FB pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer. 4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. 5. Have a single point ground connection to the plane. The ground connections for the feedback and enable components should be routed to the ground plane. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. 6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125 °C.

10.2 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction. The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current conduction path to minimize parasitic resistance. The output capacitors should be placed close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. The bypass capacitors on VCC should be placed as close as possible to the pin and closely grounded to PGND and the exposed PAD.

10.3 Ground Plane and Thermal Considerations

It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and PGND pins should be connected to the ground plane using vias right next to the bypass capacitors. PGND pin is connected to the source of the internal LS switch. They should be connected directly to the grounds of the input and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load variations. PGND trace, as well as VIN and SW traces, should be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and should be used for sensitive routes. It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough copper thickness provides low current conduction impedance, proper shielding and lower thermal resistance. The thermal characteristics of the LMR23610-Q1 are specified using the parameter θJA, which characterize the junction temperature of silicon to the ambient temperature in a specific system. Although the value of θJA is dependent on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PD x θJA + TA (22) where TJ = Junction temperature in °C PD = VIN x IIN x (1 - Efficiency) - 1.1 x IOUT 2 x DCR in Watt DCR = Inductor DC parasitic resistance in Ω θJA = Junction to ambient thermal resistance of the device in °C/W TA = Ambient temperature in °C The maximum operating junction temperature of the LMR23610-Q1 is 125 °C. θJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow.

10.4 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if short path is not available. If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to the feedback resistor divider should be routed away from the SW node path and the inductor to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high value resistors are used to set the output voltage. It is recommended to route the voltage sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage feedback path from EMI noises.

10.5 Layout Example

Figure 30. Layout

11 Device and Documentation Support

11.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR23610-Q1 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments. WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMR23610AQDDAQ1 Active Production SO PowerPAD (DDA) | 8 75 | TUBE Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F10AQ LMR23610AQDDAQ1.A Active Production SO PowerPAD (DDA) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 F10AQ LMR23610AQDDAQ1.B Active Production SO PowerPAD (DDA) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 F10AQ LMR23610AQDDARQ1 Active Production SO PowerPAD (DDA) | 8 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F10AQ LMR23610AQDDARQ1.A Active Production SO PowerPAD (DDA) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 F10AQ LMR23610AQDDARQ1.B Active Production SO PowerPAD (DDA) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 F10AQ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 10-Nov-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMR23610-Q1 :

Catalog : LMR23610 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LMR23610AQDDARQ1 SO PowerPAD Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR23610AQDDARQ1 SO PowerPAD DDA 8 2500 366.0 364.0 50.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LMR23610AQDDAQ1 DDA HSOIC 8 75 507 8 3940 4.32 LMR23610AQDDAQ1 DDA HSOIC 8 75 517 7.87 635 4.25 LMR23610AQDDAQ1.A DDA HSOIC 8 75 517 7.87 635 4.25 LMR23610AQDDAQ1.A DDA HSOIC 8 75 507 8 3940 4.32 LMR23610AQDDAQ1.B DDA HSOIC 8 75 507 8 3940 4.32 LMR23610AQDDAQ1.B DDA HSOIC 8 75 517 7.87 635 4.25 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 6.2

5.8 TYP

1.7 MAX

6X 1.27 8X 0.51 0.31 3.81 0.25

0.10 TYP

0.15 0.00 2.71 2.11 3.4 2.8 4X (0 -10 ) 0.25 GAGE PLANE 1.27 0.40 A 5.0 4.8 NOTE 3 B 4.0 3.8 4214849/B 09/2025 PowerPAD SOIC - 1.7 mm max heightDDA0008B PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MS-012. PowerPAD is a trademark of Texas Instruments. TM 1 8

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.400 EXPOSED THERMAL PAD

www.ti.com EXAMPLE BOARD LAYOUT (5.4) (1.3) TYP ( 0.2) TYP VIA (R0.05) TYP

0.07 MAX

0.07 MIN

8X (1.55) 8X (0.6) 6X (1.27) (2.95) NOTE 9 (4.9) NOTE 9 (2.71) (3.4) SOLDER MASK OPENING(1.3) TYP 4214849/B 09/2025 PowerPAD SOIC - 1.7 mm max heightDDA0008B PLASTIC SMALL OUTLINE SYMM SYMM SEE DETAILS LAND PATTERN EXAMPLE SCALE:10X 4 5 SOLDER MASK OPENING METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. TM METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS PADS 1-8 OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP8X (1.55) 8X (0.6) 6X (1.27) (5.4) (2.71) (3.4) BASED ON

0.125 THICK

PowerPAD SOIC - 1.7 mm max heightDDA0008B PLASTIC SMALL OUTLINE 2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X SYMM SYMM 4 5 BASED ON

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Product Information

LMR23610AQDDARQ1.A specifications and overview.

Summary

LMR23610-Q1 SIMPLE SWITCHER® 36 V, 1 A Synchronous Step-Down Converter REVISED APRIL 2017

Description

LMR23610-Q1 SIMPLE SWITCHER® 36 V, 1 A Synchronous Step-Down Converter REVISED APRIL 2017

Source title LMR23610AQDDARQ1.A Datasheet(PDF) - Texas Instruments

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