LMR10520XSDX/NOPB

LMR10520 TI | Alldatasheet

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Technical content

Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMR10520 SNVS730C –OCTOBER 2011–REVISED JUNE 2019 LMR105205.5-VIN,2-AStep-DownVoltageRegulatorinWSON

1 Features

1• Input Voltage Range of 3 V to 5.5 V

Output Voltage Range of 0.6 V to 4.5 V
Output Current up to 2 A
1.6-MHz (LMR10520X) and 3-MHz (LMR10520Y) Switching Frequencies
Low Shutdown IQ, 30 nA Typical
Internal Soft Start
Internally Compensated
Current-Mode PWM Operation
Thermal Shutdown
Tiny Overall Solution Reduces System Cost
WSON (3 × 3 × 0.8 mm) Packaging
Create a custom design using the LMR10520 with the WEBENCH® Power Designer

2 Applications

Point-of-Load Conversions from 3.3-V and 5-V Rails
Space-Constrained Applications
Battery-Powered Equipment
Industrial Distributed Power Applications
Power Meters
Portable Hand-Held Instruments

3 Description

The LMR10520 regulator is a monolithic, high frequency, PWM step-down DC/DC converter in a 6- pin WSON package. It provides all the active functions to provide local DC/DC conversion with fast transient response and accurate regulation in the smallest possible PCB area. With a minimum of external components, the LMR10520 is easy to use. The ability to drive 2-A loads with an internal 150-mΩ PMOS switch results in the best power density available. The world-class control circuitry allows on- times as low as 30 ns, thus supporting exceptionally high frequency conversion over the entire 3-V to 5.5- V input operating range down to the minimum output voltage of 0.6 V. The LMR10520 is internally compensated, so it is simple to use and requires few external components. Even though the operating frequency is high, efficiencies up to 93% are easy to achieve. External shutdown is included, featuring an ultra-low stand-by current of 30 nA. The LMR10520 uses current-mode control and internal compensation to provide high-performance regulation over a wide range of operating conditions. Additional features include internal soft-start circuitry to reduce inrush current, pulse-by-pulse current limit, thermal shutdown, and output overvoltage protection. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMR10520 WSON (6) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application

10.2 Receiving Notification of Documentation Updates 22

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2013) to Revision C Page Changes from Revision A (April 2013) to Revision B Page

5 Pin Configuration and Functions

DESCRIPTION

NO. NAME 1 FB Feedback pin. Connect to external resistor divider to set output voltage. 2 GND Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin. 3 SW Switch node. Connect to the inductor and catch diode. 4 VIND Power input supply. 5 VINA Control circuitry supply voltage. Connect VINA to VIND on PC board. 6 EN Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VINA + 0.3 V. DAP Die Attach Pad Connect to system ground for low thermal impedance, but it cannot be used as a primary GND connection.

SNVS730C –OCTOBER 2011–REVISED JUNE 2019 www.ti.com Product Folder Links: LMR10520 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (2) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions, see Electrical Characteristics. (3) Thermal shutdown occurs if the junction temperature exceeds the maximum junction temperature of the device.

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2). VIN -0.5V to 7V FB Voltage -0.5V to 3V EN Voltage -0.5V to 7V SW Voltage -0.5V to 7V ESD Susceptibility 2kV Junction Temperature(3) 150°C Storage Temperature −65°C to +150°C Soldering Information For soldering specifications: http://www.ti.com/lit/SNOA549

6.2 Recommended Operating Ratings

VIN 3V to 5.5V Junction Temperature −40°C to +125°C

www.ti.com SNVS730C –OCTOBER 2011–REVISED JUNE 2019 Product Folder Links: LMR10520 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated (1) Minimum and Maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). (2) Typical numbers are at 25°C and represent the most likely parametric norm. (3) Applies for packages soldered directly onto a 3”× 3”PC board with 2 oz. copper on 4 layers in still air.

6.3 Electrical Characteristics

VIN = 5 V unless otherwise indicated under the TEST CONDITIONS column. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VFB Feedback Voltage 0.588 0.600 0.612 V ΔVFB/VIN Feedback Voltage Line Regulation VIN = 3V to 5V 0.02 %/V IB Feedback Input Bias Current 0.1 100 nA UVLO Undervoltage Lockout VIN Rising 2.73 2.90 V VIN Falling 1.85 2.3 UVLO Hysteresis 0.43 V FSW Switching Frequency LMR10520-X 1.2 1.6 1.95 MHz LMR10520-Y 2.25 3.0 3.75 DMAX Maximum Duty Cycle LMR10520-X 86% 94% LMR10520-Y 82% 90% DMIN Minimum Duty Cycle LMR10520-X 5% LMR10520-Y 7% RDS(ON) Switch On Resistance 150 mΩ ICL Switch Current Limit VIN = 3.3V 2.4 3.25 A VEN_TH Shutdown Threshold Voltage 0.4 V Enable Threshold Voltage 1.8 ISW Switch Leakage 100 nA IEN Enable Pin Current Sink/Source 100 nA IQ Quiescent Current (switching) LMR10520X VFB = 0.55 3.3 5 mA LMR10520Y VFB = 0.55 4.3 6.5 Quiescent Current (shutdown) All Options VEN = 0V 30 nA θJA Junction to Ambient

0 LFPM Air Flow(3)

80 °C/W θJC Junction to Case 18 °C/W TSD Thermal Shutdown Temperature 165 °C

6.4 Typical Characteristics

Unless stated otherwise, all curves taken at VIN = 5 V with configuration in typical application circuit shown in Figure 14. TJ = 25°C, unless otherwise specified. Figure 1. Efficiency vs Load "X" Figure 2. Efficiency vs Load "Y" Figure 3. Efficiency vs Load "X" and "Y" Figure 4. Oscillator Frequency vs Temperature - "X" Figure 5. Oscillator Frequency vs Temperature - "Y" Figure 6. Current Limit vs Temperature

7 Detailed Description

7.1 Overview

Figure 13. The LMR10520 supplies a regulated output voltage by switching the internal PMOS control switch at adjusts the duty cycle (D) to maintain a constant output voltage. Figure 13. Typical Waveforms

S R R Q GND FB SW VINEN DRIVER ArtificialRamp SHDNThermal SHDNOVP

1.6 MHz

15 . 1 xREFV Control Logic VREF = 0.6V LMR10520 www.ti.com SNVS730C –OCTOBER 2011–REVISED JUNE 2019 Product Folder Links: LMR10520 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Soft-Start

This function forces VOUT to increase at a controlled rate during start-up. During soft start, the error amplifier’s reference voltage ramps from 0 V to its nominal value of 0.6 V in approximately 600 µs. This forces the regulator output to ramp up in a controlled fashion, which helps reduce inrush current.

7.3.2 Output Overvoltage Protection

The overvoltage comparator compares the FB pin voltage to a voltage that is 15% higher than the internal reference VREF. Once the FB pin voltage goes 15% above the internal reference, the internal PMOS control switch is turned off, which allows the output voltage to decrease toward regulation.

7.3.3 Undervoltage Lockout

Undervoltage lockout (UVLO) prevents the LMR10520 from operating until the input voltage exceeds 2.73 V (typical). The UVLO threshold has approximately 430 mV of hysteresis, so the part will operate until VIN drops below 2.3 V (typical). Hysteresis prevents the part from turning off during power-up if VIN is non-monotonic.

7.3.4 Current Limit

The LMR10520 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a current limit comparator detects if the output switch current exceeds 2.5 A (typical), and turns off the switch until the next switching cycle begins.

7.3.5 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature exceeds 165°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature drops to approximately 150°C.

2.2 PF 22 PF 22 nF

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.2 Typical Application

Figure 14. Typical Application Schematic

8.2.1 Detailed Design Procedure

8.2.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR10520 device with the WEBENCH® Power Designer.

Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
Compare the generated design with other possible solutions from Texas Instruments.

pricing and component availability.

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2 Inductor Selection

VD, the higher the operating efficiency of the converter. The inductor value determines the output ripple current. inductor value will decrease the output ripple current. Figure 15. Inductor Current be safe enough. The typical current limit is 3.25 A. transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple.

'VOUT = 'IL R ESR +8 x FSW x COUT IRMS_IN = IOUT x D(1 - D) IRMS_IN D IOUT 2 (1-D) +'i2 LMR10520 www.ti.com SNVS730C –OCTOBER 2011–REVISED JUNE 2019 Product Folder Links: LMR10520 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated Typical Application (continued) When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating. Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating correctly. Because of the speed of the internal current limit, the peak current of the inductor need only be specified for the required maximum output current. For example, if the designed maximum output current is 1 A, and the peak current is 1.25 A, then the inductor should be specified with a saturation current limit of > 1.25 A. There is no need to specify the saturation or peak current of the inductor at the 3.25 A typical switch current limit. The difference in inductor size is a factor of 5. Because of the operating frequency of the LMR10520, ferrite based inductors are preferred to minimize core losses. This presents little restriction since the variety of ferrite- based inductors is huge. Lastly, inductors with lower series resistance (RDCR) will provide better operating efficiency. For recommended inductors, see Other System Examples.

8.2.1.3 Input Capacitor

An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The primary specifications of the input capacitor are capacitance, voltage, RMS current rating, and equivalent series inductance (ESL). The recommended input capacitance is 22 µF. The input voltage rating is specifically stated by the capacitor manufacturer. Make sure to check any recommended deratings and also verify if there is any significant change in capacitance at the operating input voltage and the operating temperature. The input capacitor maximum RMS input current rating (IRMS-IN) must be greater than: (8) Neglecting inductor ripple simplifies the above equation to: (9) It can be shown from the above equation that maximum RMS capacitor current occurs when D = 0.5. Always calculate the RMS at the point where the duty cycle D is closest to 0.5. The ESL of an input capacitor is usually determined by the effective cross sectional area of the current path. A large leaded capacitor will have high ESL and a 0805 ceramic chip capacitor will have very low ESL. At the operating frequencies of the LMR10520, leaded capacitors may have an ESL so large that the resulting impedance (2πfL) will be higher than that required to provide stable operation. As a result, surface mount capacitors are strongly recommended. Sanyo POSCAP, Tantalum or Niobium, Panasonic SP, and multilayer ceramic capacitors (MLCC) are all good choices for both input and output capacitors and have very low ESL. For MLCCs it is recommended to use X7R or X5R type capacitors due to their tolerance and temperature characteristics. Consult capacitor manufacturer datasheets to see how rated capacitance varies over operating conditions.

8.2.1.4 Output Capacitor

The output capacitor is selected based upon the desired output ripple and transient response. The initial current of a load transient is provided mainly by the output capacitor. The output ripple of the converter is: (10) When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the output ripple will be approximately sinusoidal and 90° phase shifted from the switching action. Given the availability and quality of MLCCs and the expected output voltage of designs using the LMR10520, there is really no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not. Since the output capacitor is one of the two external components that control the stability of the regulator control loop, most applications will require a minimum of 22 µF of output capacitance. Capacitance often, but not always, can be increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended multilayer ceramic capacitors are X7R or X5R types.

D = VOUT + VD + VDCR VIN + VD + VDCR - VSW D = VOUT + VD VIN + VD - VSW K = POUT POUT + PLOSS K = POUT PIN x R2R1 = VREF VOUT - 1 LMR10520 SNVS730C –OCTOBER 2011–REVISED JUNE 2019 www.ti.com Product Folder Links: LMR10520 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Typical Application (continued)

8.2.1.5 Catch Diode

The catch diode (D1) conducts during the switch off-time. A Schottky diode is recommended for its fast switching times and low forward voltage drop. The catch diode should be chosen so that its current rating is greater than: ID1 = IOUT x (1-D) (11) The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin. To improve efficiency, choose a Schottky diode with a low forward voltage drop.

8.2.1.6 Output Voltage

The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and R1 is connected between VO and the FB pin. A good value for R2 is 10kΩ. When designing a unity gain converter (Vo = 0.6V), R1 should be between 0Ω and 100Ω, and R2 should be equal or greater than 10kΩ. (12) VREF = 0.60V (13)

8.2.1.7 Calculating Efficiency and Junction Temperature

The complete LMR10520 DC/DC converter efficiency can be calculated in the following manner. (14) Or (15) Calculations for determining the most significant power losses are shown below. Other losses totaling less than 2% are not discussed. Power loss (PLOSS) is the sum of two basic types of losses in the converter: switching and conduction. Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D): (16) VSW is the voltage drop across the internal PFET when it is on, and is equal to: VSW = IOUT x RDSON (17) VD is the forward voltage drop across the Schottky catch diode. It can be obtained from the diode manufactures Electrical Characteristics section. If the voltage drop across the inductor (VDCR) is accounted for, the equation becomes: (18) The conduction losses in the free-wheeling Schottky diode are calculated as follows: PDIODE = VD x IOUT x (1-D) (19) Often this is the single most significant power loss in the circuit. Care should be taken to choose a Schottky diode that has a low forward voltage drop.

is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node. IQ is the quiescent operating current, and is typically around 3.3 mA for the 1.6-MHz frequency option. Table 1. Power Loss Tabulation

8.2.2 Application Curves

Figure 16. Load Regulation Figure 17. Load Regulation Figure 18. Load Regulation Figure 19. Line Regulation

8.2.3 Other System Examples

8.2.3.1 LMR10520X Design Example 1

Figure 20. LMR10520x (1.6 MHz): VIN = 5 V, VOUT = 1.2 V at 2 A

8.2.3.2 LMR10510X Design Example 2

Figure 21. LMR10520X (1.6 MHz): VIN = 5 V, VOUT = 3.3 V at 2 A

8.2.3.3 LMR10510Y Design Example 3

Figure 22. LMR10520Y (3 MHz): VIN = 5 V, VOUT = 3.3 V at 2 A

8.2.3.4 LMR10510Y Design Example 4

Figure 23. LMR10520Y (3 MHz): VIN = 5 V, VOUT = 1.2 V at 2 A

9 Layout

9.1 Layout Guidelines

9.2 Layout Example

Figure 24. 6-Lead WSON PCB Dog-Bone Layout

R TJC= TJ - TC Power R TJA= TJ - TA Power R T= 'T Power LMR10520 SNVS730C –OCTOBER 2011–REVISED JUNE 2019 www.ti.com Product Folder Links: LMR10520 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated

9.3 Thermal Definitions

TJ = Chip junction temperature TA = Ambient temperature RθJC = Thermal resistance from chip junction to device case RθJA = Thermal resistance from chip junction to ambient air Heat in the LMR10520 due to internal power dissipation is removed through conduction and/or convection. Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs. conductor). Heat Transfer goes as: Silicon → package → lead frame → PCB Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural convection occurs when air currents rise from the hot device to cooler air. Thermal impedance is defined as: (30) Thermal impedance from the silicon junction to the ambient air is defined as: (31) The PCB size, weight of copper used to route traces and ground plane, and number of layers within the PCB can greatly effect RθJA. The type and number of thermal vias can also make a large difference in the thermal impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to the ground plane. Four to six thermal vias should be placed under the exposed pad to the ground plane. Thermal impedance also depends on the thermal properties of the application operating conditions (Vin, Vo, Io etc), and the surrounding circuitry. Silicon Junction Temperature Determination Method 1: To accurately measure the silicon temperature for a given application, two methods can be used. The first method requires the user to know the thermal impedance of the silicon junction to case temperature. RθJC is approximately 18°C/Watt for the 6-pin WSON package with the exposed pad. Knowing the internal dissipation from the efficiency calculation given previously, and the case temperature, which can be empirically measured on the bench we have: where

TC is the temperature of the exposed pad and can be measured on the bottom side of the PCB. (32) Therefore: Tj = (RθJC x PLOSS) + TC (33) From the previous example: Tj = (RθJC x PINTERNAL) + TC (34) Tj = 18°C/W x 0.213W + TC (35) The second method can give a very accurate silicon junction temperature.

The first step is to determine RθJA of the application. The LMR10520 has over-temperature protection circuitry. An example of calculating RθJA for an application using the LMR10520 is shown below. that temperature, the device went into thermal shutdown.

9.4 WSON Package

increasing the size of ground plane, and adding thermal vias, the RθJA for the application can be reduced. Figure 25. Internal WSON Connection

10 Device and Documentation Support

10.1 Device Support

10.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.1.2 Development Support

10.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR10520 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

10.4 Trademarks

E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMR10520XSD/NOPB Active Production WSON (NGG) | 6 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 125 L266B LMR10520XSD/NOPB.A Active Production WSON (NGG) | 6 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 125 L266B LMR10520XSDE/NOPB Active Production WSON (NGG) | 6 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 125 L266B LMR10520XSDE/NOPB.A Active Production WSON (NGG) | 6 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 125 L266B LMR10520XSDX/NOPB Active Production WSON (NGG) | 6 4500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 L266B LMR10520XSDX/NOPB.A Active Production WSON (NGG) | 6 4500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 L266B LMR10520YSD/NOPB Active Production WSON (NGG) | 6 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 125 L267B LMR10520YSD/NOPB.A Active Production WSON (NGG) | 6 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 125 L267B LMR10520YSDE/NOPB Active Production WSON (NGG) | 6 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 125 L267B LMR10520YSDE/NOPB.A Active Production WSON (NGG) | 6 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 125 L267B LMR10520YSDX/NOPB Active Production WSON (NGG) | 6 4500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 L267B LMR10520YSDX/NOPB.A Active Production WSON (NGG) | 6 4500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 L267B (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR10520XSD/NOPB WSON NGG 6 1000 208.0 191.0 35.0 LMR10520XSDE/NOPB WSON NGG 6 250 208.0 191.0 35.0 LMR10520XSDX/NOPB WSON NGG 6 4500 356.0 356.0 36.0 LMR10520YSD/NOPB WSON NGG 6 1000 208.0 191.0 35.0 LMR10520YSDE/NOPB WSON NGG 6 250 208.0 191.0 35.0 LMR10520YSDX/NOPB WSON NGG 6 4500 356.0 356.0 36.0 Pack Materials-Page 2

www.ti.com SDE06A (Rev A)

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Summary

LMR10520 5.5-VIN, 2-A Step-Down Voltage Regulator in WSON REVISED JUNE 2019

Description