LM5160-Q1 TI1 | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community LM5160-Q1 SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015 LM5160-Q1WideInput65-V,1.5-ASynchronousBuck/ Fly-Buck™ Converter
1 Features 3 Description
The LM5160 family is a 65-V, 1.5-A synchronous 1• AEC-Q100 Grade 1 Qualified with the following step-down converter with integrated high-side andresults: low-side MOSFETs. The constant-on-time control– Device Temperature Grade 1: -40°C to 125°C scheme requires no loop compensation and supports Ambient Operating Temperature Range high step-down ratios with fast transient response. An internal feedback amplifier maintains ±1% output• Wide 4.5-V to 65-V Input Voltage Range voltage regulation over the entire operating• Integrated High and Low Side Switches temperature range. The on-time varies inversely with– No Schottky Diode Required input voltage resulting in nearly constant switching
- 1.5-A Maximum Load Current frequency. Peak and valley current limit circuits protect against overload conditions. The under-• Constant On-Time Control voltage lockout (EN/UVLO) circuit provides– No External Loop Compensation independently adjustable input under-voltage – Fast Transient Response threshold and hysteresis. The LM5160 is programmed through the FPWM pin to operate in• Selectable Forced CCM or DCM Operation continuous conduction mode (CCM) from no load to• CCM Option Supports Multi-Output Fly-Buck full load or to automatically switch to discontinuous• Nearly Constant Switching Frequency conduction mode (DCM) at light load for higher efficiency. Forced CCM operation supports multiple• Frequency Adjustable up to 1 MHz output and isolated Fly-Buck applications using a• Programmable Soft-Start Time coupled inductor.• Pre-Biased Startup
- Peak Current Limiting Protection Device Information(1)
- Adjustable Input UVLO and Hysteresis PART NUMBER PACKAGE BODY SIZE (NOM) LM5160-Q1 HTSSOP (14) PWP 4.4 mm x 5.0 mm• ±1% Feedback Voltage Reference
- Thermal Shutdown Protection (1) For all available packages, see the orderable addendum at the end of the datasheet.
2 Applications
- Industrial Programmable Logic Controller
- IGBT Gate Drive Bias Supply
- Telecom Primary/Secondary Side Bias
- E-meter Power Line Communication
- Low Power Isolated DC-DC (Fly-Buck)
- Automotive Electronics Typical Fly-Buck Application CircuitTypical Sync-Buck Application Circuit An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015 www.ti.com Table of Contents
4 Revision History
Changes from Original (July 2015) to Revision A Page
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5 Pin Configuration and Functions
DESCRIPTION
AGND 1 1 Analog Ground. Ground connection of internal control circuits. PGND 2 2 Power Ground. Ground connection of the internal synchronous rectifier FET. VIN 3 3 Input supply connection. Operating input range is 4.5 V to 65 V. EN/UVLO 4 4 Precision enable. Input pin of under-voltage lockout (UVLO) comparator. On-time programming pin. A resistor between this pin and VIN sets the switch on-time as aRON 5 5 function of input voltage. SS 6 6 Soft-start. Connect a capacitor from SS to AGND to control output rise time and limit overshoot. Forced PWM logic input pin. Connect to AGND for discontinuous conduction mode (DCM) with FPWM 8 7 light loads. Connect to VCC for continuous conduction mode (CCM) at all loads and Fly-Buck configuration. FB 9 8 Feedback input of voltage regulation comparator. VCC 10 9 Internal high voltage startup regulator bypass capacitor pin. Bootstrap capacitor pin. Connect a capacitor between BST and SW to bias gate driver of highBST 11 10 side buck FET. Switch node. Source connection of high side buck FET and drain connection of low sideSW 12,13 11,12 synchronous rectifier FET. NC 7,14 - No Connection. Exposed Pad. Connect to AGND and printed circuit board ground plane to improve powerEP dissipation. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5160-Q1
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6 Specifications
6.1 Absolute Maximum Ratings
Input Voltage VIN to AGND –0.3 70 EN/UVLO to AGND –0.3 70 RON to AGND -0.3 70 BST to AGND -0.3 84 V VCC to AGND -0.3 14 FPWM to AGND -0.3 14 SS to AGND -0.3 7 FB to AGND -0.3 7 Output Voltage BST to SW -0.3 14 BST to VCC 70 V SW to AGND –1.5 70 SW to AGND (20 ns transient) –3 Lead Temperature(4) 200 Maximum Junction Temperature(3) –40 150 Storage temperature range TSTG –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C. (4) For detailed information on soldering plastic SO PowerPAD package, refer to the SNOA549 available from Texas Instruments. Maximum solder time not to exceed 4 seconds.
6.2 ESD Ratings: LM5160-Q1
Human body model (HBM), per AEC Q100-002(1) ±2000 V V(ESD) Charged device model (CDM), per AEC Q100-011 ±750 V (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions(1)
Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input Voltage 4.5 65 V IO Output Current 1.5 A Operating Junction Temperature(2) (LM5160-Q1 only) -40 150 °C (1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics (2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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6.4 Thermal Information(1)
LM5160, LM5160-Q1 THERMAL METRIC PWP (HTSSOP) DNT (WSON) UNIT
14 PINS 12 PINS
RθJA Junction-to-ambient thermal resistance(1) 39.3 33.4 RθJCbot Junction-to-case (bottom) thermal resistance(1) 2.0 1.9 ψJB Junction-to-board thermal characteristic parameter 19.3 11.3 °C/W RθJB Junction-to-board thermal resistance 19.6 11.1 RθJCtop Junction-to-case (top) thermal resistance 22.8 24.7 ψJT Junction-to-top thermal characteristic parameter 0.5 0.2 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM5160-Q1
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6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C(1)(2) for the LM5160- Q1. Unless otherwise stated, VIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISD Input Shutdown Current VIN = 24 V, EN/UVLO = 0 V 50 90.7 µA IOP Input Operating Current VIN = 24 V, FB = 3 V, Non-switching 2.3 2.84 mA VCC SUPPLY VCC Bias Regulator Output VIN = 24 V, ICC = 20 mA 6.47 7.5 8.52 V VCC Bias Regulator Current Limit VIN = 24 V 30 mA VCC(UV) VCC Undervoltage Threshold VCC rising 3.98 4.1 V VCC(HYS) VCC Undervoltage Hysteresis VCC falling 185 mV VCC(LDO) VIN - VCC Dropout Voltage VIN = 4.5 V, ICC = 20 mA 165 260 mV HIGH-SIDE FET RDS(ON) High Side On Resistance V(BST - SW) = 7 V, ISW = 1 A 0.29 Ω BST(UV) Bootstrap Gate Drive UV V(BST - SW) rising 2.93 3.6 V BST(HYS) Gate Drive UV hysteresis V(BST - SW) falling 200 mV LOW-SIDE FET RDS(ON) Low Side On Resistance ISW = 1 A 0.13 Ω HIGH SIDE CURRENT LIMIT ILIM (HS) High Side Current Limit Threshold 2.125 2.5 2.875 A TRES Current Limit Response Time ILIM (HS)Threshold detect to FET Turn-off 100 ns TOFF1 Current Limit Forced Off-Time FB = 0 V, VIN = 65 V 16 29 39.8 µs TOFF2 Current Limit Forced Off-Time FB = 1 V, VIN = 24 V 2.18 3.5 5.12 µs LOW SIDE CURRENT LIMIT ISOURCE(LS) Sourcing Current Limit 1.9 2.5 3.0 A ISINK(LS) Sinking Current Limit 5.4 DIODE EMULATION VFPWM(LOW) FPWM Input Logic Low VIN = 24 V 1 V VFPWM(HIGH) FPWM Input Logic High VIN = 24 V 3 IZX Zero Cross Detect Current FPWM = 0 (Diode Emulation) 0 mA REGULATION COMPARATOR VIN = 24 V (WSON-12) 1.977 2 2.017 VREF FB Regulation Level V VIN = 24 V (HTSSOP-14) 1.975 1.995 2.015 I(Bias) FB Input Bias Current VIN = 24 V 100 nA ERROR CORRECTION AMPLIFIER & SOFT-START GM Error Amp Transconductance FB = VREF (+/–) 10 mV 105 µA/V IEA(Source) Error Amp Source Current FB = 1 V, SS = 1 V 7.62 10.2 12.51 µA IEA(Sink) Error Amp Sink Current FB = 5 V, SS = 2.25 V 7.46 10 12.2 V(SS-FB) VSS - VFB Clamp Voltage FB = 1.75 V, CSS= 1 nF 135 mV ISS Soft-Start Charging current SS = 0.5 V 7.63 10.2 12.5 µA ENABLE/UVLO VUVLO (TH) UVLO Threshold EN/UVLO rising 1.213 1.24 1.277 V IUVLO(HYS) UVLO Hysteresis Current EN/UVLO = 1.4 V 15 20 25 µA VSD(TH) Shutdown Mode Threshold EN/UVLO falling 0.28 0.35 V VSD(HYS) Shutdown Threshold Hysteresis EN/UVLO rising 47 mV THERMAL SHUTDOWN TSD Thermal Shutdown Threshold 175 TSD(HYS) Thermal Shutdown Hysteresis 20
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www.ti.com SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015 (1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD •RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.
6.6 Switching Characteristics(1)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C for the LM5160-Q1. Unless otherwise stated, VIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MINIMUM OFF-TIME TOFF-MIN Minimum Off-Time, FB = 0 V 170 ns ON-TIME GENERATOR TON Test 1 VIN = 24 V, RON = 100 kΩ 312 428 520 TON Test 2 VIN = 24 V, RON = 200 kΩ 625 818 1040 ns TON Test 3 VIN = 8 V, RON = 100 kΩ 937 1247 1563 TON Test 4 VIN = 65 V, RON = 100 kΩ 132 176 220 (1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM5160-Q1
6.7 Typical Characteristics
At TA = 25°C and applicable to LM5160-Q1, unless otherwise noted. Figure 1. Efficiency at 500 kHz Figure 2. Efficiency at 250 kHz Figure 3. Efficiency CCM vs. DCM at 300kHz Figure 4. Efficiency vs. Input Voltage at 300kHz Figure 5. VCC vs. VIN Figure 6. VCC vs. ICC
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At TA = 25°C and applicable to LM5160-Q1, unless otherwise noted. Figure 13. Input Operating Current vs. Temperature Figure 14. Input Shutdown Current vs. Temperature Figure 15. VCC UVLO vs. Temperature Figure 16. Current Limit vs. Temperature Figure 17. FPWM Threshold vs. Temperature Figure 18. Switch Resistance vs. Temperature
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2.0V VILIM LM5160 RON CURRENT LIMIT COMPARATOR VCC UVLO ON/OFF TIMERS CONSTANT ON-TIME CONTROL LOGIC 1.24V VCC REGULATOR VIN FEEDBACK COMPARATOR DISABLE THERMAL SHUTDOWN EN/UVLO STANDBY SHUTDOWN BIAS REGULATOR 0.35V 20µA VCC FPWM SS CURRENT LIMIT TIMER PGND VIN GM ERROR AMP DIODE EMULATION VIN RESR COUT VOUT VOUT CIN RON L CBST CVCC CSS RUV2 RUV1 RFB2 RFB1 LM5160-Q1 www.ti.com SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015
7 Detailed Description
7.1 Overview
The LM5160 family of step-down switching regulators features all the functions needed to implement a low cost, efficient buck converter capable of supplying 1.5 A to the load. This high voltage regulator contains 65-V N- Channel buck and synchronous rectifier switches and is available in the WSON-12 package. The LM5160-Q1 is available in the HTSSOP-14 package. The regulator operation is based on constant on-time control where the on-time is inversely proportional to input voltage VIN. This feature maintains a relatively constant operating frequency with load and input voltage variations. A constant on-time switching regulator requires no loop compensation resulting in fast load transient response. Peak current limit detection circuit is implemented with a forced off-time during current limiting which is inversely proportional to voltage at the feedback pin, VFB and directly proportional to VIN. Varying the current limit off-time with VFB and VIN ensures short circuit protection with minimal current limit foldback. The LM5160 can be applied in numerous end equipment systems requiring efficient step-down regulation from higher input voltages. This regulator is well suited for 24 V industrial systems as well as 48 V telecom and PoE voltage ranges. The LM5160 integrates an under-voltage lockout (EN/UVLO) circuit to prevent faulty operation of the device at low input voltages and features intelligent current limit and thermal shutdown to protect the device during overload or short circuit. The LM5160 device name is used generically throughout this document and represents both the LM5160-Q1 and LM5160A unless stated otherwise. The only difference between the two is the ability to connect an external voltage source to the VCC pin of the LM5160A.
7.2 Functional Block Diagram
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V (R R )V V R u OUT sw 10 ON VF Hz R 1 10 u u LM5160-Q1 SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015 www.ti.com
7.3 Feature Description
7.3.1 Control Circuit
The LM5160 step-down switching regulator employs a control principle based on a comparator and a one-shot on-timer, with the output voltage feedback (FB) compared to the voltage at the Soft-Start (SS) pin (VSS). If the FB voltage is below VSS, the internal buck switch is turned on for a time period determined by the input voltage and one-shot programming resistor (RON). Following the on-time, the buck switch must remain off for the minimum off-time forced by the minimum off-time one-shot. The buck switch remains off until the FB voltage falls below the Soft-Start again, when it turns back on for another on-time one-shot period. During a rapid start-up or when the load current increases suddenly, the regulator will operate with minimum off- time per cycle. When regulating the output in steady state operation, the off-time will automatically adjust to produce the SW pin duty cycle required for output voltage regulation. When in regulation, the LM5160 operates in continuous conduction mode at heavy load currents. If the FPWM pin is connected to ground or left floating, the regulator will operate in discontinuous conduction mode at light load with the synchronous rectifier FET in diode emulation. With sufficient load, the LM5160 operates in continuous conduction mode with the inductor current never reaching zero during the off-time of the high side FET. In this mode the operating frequency remains relatively constant with load and line variations. The minimum load current for continuous conduction mode is one-half the inductor’s ripple current amplitude. The operating frequency is programmed by the RON pin resistor and can be calculated from Equation 1 with RON expressed in ohms. (1) In discontinuous conduction mode, current through the inductor ramps up from zero to a peak value during the on-time, then ramps back to zero before the end of the off-time. The next on-time period starts when the voltage at FB falls below VSS. When the inductor current is zero during the high side FET off-time, the load current is supplied by the output capacitor. In this mode, the operating switching frequency is lower than the continuous conduction mode switching frequency and the frequency varies with load. The discontinuous conduction mode maintains conversion efficiency at light loads since the switching losses decrease with the decrease in load and frequency. The output voltage is set by two external resistors ( RFB1, RFB2). The regulated output voltage is calculated from Equation 2, where VREF = 2 V (typ) is the feedback reference voltage. (2)
7.3.2 VCC Regulator
The LM5160 contains an internal high voltage linear regulator with a nominal output voltage of 7.5 V (typ). The VCC regulator is internally current limited to 30 mA (minimum). This regulator supplies power to internal circuit blocks including the synchronous FET gate driver and the logic circuits. When the voltage on the VCC pin reaches the under-voltage lockout (VCC(UV)) threshold of 3.98 V (typ), the IC is enabled. An external capacitor at the VCC pin stabilizes the regulator and supplies transient VCC current to the gate drivers. An internal diode connected from VCC to the BST pin replenishes the charge in the high side gate drive bootstrap capacitor when the SW pin is low. In high input voltage applications, the power dissipated in the regulator is significant and can limit the efficiency and maximum achievable output power. The LM5160A allows the internal VCC regulator power loss to be reduced by supplying the VCC voltage via a diode from an external voltage source regulated between 9V and 13 V. The external VCC bias can be supplied from the LM5160A converter output rail if the regulation voltage is within this range. When the VCC pin of the LM5160A is raised above the regulation voltage (7.5 V typical), the internal regulator is disabled and the power dissipation in the IC is reduced. The only difference between the LM5160 and LM5160A is wide operating VCC voltage range of the LM5160A.
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OFF(CL) FB 5VT s 24V 12 P OUT ON 10 SW VR F 1 10 : u u ON ON IN R 1 10T s V u u LM5160-Q1 www.ti.com SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015 Feature Description (continued)
7.3.3 Regulation Comparator
The feedback voltage at the FB pin is compared to the SS pin voltage VSS. In normal operation when the output voltage is in regulation, an on-time period is initiated when the voltage at FB pin falls below VSS. The high side buck switch will stay on for the on-time one-shot period causing the FB voltage to rise. After the on-time period expires, the high side switch will remain off until the FB voltage falls below VSS. During the startup, the FB voltage will be below VSS at the end of each on-time period and the high side switch turns on again after the minimum forced off-time of 170 ns (typ). When the output is shorted to ground (FB = 0 V), the high side peak current limit is triggered, the high side FET is turned off, and remains off for a period determined by the current limit off-timer. See the Current Limit section for additional information.
7.3.4 Soft-Start
The soft-start feature of the LM5160 allows the converter to gradually reach a steady state operating point, thereby reducing start-up stresses and current surges. When the EN/UVLO pin is above the EN/UVLO standby threshold VUVLO(TH) = 1.24 V (typ) and the VCC exceeds the VCC under-voltage VCC(UV) = 3.98 V (typ) threshold, an internal 10 µA current source charges the external capacitor at the SS pin (CSS) from 0 V to 2 V. The voltage at the SS pin is the non-inverting input of the internal FB comparator. The soft-start interval ends when the SS capacitor is charged to the 2V reference level. The ramping voltage at the SS pin produces a controlled, monotonic output voltage start-up. A minimum 1 nF soft-start capacitor should be used in all applications.
7.3.5 Error Transconductance (GM) Amplifier
The LM5160 provides a trans-conductance (GM) error amplifier that minimizes the difference between the reference voltage (VREF) and the average feedback (FB) voltage. This amplifier reduces the load and line regulation errors that are common in constant-on-time regulators. The soft-start capacitor (CSS) provides compensation for this error correction loop. The soft-start capacitor should be greater than 1 nF to ensure stability.
7.3.6 On-Time Generator
The on-time of the LM5160 high side FET is determined by the RON resistor and is inversely proportional to the input voltage (VIN). The inverse relationship with VIN results in a nearly constant frequency as VIN is varied. The on-time can be calculated from Equation 3 with RON expressed in ohms. (3) To set a specific continuous conduction mode switching frequency (FSW expressed in Hz), the RON resistor is determined from the following: (4) RON should be selected for a minimum on-time (at maximum VIN) greater than 150 ns for proper operation. This minimum on-time requirement will limit the maximum switching frequency of applications with relatively high VIN and low VOUT.
7.3.7 Current Limit
The LM5160 provides an intelligent current limit off-timer that adjusts the off-time to reduce the foldback in the current limit. If the peak value of the current in the buck switch exceeds 2.5 A (typ) the present on-time period is immediately terminated, and a non-resettable off-timer is initiated. The length of the off-time is controlled by the FB voltage and the input voltage VIN. As an example, when VFB = 0 V and VIN = 24 V, the off-time is set to 10 μs. This condition would occur if the output is shorted or during the initial phase of start-up. In cases of output overload where the FB voltage is greater than zero volts (a soft short), the current limit off-time is reduced. Reducing the off-time during less severe overloads reduces the current limit foldback, overload recovery time, and start-up time. The current limit off-time, TOFF(CL) is calculated from Equation 5: (5) Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LM5160-Q1
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7.3.8 N-Channel Buck Switch and Driver
The LM5160 integrates an N-Channel buck switch and associated floating high side gate driver. The gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage bootstrap diode. A 10 nF or larger ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the high-side driver during the buck switch on-time. During the off-time, the SW node is pulled down to approximately 0 V and the bootstrap capacitor charges from VCC through the internal bootstrap diode. The minimum off-time of 170 ns (typ) provides a minimum time each cycle to recharge the bootstrap capacitor.
7.3.9 Synchronous Rectifier
The LM5160 provides an internal low side synchronous rectifier N-Channel FET. This low side FET provides a low resistance path for the inductor current when the high-side FET is turned off. With the FPWM pin connected to ground or left floating, the LM5160 synchronous rectifier operates in diode emulation mode. Diode emulation enables the pulse-skipping during light load conditions. This leads to a reduction in the average switching frequency at light loads. Switching losses and FET gate driver losses, both of which are proportional to switching frequency, are significantly reduced and efficiency is improved. This pulse- skipping mode also reduces the circulating inductor currents and losses associated with a continuous conduction mode (CCM). When the FPWM pin is pulled high, diode emulation is disabled. The inductor current can flow in either direction through the low side FET resulting in CCM operation with nearly constant switching frequency. A negative sink current limit circuit limits the current that can flow into the SW pin and through the low side FET to ground. In a buck regulator application, large negative current will only flow from VOUT to the SW pin if VOUT is lifted above the output regulation set-point.
7.3.10 Enable / Under-Voltage Lockout (EN/UVLO)
The LM5160 contains a dual level under-voltage lockout (EN/UVLO) circuit. When the EN/UVLO pin voltage is below 0.35 V, the regulator is in a low current shutdown mode. When the EN/UVLO pin voltage is greater than regulator is active but converter switching remains disabled. When the voltage at the VCC pin exceeds the VCC rising threshold VCC(UV) = 3.98 V (typ) and the EN/UVLO pin voltage is greater than 1.24 V, normal switching operation begins. An external resistor voltage divider from VIN to GND can be used to set the minimum operating voltage of the regulator. EN/UVLO hysteresis is accomplished with an internal 20 μA (typ) current source (IUVLO(HYS)) that is switched on or off into the impedance of the EN/UVLO pin resistor divider. When the EN/UVLO threshold is exceeded, the current source is activated to effectively raise the voltage at the EN/UVLO pin. The hysteresis is equal to the value of this current times the upper resistance of the resistor divider, (RUV2) (See Functional Block Diagram ).
7.3.11 Thermal Protection
The LM5160 should be operated such that the junction temperature does not exceed 150 °C during normal operation. An internal Thermal Shutdown circuit is provided to protect the LM5160 in the event of a higher than normal junction temperature. When activated, typically at 175 °C, the controller is forced into a low power reset state, disabling the high side buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental device overheating. When the junction temperature falls below 155 °C (typical hysteresis = 20 °C), the VCC regulator is enabled, and operation resumes.
7.4 Device Functional Modes
7.4.1 Forced Pulse Width Modulation (FPWM) Mode
The Synchronous Rectifier section gives a brief introduction to the LM5160 diode emulation feature. The FPWM pin allows the power supply designer to select either CCM or DCM mode of operation at light loads. When the FPWM pin is connected to ground or left floating (FPWM = 0), a pulse-skipping mode is enabled and a zero- cross current detector circuit is enabled. The zero-cross detector will turn off the low side FET when the inductor current falls to zero (IZX, see Electrical Characteristics ). This feature allows the LM5160 regulator to operate in DCM mode at light loads. In the DCM state, the switching frequency will decrease with lighter loads.
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improves the output transient response to step load changes and provides nearly constant switching frequency. Table 1. FPWM Pin Mode Summary The FPWM pin is grounded or left floating. DCM enabled at lightGND or Floating (High Z) 0 loads. The FPWM pin is connected to VCC. The LM5160 then operatesVCC 1 in CCM mode at light loads.
7.4.2 Under-Voltage Detector
explained in Enable / Under-Voltage Lockout (EN/UVLO) . Table 2. UVLO Pin Mode Summary VCC regulator disabled. High and low side< 0.35 V Off Shutdown FETs disabled. VCC regulator enabled. High and low side0.35 V to 1.24 V On Standby FETs disabled. VCC > VCC(UV) Operating VCC regulator enabled. Switching enabled. switching when the VCC(UV) = 3.98 V (typ) is satisfied.
1 F μ
8 Applications and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
below, the components are labeled by numbers instead of the descriptive name used in the previous sections. For example, R3 represents RON and so on. Figure 19. Synchronous Buck Application Circuit
8.2.1.1 Design Requirements
Table 3. Design Parameters
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O IN, max O min IN, max SW O, max V (V V ) L V F I 0.4 u u u u OUT ON 10 SW VR F 1 10 : u u IN, max OUT SW, max (@ V ) IN, max ON, min VF V T (ns) u IN, min IN, min OUT SW, max (@ V ) IN, min OFF, min V V F V T (ns) u OUTFB2 FB1 REF VR 1R V LM5160-Q1 www.ti.com SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Output Resistor Divider Selection
With the required output voltage set point at 5 V and VFB = 2 V (typ.), the ratio of R6 (RFB1) to R5 (RFB2) can be calculated using the formula: (6) The resistor ratio calculates to be 3:2. Standard values of R6 (RFB1) = 2 kΩ and R5 (RFB2 ) =3.01 kΩ are chosen. Higher or lower values could be used as long as the ratio of the 3:2 is maintained.
8.2.1.2.2 Frequency Selection
The duty cycle required to maintain output regulation at the minimum input voltage restricts the maximum switching frequency of LM5160. The maximum value of the minimum forced off-time TOFF,min (max), limits the duty cycle and therefore the switching frequency. The maximum frequency that will avoid output dropout at minimum input voltage can be calculated from Equation 7. (7) For this design example, the maximum frequency based on the minimum off-time limitation for TOFF,min(typ) = 170 ns is calculated to be FSW,max(@VIN,min) = 2.9 MHz. This value is well above 1 MHz, the maximum possible operating frequency of the LM5160. Therefore, the minimum off-time parameter cannot be used further for the maximum achievable switching frequency calculation in this application. At the maximum input voltage, the maximum switching frequency of LM5160 is restricted by the minimum on- time, TON,min which limits the minimum duty cycle of the converter. The maximum frequency at maximum input voltage can be calculated using Equation 8. (8) Using Equation 8 and TON,min (typ) = 150 ns, the maximum achievable switching frequency is FSW,max(@VIN,min)=514 kHz. Taking this value as the maximum possible operational switching frequency over the input voltage range in this application, a nominal switching frequency of FSW = 300 kHz is chosen for this design. The value of the resistor, RON sets the nominal switching frequency based on Equation 9. (9) For this particular application with FSW = 300 kHz, RON calculates to be 167 kΩ . Selecting a standard value for R3 (RON) = 169 kΩ (±1%) will result in an ideal nominal frequency of 296 kHz. The resistor value may need to adjusted further in order to achieve the required switching frequency as the switching frequency in COTs varies slightly(±10%) with input voltage and/or output current. Operation at a lower nominal switching frequency will result in higher efficiency but increase in the inductor and capacitor values leading to a larger total solution size.
8.2.1.2.3 Inductor Selection
The inductor is selected to limit the inductor ripple current between 20 and 40 percent of the maximum load current. The minimum value of the inductor required in this application can be calculated from: (10) Based on Equation 10 , the minimum value of the inductor is calculated to be 26 µH for VIN = 65 V (max) and inductor current ripple equal to 40 percent of the maximum load current. Allowing some margin for inductance variation and inductor saturation, a higher standard value of L1 (L) = 47 µH is selected for this design. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LM5160-Q1
O, max IN IN, ripple SW I D (1 D) C V F u u ' u O ESR REF L, min 25 mV VR V I ut u ' L, max OUT SW O, ripple I C 8 F V u u' L, max L(peak) O, max I I I 2 O IN O L IN SW V (V V )I V F L u ' u u LM5160-Q1 SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015 www.ti.com The peak inductor current at maximum load must be smaller than the minimum current limit threshold of the high side FET as given in Electrical Characteristics table. The inductor current ripple at any input voltage is given by: (11) The peak-to-peak inductor current ripple is calculated to be 180 mA and 332 mA at the minimum and maximum input voltages respectively. The maximum peak inductor current in the buck FET is given by: (12) In this design with maximum output current of 1.5 A, the maximum peak inductor current is calculated to be approximately 1.67 A which is less than the minimum high-side FET current limit threshold. The saturation current of the inductor must also be carefully considered. The peak value of the inductor current will be bound by the high side FET current limit during overload or short circuit conditions. Based on the high side FET current limit specification in the Electrical Characteristics , an inductor with saturation current rating above 2.875 A (max) should be selected.
8.2.1.2.4 Output Capacitor Selection
The output capacitor is selected to limit the capacitive ripple at the output of the regulator. Maximum capacitive ripple is observed at maximum input voltage. The output capacitance required for a ripple voltage ∆VO across the capacitor is given by Equation 13. (13) Substituting ∆VO, ripple = 10 mV gives COUT = 14 μF. Two standard 10 μF ceramic capacitors in parallel (C8, C9) are selected. An X7R type capacitor with a voltage rating 16 V or higher should be used for COUT (C8, C9) to limit the reduction of capacitance due to dc bias voltage.
8.2.1.2.5 Series Ripple Resistor - RESR
The series resistor is selected such that sufficient ripple injection is ensured at the feedback node FB. The ripple produced by RESR is proportional to the inductor current ripple, and therefore, RESR should be chosen for minimum inductor current ripple which occurs at minimum input voltage. The RESR is calculated by Equation 14. (14) With VO = 5 V, VREF = 2 V and ΔIL, min = 180 mA (at VIN, min= 10 V) as calculated in Equation 11, Equation 14 requires an RESR greater than or equal to 0.35 Ω. Selecting R7 (RESR) = 0.47 Ω will result in ~150 mV of maximum output voltage ripple at VIN,max. For applications requiring lower output voltage ripple, Type II or Type III ripple injection circuits should be used as described in Ripple Configuration.
8.2.1.2.6 VCC and Bootstrap Capacitor
The VCC capacitor charges the bootstrap capacitor during the off-time of the high side switch and powers internal logic circuits and the low side sync FET gate driver. The bootstrap capacitor biases the high side gate driver during the high side FET on-time. A good value for C5 (CVCC) is 1 µF. A good choice for C4 (CBST) is 10 nF. Both should be high quality X7R ceramic capacitors.
8.2.1.2.7 Input Capacitor Selection
The input capacitor must be large enough to limit the input voltage ripple to an acceptable level. Equation 15 provides the input capacitance CIN required for a worst case input ripple of ∆VIN, ripple . (15)
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IN, UVLO(rising) UVLO(TH) UV1 RV V 1 R § · ¨ ¸ © ¹ IN(HYS) UVLO(HYS) UV2V I R u SS Startup SS SS I T C V u LM5160-Q1 www.ti.com SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015 CIN (C1, C10) supplies most of the switch current during the on-time to limit the voltage ripple at the VIN pin. At maximum load current, when the buck switch turns on, the current into the VIN pin quickly increases to the valley current of the inductor ripple and then ramps up to the peak of the inductor ripple during the on-time of the high side FET. The average current during the on-time is the output load current. For a worst case calculation, CIN must supply this average load current during the maximum on-time, without letting the voltage at VIN drop more than the desired input ripple. For this design, the input voltage drop is limited to 0.5 V and the value of CIN is calculated using Equation 15. Based on Equation 15, the value of the input capacitor is calculated to be approximately 2.5 µF at D = 0.5. Taking into account the decrease in capacitance over an applied voltage, two standard value ceramic capacitors of 2.2 μF are selected for C1 and C10. The input capacitors should be rated for the maximum input voltage under all operating and transient conditions. A 100 V, X7R dielectric was selected for this design. A third input capacitor C2 may be needed in this design as a bypass path for the high frequency component of the input switching current. The value of C2 is 0.47 μF and this bypass capacitor (when used with the LM5160- Q1 HTSSOP-14 package, a bypass capacitor C2 = 0.1 μF is used) should be placed directly across VIN and PGND (pin 3 and 2) near the IC. The CIN values and location are critical to reducing switching noise and transients.
8.2.1.2.8 Soft-Start Capacitor Selection
The capacitor at the SS pin determines the soft-start time, i.e. the time for the output voltage to reach its final steady state value. The capacitor value is determined from Equation 16: (16) With C3 (CSS) set at 22 nF and the Vss = 2 V, ISS = 10 µA, the TStartup should measure approximately 4 ms.
8.2.1.2.9 EN/UVLO Resistor Selection
The UVLO resistors R1 (RUV2) and R2 (RUV1) set the input under-voltage lockout threshold and hysteresis according to the following equations: (17) and, (18) From the Electrical Characteristics table, IUVLO(HYS) = 20 μA (typ). To design for VIN rising threshold (VIN, UVLO(rising)) at 10 V and EN/UVLO hysteresis of 2.5 V, Equation 17 and Equation 18 yield RUV1 = 17.98 kΩ and RUV2 = 125 kΩ . Selecting 1% standard value of R2 (RUV1) = 18.2 kΩ and R1 (RUV2) = 127 kΩ results in UVLO thresholds and hysteresis of 9.89 V and 2.54 V respectively. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LM5160-Q1
8.2.1.3 Application Performance Plots
Figure 20. Load Regulation Figure 21. Efficiency vs IOUT Figure 22. EN/UVLO Startup at VIN= 24 V and IOUT = 1 A Figure 23. Pre-Bias Startup at VIN= 48 V and RLOAD = 3Ω Figure 24. EN/UVLO Startup at VIN= 24 V and RLOAD = 100Ω Figure 25. Startup at VIN= 48 V and RLOAD = 10Ω
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Figure 26. Load Transient (300 mA - 1.5 A) at VIN = 24 V Figure 27. Output Short-Circuit at VIN = 48 V schematic of the Fly-Buck application circuit is shown in Figure 28 . Figure 28. 12 V/ 4.5 W Fly-Buck Schematic
8.2.2.1 LM5160 Fly-Buck Design Requirements
secondary load current capability from 0 mA to 400 mA. The primary side remains unloaded in this application. The switching frequency is set at 300 kHz (nominal). This design achieves greater than 88% peak efficiency. Table 4. Design Parameters
OUT2 IN(MIN) sw I V 1C V V f § · u ¨ ¸ ¨ ¸ ' © ¹ R(diode) IN(max) N2V V 32 V 1.5 48 VN1 u u OUT(ISO) OUT V 0.7 V V 8.47 V 1.5 LM5160-Q1 SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015 www.ti.com
8.2.2.2 Detailed Design Procedure
The Fly-Buck converter design procedure closely follows the buck converter design outlined in LM5160 Synchronous Buck (10-V to 60-V Input, 5-V Output, 1.5-A Load) . The selection of primary output voltage, transformer turns ratio, rectifier diode, and output capacitors are covered here.
8.2.2.2.1 Selection of VOUT1 and Turns Ratio
The primary output voltage in a Fly-Buck converter should be no more than one half of the minimum input voltage. For a minimum VIN of 18 V, the primary output voltage (VOUT) should be no higher than 9 V. To generate an isolated output voltage of VOUT (ISO) = 12 V, a transformer turns ratio (N1:N2) of 1:1.5 is selected. Using this turns ration, the required primary output voltage VOUT is calculated to be: (19) The 0.7 V subtracted from VOUT(ISO) represents the forward voltage drop of the secondary rectifier diode. Fine tuning the primary side VOUT1 may be required to account for voltage errors due to the leakage inductance of the transformer and the resistance of the transformer windings and the low side FET of LM5160.
8.2.2.2.2 Secondary Rectifier Diode
The secondary rectifier diode must block the maximum input voltage multiplied by the transformer turns ratio. The minimum diode reverse voltage VR(diode) rating is given by: (20) A diode of 60 V or higher reverse voltage rating should be selected in this application. If the input voltage (VIN) has transients above the normal operating maximum input voltage of 32 V, then the worst case transient input voltage should be used in the diode voltage calculation of Equation 20.
8.2.2.2.3 External Ripple Circuit
Type 3 ripple circuit is required for Fly-Buck applications. The design procedure for ripple components is identical to that in a buck converter. See Ripple Configuration for ripple design information.
8.2.2.2.4 Output Capacitor (COUT2)
The Fly-Buck output capacitor conducts higher ripple current than a buck converter output capacitor. The capacitive ripple for the isolated output capacitor is calculated based on the time the rectifier diode is off. During this time the entire output current is supplied by the output capacitor. The required capacitance for a worst case VOUT2 (VOUT (ISO)) ripple voltage can be calculated using Equation 21 where, ΔVOUT2 is the target ripple at the secondary output. (21) Equation 21 is an approximation and ignores the ripple components associated with ESR and ESL of the output capacitor. For a ΔVOUT2 = 100 mV, Equation 21 requires COUT2 = 6.5 µF. When selecting a capacitor, its DC bias should be considered to ensure sufficient capacitance over the output voltage.
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8.2.2.3 Application Performance Plots
Figure 30. Efficiency vs. IOUT2Figure 29. Load Regulation Figure 32. Load Transient at IOUT2 = 100 mA - 300mAFigure 31. Primary Switch Node at VIN = 24 V Figure 34. Secondary Short at IOUT2 = 600mAFigure 33. VIN Startup at IOUT2 = 200 mA
applied to the VCC pin, either from VOUT or an external supply should be between 9V and 13V. Figure 35. 12 V/ 4.5 W Fly-Buck Schematic with LM5160A
8.2.4 Ripple Configuration
one-shot, and the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage. enough to dominate any noise present at the feedback node.
- Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
- Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor and
converters, with multiple on-time bursts in close succession followed by a long off-time. triangular ramp. This triangular ramp is then ac coupled into the feedback node (FB) using the capacitor CB. ripple is imperative. See application note AN-1481 for more details for each ripple generation method.
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Table 5. Ripple Configuration
8.3 Do's and Don'ts
requirement warrants an external Vcc bias, the LM5160A should be used.
9 Power Supply Recommendations
maintain the stability of the converter. the input voltage to the IC and prevent droop or oscillation, over the entire load range.
10 Layout
10.1 Layout Guidelines
- CIN: The loop consisting of input capacitor (CIN), VIN pin, and PGND pin carries the switching current. Therefore, in both the LM5160 and the LM5160A, the input capacitor should be placed close to the IC, directly across VIN and PGND pins, and the connections to these two pins should be direct to minimize the loop area. In general it is not possible to place all of input capacitances near the IC. A good layout practice includes placing the bulk capacitor as close as possible to the VIN pin (see Figure 36).When using the LM5160-Q1 HTSSOP-14 package, a bypass capacitor measuring ~0.1 μF should be placed directly across VIN and PGND (pin 3 and 2), as close as possible to the IC while complying with all layout design rules.
- CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the connecting trace length and loop area should be minimized (see Figure 36).
- The feedback trace carries the output voltage information and a small ripple component that is necessary for proper operation of both the LM5160 and the LM5160A. Therefore, care should be taken while routing the feedback trace to avoid coupling any noise into this pin. In particular, the feedback trace should be short and not run close to magnetic components, or parallel to any other switching trace.
- SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a source of noise. The SW node area should be minimized. In particular, the SW node should not be inadvertently connected to a copper plane or pour.
10.2 Layout Example
Figure 36. Placement of Bypass Capacitors
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www.ti.com SNVSAE4A –JULY 2015–REVISED NOVEMBER 2015
11 Device and Documentation Support
11.1 Related Documentation
AN-2292 Designing an Isolated Buck (Fly-Buck) Converter AN-1481 Controlling Output Ripple & Achieving ESR Independence in Constant On-Time Regulator Designs
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.3 Trademarks
Fly-Buck, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LM5160-Q1
www.ti.com 14-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM5160QPWPQ1 ACTIVE HTSSOP PWP 14 94 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 5160 QPWPQ1 LM5160QPWPRQ1 ACTIVE HTSSOP PWP 14 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 5160 QPWPQ1 LM5160QPWPTQ1 ACTIVE HTSSOP PWP 14 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 5160 QPWPQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
www.ti.com 14-Oct-2015 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM5160-Q1 :
- Catalog: LM5160 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5160QPWPRQ1 HTSSOP PWP 14 2500 367.0 367.0 35.0 LM5160QPWPTQ1 HTSSOP PWP 14 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 Pack Materials-Page 2
www.ti.com MXA14A (Rev A)
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