LMQ66420MC3RXBRQ1

Texas Instruments

LMQ664x0-Q1, 36-V, 1-A, 2-A, and 3-A Ultra-Small Synchronous Automotive Step-Down Converter with Integrated VIN Bypass and CBOOT Capacitors FEBRUARY 2022

Manufacturer: Texas Instruments

Document: 48 Pages / 3Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse L parts

Online Datasheet

Read LMQ66420MC3RXBRQ1 online.

LMQ66430-Q1 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 48

Technical content

LMQ664x0-Q1, 36-V, 1-A, 2-A, and 3-A Ultra-Small Synchronous Automotive Step-Down Converter with Integrated VIN Bypass and CBOOT Capacitors

1 Features

AEC-Q100-qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA
One of the industry's lowest IQ: – Ultra-low 1.5-µA IQ (switching) at 13.5 VIN,

3.3 V fixed VOUT and IQ < 3 μA at 150°C

– Greater than 85% efficiency at 1 mA

Designed for automotive applications: – Junction temperature range: –40°C to +150°C – NC pin between critical pins for better reliability – Best in-class pin FMEA – Supports 42-V automotive load dump transients – Supports 3-VIN for automotive cold crank – Adjustable up to 95% of VIN, 3.3-V, and 5-V fixed VOUT options available
Miniature solution size and low component cost: – One of the industry's smallest solution size with the highest power density and performance – Integrated input bypass capacitors and bootstrap capacitor reducing EMI – 2.6-mm × 2.6-mm enhanced QFN package with wettable flanks – Internal compensation
Optimized for ultra-low EMI requirements: – Dual random spread spectrum (DRSS) for enhanced EMI performance across low and high-frequency bands – Enhanced QFN package minimizes switch node ringing – Pin selectable FPWM mode for constant frequency at light loads and FSW synchronization with MODE/SYNC pin – Adjustable FSW: 200 kHz–2.2 MHz with RT pin

2 Applications

Advanced driver assistance systems: radar ECU
Infotainment and cluster: head unit, eCall
Body electronics and lighting

3 Description

The LMQ664x0-Q1 is the industry's smallest 36-V, 3-A (available in 2-A and 1-A variants) synchronous step-down DC/DC converter with an integrated bypass and bootstrap capacitor in an enhanced QFN package. This easy-to-use converter supports a wide input voltage range of 2.7 V to 36 V (after start-up or once operating) with transients up to 42 V. The LMQ664x0-Q1 is specifically designed to meet low standby power requirements for always- on, automotive applications. Auto mode enables frequency foldback when operating at light loads, allowing an unloaded typical current consumption of 1.5 µA at 13.5 V IN and high light load efficiency. A seamless transition between PWM and PFM modes along with very low MOSFET ON resistances makes sure there is exceptional efficiency across the entire load range. The control architecture (peak current mode) and feature set are optimized for an ultra- small solution size with minimal output capacitance. The device minimizes input filter size by using dual-random spread spectrum (DRSS), a low-EMI enhanced QFN package, and an optimized pin-out. The MODE/SYNC and RT pin variants can be used to set or synchronize the frequency to avoid noise sensitive frequency bands. There are NC pins between critical high voltage pins, reducing potential failures (optimal pin FMEA). The rich feature set of the LMQ664x0-Q1 is designed to simplify implementation for a wide range of automotive end equipment. Device Information PART NUMBER PACKAGE (1) BODY SIZE (NOM) LMQ66430-Q1 WQFN (15) 2.60 mm × 2.60 mmLMQ66420-Q1 LMQ66410-Q1 (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Solution Size (16.5 mm × 13.5 mm) Output Current (A) Efficiency (%) 100 VIN = 12 V VIN = 18 V VIN = 24 V Efficiency: VOUT = 3.3 V (Fixed), 2.2 MHz ADVANCE INFORMATION LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

12.3 Receiving Notification of Documentation Updates..40

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES February 2022 * Advance Information LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

5 Device Comparison Table

Orderable Part Number (1) Output Current Output Voltage External Sync FSW Internal Capacitors Spread Spectrum Status LMQ66430MC3RXBRQ1 3 A 3.3-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed

2.2 MHz Yes Yes

LMQ66430MC5RXBRQ1 3 A 5-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed

2.2 MHz Yes Yes Contact TI

LMQ66420MC3RXBRQ1 2 A 3.3-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed LMQ66420MC5RXBRQ1 2 A 5-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed LMQ66410MC3RXBRQ1 1 A 3.3-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed LMQ66410MC5RXBRQ1 1 A 5-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed LMR66430MC5RXBRQ1 3 A 5-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed

2.2 MHz No Yes Contact TI

LMR66420MC5RXBRQ1 2 A 5-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed LMR66410MC5RXBRQ1 1 A 5-V Fixed / Adjustable Yes (PFM / FPWM Selectable) Fixed (1) For more information on device orderable part numbers, see Section 12.1.2. www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMQ66430-Q1

6 Pin Configuration and Functions

MODE/SYNC(B) VIN EN VOUT/FB RT(A) NC 2 NC NC VCC NC NC BOOT GND/DAP 6 7 14 13 PG SWPGND A. See Section 5 for more details. Pin 13 is factory-set for externally adjustable switching frequency RT variants only. B. Pin 13 is factory-set for fixed switching frequency MODE/SYNC variants only. C. Pin 11 is trimmed and factory-set for fixed output voltage VOUT/BIAS variants only. Figure 6-1. 15-Pin (2.6-mm × 2.6-mm) Enhanced QFN Package (Top View) Table 6-1. Pin Functions PIN I/O DESCRIPTION NAME NO. EN/UVLO 1 A Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN. Do not float this pin. NC 2 — No internal connection to device VIN 3 P Input supply to regulator. Two 22-nF capacitors are connected in series internally from this pin to the GND pin. Additional high-quality bypass capacitor or capacitors can be added directly to this pin and GND. NC 4 — No internal connection to device NC 5 — Middle point of the two internal series bypass capacitors PGND 6 G Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces. SW 7 P Regulator switch node. Connect to the power inductor. BOOT 8 P Bootstrap supply voltage for internal high-side driver. A 0.1-µF capacitor is internally connected from this pin to the SW pin. NC 9 — No internal connection to device VCC 10 A Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to GND. VOUT/FB 11 A Fixed output options and adjustable output options are available with the VOUT/FB pin variant. feedback resistor divider values. See Section 5 for more details. The FB function can be used to adjust the output voltage. Connect to tap point of feedback voltage divider. Do not float this pin. NC 12 — No internal connection to device RT or MODE/ SYNC 13 A For the RT variant, the switching frequency can be adjusted from 200 kHz to 2.2 MHz. For the MODE/SYNC variant, the device can operate in user-selectable PFM/FPWM mode and can be synchronized to an external clock. Do not float this pin. PG 14 A Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = power OK, low = power bad. It goes low when EN = low. It can be open or grounded when not used. GND/DAP 15 G Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND. A = Analog, P = Power, G = Ground LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range (1) PARAMETER MIN MAX UNIT Voltages VIN to GND –0.3 42 V SW to GND –0.3 VIN + 0.3 BOOT to SW –0.3 5.5 VCC to GND –0.3 5.5 VOUT/FB to GND –0.3 16 SYNC/MODE or RT to GND –0.3 5.5 PG to GND –0.3 20 EN to GND –0.3 42 Temperature TJ, junction temperature –40 150 °C Temperature Tstg, storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002, HBD ESD Classification Level 2 (1) ±2000 V Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C5 ±750 V (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) MIN MAX UNIT VIN Input voltage range for start-up 3.6 36 V Input voltage range after start-up 3.0 36 V VOUT Output voltage range with adjustable output voltage setup 1 18 V IOUT LMQ66430-Q1 continuous DC output current range 0 3 A IOUT LMQ66420-Q1 continuous DC output current range 0 2 A IOUT LMQ66410-Q1 continuous DC output current range 0 1 TJ Operating junction temperature –40 150 °C www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMQ66430-Q1

7.4 Thermal Information

The value of RθJA in this table is only valid for comparison with other packages. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application. For example, a 4-layer PCB can achieve a RθJA = 50℃/W. THERMAL METRIC (1) RLF (WQFN) UNIT

15 PINS

RθJA Junction-to-ambient thermal resistance for LMQ66430-2EVM 50 °C/W RθJA Junction-to-ambient thermal resistance 66.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 53.6 °C/W RθJB Junction-to-board thermal resistance 26.2 °C/W ψJT Junction-to-top characterization parameter 3.3 °C/W ψJB Junction-to-board characterization parameter 25.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are compliant through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following apply: VIN = 13.5 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) VINMIN Input voltage rising threshold for start-up Before start-up 3.2 3.35 3.5 V Input voltage falling threshold Once operating 2.45 2.7 3 V ISD(VIN) Shutdown quiescent current at the VIN pin EN = 0 V 0.25 1 µA IQVIN(nonsw) Nonswitching input current; measured at the VIN pin (1) Fixed 5-V VOUT, VVOUT/FB = 5.25 V 1.6 3 µA IQVIN(nonsw) Nonswitching input current; measured at the VIN pin (1) Fixed 3.3-V VOUT, VVOUT/FB = 3.47 V 1.2 2.2 µA ENABLE (EN PIN) VEN-WAKE EN wakeup threshold 0.5 0.7 1 V VEN-VOUT Precision enable rising threshold for VOUT 1.16 1.23 1.3 V VEN-HYST Enable hysteresis below VEN-VOUT 0.3 0.35 0.4 V ILKG-EN Enable pin input leakage current VEN = VIN = 13.5 V 10 nA INTERNAL LDO (VCC PIN) VCC VCC pin output voltage VFB = 0 V, IVCC = 1 mA 3.1 3.3 3.45 V VOLTAGE FEEDBACK (VOUT/FB PIN) VOUT Output voltage accuracy for fixed VOUT 5-V VOUT, VIN = 5.5 V to 36 V, FPWM mode 4.94 5.00 5.06 V VFB Internal reference voltage accuracy VOUT = 1 V, VIN = 3.0 V to 36 V, FPWM mode 0.99 1.00 1.01 V IFB(LKG) FB input current Adjustable configuration, FB = 1 V 10 nA CURRENT LIMITS IPEAKMAX High-side peak current limit LMQ66430-Q1 3.9 4.4 5 A IVALMAX Low-side valley current limit LMQ66430-Q1 2.9 3.5 4 A IPEAKMIN Minimum peak current limit LMQ66430-Q1, auto mode 0.69 A INEGMIN Low-side valley current negative limit LMQ66430-Q1, FPWM mode –1 –0.8 –0.6 A IPEAKMAX High-side peak current limit LMQ66420-Q1 2.8 3.4 3.9 A IVALMAX Low-side valley current limit LMQ66420-Q1 1.9 2.2 2.53 A IPEAKMIN Minimum peak current limit LMQ66420-Q1, auto mode 0.37 0.5 0.65 A LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

7.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are compliant through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following apply: VIN = 13.5 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INEGMIN Negative current limit LMQ66420-Q1, FPWM mode –1 –0.8 –0.6 A IPEAKMAX High-side peak current limit LMQ66410-Q1 1.4 1.8 2.1 A IVALMAX Low-side valley current limit LMQ66410-Q1 0.9 1.1 1.4 A IPEAKMIN Minimum peak current limit LMQ66410-Q1, auto mode 0.17 0.27 0.35 A INEGMIN Low-side valley current negative limit LMQ66410-Q1, FPWM mode –1 –0.8 –0.6 A IZC Zero-cross current limit Auto mode 30 80 135 mA POWER GOOD (PG PIN) PGOV PG upper threshold – rising % of VOUT/FB (fixed or adjustable output) 104% 108 111 PGUV PG upper threshold – falling % of VOUT/FB (fixed or adjustable output) 89% 91% 94.2 PGHYST PG recovery hysteresis for OV % of VOUT/FB target regulation voltage 2% 2.4% 2.8% PG recovery hysteresis for UV % of VOUT/FB target regulation voltage 1.1% 3.3% 5.9% VPG-VAL Minimum VIN for PG function VEN = 0 V, RPG_PU = 10 kΩ 1.5 V RPG PG ON resistance VEN = 3.3 V, 200-µA pullup current 100 Ω RPG PG ON resistance VEN = 0 V, 200-µA pullup current 100 Ω tRESET_FILTER PG deglitch delay at falling edge 25 40 75 µs tPG_ACT Delay time to PG high signal 1.35 2.5 4 ms SOFT START tSS Time from first SW pulse to VOUT/FB at 90% of set point 2 3.5 4.6 ms tHICCUP Time in hiccup before retry soft start 30 50 75 ms OSCILLATOR (SYNC/MODE PIN) tPULSE_H High duration needed to be recognized as a pulse 100 ns tPULSE_L Low duration needed to be recognized as a pulse 100 ns tSYNC High/Low level pulse maximum duration to be recognized as a valid clock signal 6 µs tMODE Time at one level needed to indicate FPWM or auto mode 12.5 µs fSYNC Frequency SYNC range 0.2 2.5 MHz VMODE_L SYNC/MODE input voltage low level threshold 1 V VMODE_H SYNC/MODE input voltage high level threshold 1.6 V OSCILLATOR (RT PIN) fADJ Frequency adjust range 0.25 2.2 MHz FSW(2p2MHz) Switching frequency with fixed 2.2 MHz RT pin tied to GND 2100 2200 2300 kHz FSW(Adj) Accuracy of external frequency, 400 kHz RRT = 39.2 kΩ, 0.1% resistor 340 400 460 kHz Accuracy of external frequency, 2.2 MHz RRT = 6.92 kΩ, 0.1% resistor 2100 2200 2450 kHz SWITCH NODE tON-MIN Minimum HS switch on time FPWM mode, IOUT = 1 A, 2.2 MHz fixed 65 75 ns tOFF-MIN Minimum HS switch off time 60 85 ns tON-MAX Maximum HS switch on time HS timeout in dropout 6 9 13 µs www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMQ66430-Q1

7.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by production testing. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IQVIN Input current to VIN VIN = 13.5 V, fixed 3.3-V VOUT, IOUT = 0 A, auto mode 1.5 µA VIN = 13.5 V, fixed 5-V VOUT, IOUT = 0 A, auto mode 2 µA POWER STAGE VDROP1 Input to output voltage differential to maintain VOUT regulation ≥ 95%, with frequency foldback VOUT = 3.3 V, fixed 2.2 MHz, IOUT = 1 A 0.2 V VOUT = 5 V, fixed 2.2 MHz, IOUT = 1 A 0.2 V VDROP2 Input to output voltage differential to maintain VOUT regulation ≥ 95% and FSW ≥ 1.85 MHz VOUT = 3.3 V, fixed 2.2 MHz, IOUT = 1 A 0.7 V Input to output voltage differential to maintain VOUT regulation ≥ 95% and FSW ≥ 1.85 MHz VOUT = 5 V, fixed 2.2 MHz trim, IOUT = 1 A 0.9 V DMAX Maximum switch duty cycle While in frequency foldback 98% FSW = 1.85 MHz, VOUT = 5.0 V, IOUT = 1 A 87% RFBPARA(min) Minimum value of the parallel feedback resistors: RFBT//RFBB 5 kΩ PROTECTION TSD(trip) Thermal shutdown temperature Shutdown temperature 158 168 186 °C TSD(hyst) Thermal shutdown temperature Recovery temperature 15 20 °C LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

7.7 Typical Characteristics

Unless otherwise specified, the following conditions apply: TA = 25°C, VIN = 13.5 V Temperature (°C) Shutdown Current (µA) -40 -10 20 50 80 110 140 0.2 0.3 0.4 0.5 0.6 0.7 VIN = 13.5V VIN = 24V VOUT = 3.3 V fixed Figure 7-1. Shutdown Current Versus Temperature Temperature (°C) Non-Switching Input Current (µA) -40 -10 20 50 80 110 140 1.2 1.4 1.6 1.8 VOUT = 3.3 V fixed Figure 7-2. Nonswitching Input Current (IQVIN(nonsw)) Versus Temperature Temperature (°C) Output Voltage (V) -40 -10 20 50 80 110 140 3.29 3.292 3.294 3.296 3.298 3.3 VOUT = 3.3 V fixed Figure 7-3. Output Voltage Accuracy Versus Temperature Temperature (°C) Voltage Reference Voltage (V) -40 -10 20 50 80 110 140 0.9975 0.998 0.9985 0.999 0.9995 VOUT = adjustable Figure 7-4. Feedback Voltage Accuracy Versus Temperature www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMQ66430-Q1

8 Detailed Description

8.1 Overview

The LMQ664x0-Q1 is a wide input, low-quiescent current, high-performance regulator that can operate over a wide range of duty ratio and the switching frequencies, including sub-AM band at 400 kHz and above AM band at 2.2 MHz. During wide input transients, if the minimum on time or the minimum off time cannot support the desired duty ratio at the higher switching frequency settings, the switching frequency is reduced automatically, allowing the device to maintain the output voltage regulation. With an internally compensated design optimized for minimal output capacitors, the system design process with the device is simplified significantly compared to other buck regulators available in the market. The device is designed to minimize external component cost and solution size while operating in all demanding automotive environments. The device family includes variants that can be set up to operate over a wide switching frequency range, from 200 kHz to 2.2 MHz, with the correct resistor selection from the RT pin to ground. To further reduce system cost, the PG output feature with built-in delayed release allows the elimination of the reset supervisor in many applications. The LMQ664x0-Q1 family is designed to reduce EMI/EMC emissions by introducing a dual random spread spectrum (DRSS) switching frequency dithering scheme, utilizing the enhanced QFN package where no bond wires are used and integrates the high-frequency VIN bypass capacitors including, a CBOOT capacitor, inside the package (LMQ variants). Also, available is the MODE/SYNC feature (select variants) that allows synchronization to an external clock. Together, these features eliminate the need for any common-mode choke or shielding or any elaborate input filter design scheme, greatly reducing the complexity and cost of the EMI/EMC mitigation measures. The device comes in an ultra-small 2.6-mm × 2.6-mm enhanced QFN package with wettable flanks, allowing for quick optical inspection along with specially designed corner anchor pins for reliable board level solder connections. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

8.2 Functional Block Diagram

/SYNC EN CONTROL LOGIC & DRIVER ENABLE PGND SW VIN LDO MAX. & MIN. LIMITS ERROR AMPLFIER + HS CURRENT SENSE SLOPE COMPENSATION VREF VCC HS CURRENT LMIT CLOCK FSW FOLDBACK MIN. LS CURRENT LIMIT THERMAL SHUTDOWN CLOCK COMP SOFT- START BANDGAP SYS ENABLE VCC UVLO VCC UVLO GND VIN FPWM or AUTO RT VOUT/ FB LS CURRENT LMIT SYS ENABLE TSD TSD TSD LS CURRENT SENSE VOUT UV/OV VOUT UV/OV RT VARIANTS ONLY MODE/SYNC VARIANTS ONLY ADJ. OUTPUT VOLTAGE FIXED OUTPUT VOLTAGE FIXED OUTPUT VOLTAGE ADJ. OUTPUT VOLTAGE FIXED OUTPUT VOLTAGE VOUT FB VOUT SYS ENABLE BOOT Figure 8-1. LMQ664x0-Q1 Functional Block Diagram www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMQ66430-Q1

8.3 Feature Description

8.3.1 Enable, Start-Up, and Shutdown

Voltage at the EN pin controls the start-up or remote shutdown of the LMQ664x0-Q1 family of devices. The part stays shut down as long as the EN pin voltage is less than V EN-WAKE = 0.5 V. During the shutdown, the input current drawn by the device typically drops down to 0.25 µA (V IN = 13.5 V). With the voltage at the EN pin greater than V EN-WAKE, the device enters device standby mode and the internal LDO powers up to generate VCC. As the EN voltage increases further, approaching V EN-VOUT, the device finally starts to switch, entering start-up mode with a soft start. During the device shutdown process, when the EN input voltage measures less than (V EN-VOUT–VEN-HYST), the regulator stops switching and re-enters device standby mode. Any further decrease in the EN pin voltage, below V EN-WAKE, and the device is then firmly shut down. The high-voltage compliant EN input pin can be connected directly to the V IN input pin if remote precision control is not needed. The EN input pin must not be allowed to float. The various EN threshold parameters and their values are listed in the Electrical Characteristics. Figure 8-3 shows the precision enable behavior and Figure 8-4 shows a typical remote EN start-up waveform in an application. Once EN goes high, after a delay of about 1 ms, the output voltage begins to rise with a soft start and reaches close to the final value in about 3.5 ms (t ss). After a delay of about 2.5 ms (t PG_ACT), the PG flag goes high. During start-up, the device is not allowed to enter FPWM mode component selection. RENT RENB EN AGND VIN Figure 8-2. VIN UVLO Using the EN Pin LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

3.3V VOUT VOUT VEN-WAKE VEN-HYST Figure 8-3. Precision Enable Behavior VOUT (2V/DIV) PG (5V/DIV) EN (5V/DIV) IL (1A/DIV) Figure 8-4. Enable Start-Up VIN = 24 V, VOUT = 3.3 V, IOUT = 2 A

8.3.2 External CLK SYNC (with MODE/SYNC)

Synchronized operation of multiple regulators in a single system is often desirable for a well-defined system level performance. The select variants in the device with the MODE/SYNC pin allow the power designer to synchronize the device to a common external clock. The device implements an in-phase locking scheme, where the rising edge of the clock signal, provided to the MODE/SYNC pin of the device, corresponds to the turning on of the high-side device. The external clock synchronization is implemented using a phase locked loop (PLL), eliminating any large glitches. The external clock fed into the device replaces the internal free-running clock, but does not affect any frequency foldback operation. Output voltage continues to be well regulated. The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided. www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMQ66430-Q1

The MODE/SYNC input pin in the device can operate in one of three selectable modes:

Auto mode: Pulse frequency modulation (PFM) operation is enabled during light load and diode emulation
FPWM mode: In FPWM mode, diode emulation is disabled, allowing current to flow backwards through the details.
SYNC mode: The internal clock locks to an external signal applied to the MODE/SYNC pin. As long as output voltage can be regulated at full frequency and is not limited by minimum off time or minimum on time, clock frequency is matched to the frequency of the signal applied to the MODE/SYNC pin. While the device is in SYNC mode, it operates as though in FPWM mode: diode emulation is disabled, allowing the frequency applied to the MODE/SYNC pin to be matched without a load.

8.3.2.1 Pulse-Dependent MODE/SYNC Pin Control

Most systems that require more than a single mode of operation from the device are controlled by digital circuitry such as a microprocessor. These systems can generate dynamic signals easily but have difficulty generating multi-level signals. Pulse-dependent MODE/SYNC pin control is useful with these systems. To initiate pulse-dependent MODE/SYNC pin control, a valid sync signal must be applied. Table 8-1 shows a summary of the pulse dependent mode selection settings. Table 8-1. Pulse-Dependent Mode Selection Settings Mode/Sync Input Mode > VMODE_H FPWM with spread spectrum factory setting < VMODE_L Auto mode with spread spectrum factory setting Synchronization Clock SYNC mode Figure 8-5 shows the transition between auto mode and FPWM mode while in pulse-dependent MODE/SYNC control. The device transitions to a new mode of operation after the time, t MODE. Figure 8-5 and Figure 8-6 show the details. Transition to new mode of operation starts, spread spectrum turns on FPWM Mode Auto Mode > tMODE VMODE_H VMODE_L Figure 8-5. Transition from Auto Mode and FPWM Mode If MODE/SYNC voltage remains constant longer than t MODE, the device enters either auto mode or FPWM mode with spread spectrum turned on (if factory setting is enabled) and MODE/SYNC continues to operate in pulse-dependent scheme. Now Auto Mode, Spread Spectrum on tMODE VMODE_H VMODE_L > tPULSE_L < tSYNC > tPULSE_H Figure 8-6. Transition from SYNC Mode to Auto Mode Now FPWM Mode, Spread Spectrum on tMODE VMODE_H VMODE_L > tPULSE_L < tSYNC > tPULSE_H < tSYNC > tPULSE_L Figure 8-7. Transition from SYNC Mode to FPWM Mode LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

8.3.3 Adjustable Switching Frequency (with RT)

The select variants in the device family with the RT pin allow the power designers to set any desired operating frequency between 200 kHz and 2.2 MHz in their applications. See Figure 8-8 to determine the resistor value needed for the desired switching frequency. The RT pin and the MODE/SYNC pin variants share the same pin location. The power supply designer can either use the RT pin variant and adjust the switching frequency of operation as warranted by the application or use the MODE/SYNC variant and synchronize to an external clock signal. See Table 8-2 for selection on programming the RT pin. Table 8-2. RT Pin Setting RT Input Switching Frequency VCC 1 MHz GND 2.2 MHz RT to GND Adjustable according to Figure 8-8 Float (not recommended) No switching Equation 1 can be used to calculate the value of RT for a desired frequency. RT = 18286 Fsw1.021 (1) where

RT is the frequency setting resistor value (kΩ).
FSW is the switching frequency. Switching Frequency (kHz) RT resistor (k:) 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 RTvs Figure 8-8. RT Values vs Frequency

8.3.4 Power-Good Output Operation

The power-good feature using the PG pin of the device can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output remains low under device fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for any short duration excursions in the output voltage, such as during line and load transients. Output voltage excursions lasting less than t RESET_FILTER do not trip the power-good flag. Power-good operation can best be understood in reference to Figure 8-9. Table 8-3 gives a more detailed breakdown of the PG operation. Here, V PGUV is defined as the PG UV scaled version of V OUT (target regulated output voltage) and V PGHYST as the PGHYST scaled version of V OUT, where both PG UV and PG HYST are listed in the Electrical Characteristics. During the initial power up, a total delay of 2.5 ms (typical) is encountered from the time V EN-VOUT is triggered to the time that the power good is flagged high. This delay only occurs during the device start-up and is not encountered during any other normal operation of the power-good function. When EN is pulled low, the power-good flag output is also forced low. With EN low, power good remains valid as long as the input voltage (VPG-VAL is greater 1.5 V (maximum)). www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMQ66430-Q1

The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup resistor connected to a suitable logic supply. It can also be pulled up to either V CC or V OUT through an appropriate resistor, as desired. If this function is not needed, the PG pin can be open or grounded. Limit the current into this pin to ≤ 4 mA. Input Voltage Input Voltage Output Voltage VPG-UV (falling) VPG-HYST VINMIN (rising) VPG_VAL GND VOUT VINMIN (falling) PG PG may not be valid if input is below VPG-VAL Startup delay tRESET_FILTER PG may not be valid if input is below VPG-VAL Small glitches do not reset tPG_ACT timer Small glitches do not cause reset to signal a fault tPG_ACT tRESET_FILTER tPG_ACT tRESET_FILTER tRESET_FILTER Figure 8-9. Power-Good Operation (OV Events Not Included) Table 8-3. Fault Conditions for PG (Pull Low) Fault Condition Initiated Fault Condition Ends (After Which tPG_ACT Must Pass Before PG Output Is Released) VOUT < VPGUV AND t > tRESET_FILTER Output voltage in regulation: VPGUV + VPGHYST < VOUT < VPGOV - VPGHYST VOUT > VPGOV AND t > tRESET_FILTER Output voltage in regulation TJ > TSD(trip) TJ < TSD(trip) - TSD(hyst) AND output voltage in regulation EN < VEN-VOUT – VEN-HYST EN > VEN-VOUT AND output voltage in regulation

8.3.5 Internal LDO, VCC, and VOUT/FB Input

The device uses the internal LDO output and the VCC pin for all internal power supply. The VCC pin draws power either from the VIN (in adjustable output variants) or VOUT/FB (in fixed-output variants). In the fixed- output variants, once the device is active but has yet to regulate, the VCC rail continues to draw power from the input voltage, V IN, until the VOUT/FB voltage reaches > 3.15 V (or when the device has reached steady-state regulation post the soft start). The VCC rail typically measures 3.3 V in both adjustable and fixed output variants. During start-up, VCC momentarily exceeds the normal operating voltage and then drops to the normal operating voltage.

8.3.6 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)

The high-side switch driver circuit requires a bias voltage higher than VIN to make sure the HS switch is turned on. The internal 0.1- μF capacitor that is connected between BOOT and SW works as a charge pump to boost voltage on the BOOT terminal to (SW + VCC). The boot diode is integrated on the device die to minimize physical solution size. The CBOOT rail has a UVLO setting. This UVLO has a threshold of V BOOT-UVLO and is typically set at 2.1 V. If the BOOT capacitor is not charged above this voltage with respect to the SW pin, then the part initiates a charging sequence, turning on the low-side switch before attempting to turn on the high-side device. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

8.3.7 Output Voltage Selection

In the device family, an adjustable output or fixed output voltage option is configurable for every device variant (see Section 5). For an adjustable output, the user needs an external resistor divider connection between the output voltage node, the device FB pin, and the system GND, as shown in Figure 8-10. The adjustable output adjust the output voltage. When using the fixed-output configuration from the device family, simply connect the FB pin (identified as VOUT/FB pin for fixed-output variants in the rest of the data sheet) to the system output voltage node. See Section 5 for more details. RFBT RFBB FB AGND VOUT Figure 8-10. Setting Output Voltage for Adjustable Output Variant In adjustable output voltage variants, an additional feedforward capacitor, C FF, in parallel with the R FBT, can be resistor divider or feedforward capacitor is needed in fixed-output variants.

8.3.8 Spread Spectrum

In the LMQ664x0-Q1 family of devices, spread spectrum is a factory option. To find which parts have spread spectrum enabled, see Section 5. Spread spectrum eliminates peak emissions at specific frequencies by spreading these peaks across a wider range of frequencies than a part with fixed-frequency operation. The LMQ664x0-Q1 implements a modulation pattern designed to reduce low frequency-conducted emissions from the first few harmonics of the switching frequency. The pattern can also help reduce the higher harmonics that are more difficult to filter, which can fall in the FM band. These harmonics often couple to the environment through electric fields around the switch node and inductor. The LMQ664x0-Q1 uses a spread of frequencies, which can spread energy smoothly across the FM and TV bands. The device implements dual random spread spectrum (DRSS). DRSS is a combination of a triangular frequency spreading pattern and pseudorandom frequency hopping. The combination allows the spread spectrum to be very effective at spreading the energy at the following:

Fundamental switching harmonic with slow triangular pattern
High frequency harmonics with additional pseudo-random jumps at the switching frequency The advantage of DRSS is its equivalent harmonic attenuation in the upper frequencies with a smaller fundamental frequency deviation. This reduces the amount of input current and output voltage ripple that is introduced at the modulating frequency. Additionally, the LMQ664x0-Q1 also allows the user to further reduce the output voltage ripple caused by the spread spectrum modulating pattern. The spread spectrum is only available while the clock of the device is free running at its natural frequency. Any of the following conditions overrides spread spectrum, turning it off:
The clock is slowed due to operation at low-input voltage – this is operation in dropout.
The clock is slowed under light load in auto mode. Note that if you are operating in FPWM mode, spread spectrum can be active, even if there is no load.
The clock is slowed due to high input to output voltage ratio. This mode of operation is expected if on time reaches minimum on time. See the Electrical Characteristics.
The clock is synchronized with an external clock. www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMQ66430-Q1

8.3.9 Soft Start and Recovery from Dropout

When designing with the LMQ664x0-Q1, slow rise in output voltage due to recovery from dropout and soft start must be considered as two separate operating conditions, as shown in Figure 8-11 and Figure 8-12. Soft start is triggered by any of the following conditions:

Power is applied to the VIN pin of the device, releasing undervoltage lockout.
EN is used to turn on the device.
Recovery from shutdown due to overtemperature protection Once soft start is triggered, the IC takes the following actions:
The reference used by the IC to regulate output voltage is slowly ramped up. The net result is that output voltage, if previously 0 V, takes tSS to reach 90% of the desired value.
Operating mode is set to auto mode of operation, activating the diode emulation mode for the low-side MOSFET. This allows start-up without pulling the output low. This is true even when there is a voltage already present at the output during a pre-bias start-up. VEN VOUT Set Point EN and Output Voltages Time t VOUT V 90% of VOUT Set Point 0 V tSS Triggering event If selected, FPWM is enabled only after completion of tSStEN VEN VOUT Set Point EN and Output Voltages Time t VOUT V 90% of VOUT Set Point 0 V tSS Triggering event tEN If selected, FPWM is enabled only after completion of tSS Figure 8-11. Soft Start with and Without Pre-bias Voltage

8.3.9.1 Recovery from Dropout

Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called graceful recovery from dropout in this document, differs from soft start in two important ways:

The reference voltage is set to approximately 1% above what is needed to achieve the existing output voltage.
If the device is set to FPWM, it will continue to operate in that mode during its recovery from dropout. If output voltage were to suddenly be pulled up by an external supply, the LMQ664x0-Q1 can pull down on the output. Note that all protections that are present during normal operation are in place, preventing any catastrophic failure if output is shorted to a high voltage or ground. Load current VOUT Set Point and max output current Output Voltage and Current Slope the same as during soft start Time t VOUT V Figure 8-12. Recovery from Dropout VOUT (2V/DIV) 500µs/DIV VIN (2V/DIV) Load Current (0.2A/DIV) Figure 8-13. Typical Output Recovery from Dropout from 8 V to 4 V Whether output voltage falls due to high load or low input voltage, once the condition that causes output to fall below its set point is removed, the output climbs at the same speed as during start-up. Figure 8-13 shows an example of this behavior. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

8.3.10 Current Limit and Short Circuit

The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both high-side and low-side MOSFETs. High-side MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is compared to either the minimum of a fixed current set point or the output of the internal error amplifier loop minus the slope compensation every switching cycle. Since the output of the internal error amplifier loop has a maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased duty factor if duty factor is typically above 35%. When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side device, the low-side device has a turn-off commanded by the internal error amplifier loop. In the case of the low-side device, turn-off is prevented if the current exceeds this value, even if the oscillator normally starts a new switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be. This is called the low-side current limit, IVALMAX in Figure 8-14. If the LS current limit is exceeded, the LS MOSFET stays on and the HS switch is not to be turned on. The LS switch is turned off once the LS current falls below this limit and the HS switch is turned on again as long as at least one clock period has passed since the last time the HS device has turned on. iL VSW IOUT Inductor Current t t SW Voltage VIN Typically, tSW > Clock setting tON < tON_MAX IPEAKMAX IVALMAX Figure 8-14. Current Limit Waveforms Since the current waveform assumes values between I PEAKMAX and I VALMAX, the maximum output current is very close to the average of these two values unless duty factor is very high. Once operating in current limit, hysteretic control is used and current does not increase as output voltage approaches zero. If duty factor is very high, current ripple must be very low in order to prevent instability. Since current ripple is low, the part is able to deliver full current. The current delivered is very close to IVALMAX. VOUT

0 Output Voltage

VIN > 2 * VOUT Setting VIN ~ VOUT Setting Figure 8-15. Output Voltage Versus Output Current Under most conditions, current is limited to the average of I PEAKMAX and I VALMAX, which is approximately 1.3 times the maximum rated current. If input voltage is low, current can be limited to approximately I VALMAX. Also note that the maximum output current does not exceed the average of I PEAKMAX and IVALMAX. Once the overload is removed, the part recovers as though in soft start. www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMQ66430-Q1

8.3.11 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to approximately 153°C (typical). When the junction temperature falls below 153°C (typical), the device attempts another soft start. While the device is shut down due to high junction temperature, power continues to be provided to VCC. To prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced current limit while the part is disabled due to high junction temperature. The LDO only provides a few milliamperes during thermal shutdown.

8.3.12 Input Supply Current

The device is designed to have very low input supply current when regulating light loads. This is achieved by powering much of the internal circuitry from the output. The VOUT/FB pin in the fixed-output voltage variants is the input to the LDO that powers the majority of the control circuits. By connecting the VOUT/FB input pin to the output node of the regulator, a small amount of current is drawn from the output. This current is reduced at the input by the ratio of VOUT / VIN. IQ_VIN = IQ + IEN + IBIAS ¾eff x V IN VOUT (2) where

IQVIN is the total standby (switching) current consumed by the operating (switching) buck converter when unloaded.
IQ is the current drawn from the VIN terminal.
IEN is current drawn by the EN terminal. Include this current if EN is connected to VIN. Check ILKG-EN in the Electrical Characteristics for IEN.
IBIAS is bias current drawn by the BIAS LDO.
ηeff is the light-load efficiency of the buck converter with IQ_VIN removed from the input current of the buck converter. ηeff = 0.8 is a conservative value that can be used under normal operating conditions. This can be traced back as the ISUPPLY in the System Characteristics.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.4 V, both the converter and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode, the quiescent current drops to typically 250 nA.

8.4.2 Standby Mode

The internal LDO has a lower EN threshold than the output of the converter. When the EN pin voltage is above 1 V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the VCC voltage at 3.3 V typical. The precision enable circuitry is ON once VCC is above its UVLO. The internal power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable threshold. The device also employs UVLO protection. If the VCC voltage is below its UVLO level, the output of the converter is turned off. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

8.4.3 Active Mode

The device is in active mode whenever the EN pin is above V EN-VOUT, VIN is high enough to satisfy V INMIN, and no other fault conditions are present. The simplest way to enable the operation is to connect the EN pin to V IN, which allows the device to start up when the applied input voltage exceeds the minimum VINMIN. In active mode, depending on the load current, input voltage, and output voltage, the device is in one of five modes:

Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the inductor current ripple
Auto mode – light load operation: PFM when switching frequency is decreased at very light load
FPWM mode – light load operation: Discontinuous conduction mode (DCM) when the load current is lower than half of the inductor current ripple
Minimum on time: At high input voltage and low output voltages, the switching frequency is reduced to maintain regulation.
Dropout mode: When switching frequency is reduced to minimize voltage dropout

8.4.3.1 CCM Mode

The following operating description of the device refers to Section 8.2 and to the waveforms in Figure 8-16 . In CCM, the device supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) switches with varying duty cycle (D). During the HS switch on time, the SW pin voltage, V SW, swings up to approximately V IN, and the inductor current, i L, increases with a linear slope. The HS switch is turned off by the control logic. During the HS switch off time, t OFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the V SW to swing below ground by the voltage drop across the LS switch. The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on time of the HS switch over the switching period: D = TON / TSW (3) In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN (4) iL VSW IPEAK IOUT Iripple Inductor Current - IOUT RDSON-LS D = t t SW Voltage tON tSWVIN tSW tON tOFF VOUT VIN Figure 8-16. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM) www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMQ66430-Q1

8.4.3.2 Auto Mode – Light Load Operation

The LMQ664x0-Q1 can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows for seamless transition between normal current mode operation while heavily loaded and highly efficient light load operation. The other behavior, called FPWM mode, maintains full frequency even when unloaded. Which mode the device operates in depends on which variant from this family is selected. Note that all parts operate in FPWM mode when synchronizing frequency to an external signal. The light load operation is employed in the device only in auto mode. The light load operation employs two techniques to improve efficiency:

Diode emulation, which allows DCM operation. See Figure 8-17.
Frequency reduction. See Figure 8-17. Note that while these two features operate together to improve light load efficiency, they operate independently.

8.4.3.2.1 Diode Emulation

Diode emulation prevents reverse current through the inductor, which requires a lower frequency needed to regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced. With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to maintain regulation. iL VSW IPEAK IOUT Inductor Current D = t t SW Voltage tON tSW VIN tSW tON tOFF tHIGHZ VOUT VIN In auto mode, the low-side device is turned off once SW node current is near zero. As a result, once output current is less than half of what inductor ripple would be in CCM, the part operates in DCM, which is equivalent to the statement that diode emulation is active. Figure 8-17. PFM Operation The device has a minimum peak inductor current setting (see I PEAKMIN in the Electrical Characteristics) while in auto mode. Once current is reduced to a low value with fixed input voltage, on time is constant. Regulation is then achieved by adjusting frequency. This mode of operation is called PFM mode regulation. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

8.4.3.2.2 Frequency Reduction

The device reduces frequency whenever output voltage is high. This function is enabled whenever the internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when the part is completely unloaded. 1% Above Set point VOUT Set Point Output Voltage Current Limit VOUT Output Current IOUT0 In auto mode, once output current drops below approximately 1/10th the rated current of the part, output resistance increases so that output voltage is 1% high while the buck is completely unloaded. Figure 8-18. Steady State Output Voltage Versus Output Current in Auto Mode In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a dummy load at VOUT or FPWM mode can be used to reduce or eliminate this offset.

8.4.3.3 FPWM Mode – Light Load Operation

In FPWM mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see the Electrical Characteristics for reverse current limit values. iL VSW IPEAK IOUT Iripple Inductor Current D = t t SW Voltage tON tSW VIN tSW tON tOFF VOUT VIN In FPWM mode, continuous conduction (CCM) is possible even if IOUT is less than half of Iripple. Figure 8-19. FPWM Mode Operation For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to command minimum on time even while lightly loaded, allowing good behavior during faults that involve output being pulled up. www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMQ66430-Q1

8.4.3.4 Minimum On-Time (High Input Voltage) Operation

The device continues to regulate output voltage even if the input-to-output voltage ratio requires an on time less than the minimum on time of the chip with a given clock setting. This is accomplished by using valley current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a maximum valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until valley current falls below that determined by the compensation circuit. If the converter is not operating in current limit, the maximum valley current is set above the peak inductor current, preventing valley control from being used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high, such that the inductor current peak value exceeds the peak command dictated by compensation, the high-side device cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit reduces both peak and valley current. Once a low enough current is selected by the compensation circuit, valley current matches that being commanded by the compensation circuit. Under these conditions, the low-side device is kept on and the next clock cycle is prevented from starting until inductor current drops below the desired valley current. Since the on time is fixed at its minimum value, this type of operation resembles that of a device using a constant on-time (COT) control scheme; see Figure 8-20. iL VSW IVAL IOUT Iripple Inductor Current - IOUT RDSON-LS D = t t SW Voltage tON tSWVIN tSW > Clock setting tON = tON_MIN tOFF VOUT VIN In valley control mode, minimum inductor current is regulated, not peak inductor current. Figure 8-20. Valley Current Mode Operation LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

8.4.3.5 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the required duty cycle. At a given clock frequency the duty cycle is limited by minimum off time. Once this limit is reached, as shown in Figure 8-22, and the clock frequency was to be maintained, the output voltage would fall. Instead of allowing the output voltage to drop, the device extends the high-side switch on time past the end of the clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle once peak inductor current is achieved or once a pre-determined maximum on time, t ON-MAX, of approximately 9 µs passes. As a result, once the needed duty cycle cannot be achieved at the selected clock frequency due to the existence of a minimum off time, frequency drops to maintain regulation. As shown in Figure 8-21, if input voltage is low enough so that output voltage cannot be regulated even with an on time of t ON-MAX, output voltage drops to slightly below the input voltage by V DROP1. For additional information on recovery from dropout, refer to Figure 8-12. VOUT Output Setting Output Voltage VIN0 Input Voltage FSW Switching Frequency VIN0 Input Voltage Input Voltage ~110kHz VDROP1 Output Voltage FSW-NOM Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz, input voltage tracks output voltage. Figure 8-21. Frequency and Output Voltage in Dropout iL VSW IOUT Iripple Inductor Current - IOUT RDSON-LS D = t t SW Voltage tON tSWVIN tSW > Clock setting tOFF = tOFF_MIN tON < tON_MAX VOUT VIN IPEAK Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result, frequency drops. This frequency drop is limited by tON-MAX. Figure 8-22. Dropout Waveforms www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMQ66430-Q1

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The LMQ664x0-Q1 step-down DC-to-DC converters are typically used to convert a higher DC voltage to a lower DC voltage. The LMQ66430-Q1 supports a maximum output current of 3 A while the LMQ66420-Q1 and LMQ66410-Q1 support a maximum output current of 2 A and 1 A, respectively. The following design procedure can be used to select components for the LMQ66430-Q1. The design procedure can also be used to select components for the LMQ66420-Q1 or LMQ66410-Q1 by limiting the maximum output current to 2 A or 1 A, respectively. Note All of the capacitance values given in the following application information refer to effective values unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective capacitance up to the required value. This can also ease the RMS current requirements on a single capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to ensure that the minimum value of effective capacitance is provided. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

9.2 Typical Application

Figure 9-1 shows a typical application circuit for the LMQ664x0-Q1. This device is designed to function over a wide range of external components and system parameters. However, the internal compensation is optimized for a certain range of external inductance and output capacitance. As a quick-start guide, Table 9-1 and Table 9-2 provide typical component values for a range of the most common output voltages. VIN EN VCC SW BOOT VOUT / FB VIN VOUT L COUT CIN CVCC 4.7 µF 1 µF MODE/ SYNC RFBT RFBBGND PG Figure 9-1. Example Application Circuit Table 9-1. Typical External Component Values for Adjustable Output LMQ66430-Q1 ƒSW (kHz)(1) VOUT (V) L (µH) Nominal COUT (Rated Capacitance) RFBT (kΩ)(2) RFBB (kΩ) CIN CBOOT CVCC 400 3.3 10 3 × 22 µF 33.2 14.3 4.7 µF DNP 1 µF 400 5 10 3 × 22 µF 49.9 12.4 4.7 µF DNP 1 µF 2200 5 2.2 2 × 22 µF 49.9 12.4 4.7 µF DNP 1 µF (1) Inductor values are calculated based on typical VIN = 12 V. Table 9-2. Typical External Component Values for Fixed Output LMQ66430-Q1 ƒSW (kHz)(1) VOUT (V) L (µH) Nominal COUT (Rated Capacitance) RFBT (Ω) RFBB (Ω)(2) CIN CBOOT CVCC 400 3.3 10 3 × 22 µF 0 DNP 4.7 µF DNP 1 µF 2200 3.3 2.2 2 × 22 µF 0 DNP 4.7 µF DNP 1 µF 400 5 10 3 × 22 µF 0 DNP 4.7 µF DNP 1 µF 2200 5 2.2 2 × 22 µF 0 DNP 4.7 µF DNP 1 µF (1) Inductor values are calculated based on typical VIN = 13.5 V. (2) DNP = Do Not Populate

9.2.1 Design Requirements

Section 9.2.2 provides a detailed design procedure based on Table 9-3. Table 9-3. Detailed Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 12 V (4 V to 36 V) Output voltage 3.3 V Maximum output current 0 A to 3 A Switching frequency 2.2 MHz www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMQ66430-Q1

9.2.2 Detailed Design Procedure

The following design procedure applies to Figure 9-1 and Table 9-2.

9.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size. Lower switching frequency implies reduced switching losses and usually results in higher system efficiency. However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more compact design. For this example, 2200 kHz is used.

9.2.2.2 Setting the Output Voltage

VOUT / FB of the device can be either connected directly to the output capacitor or a midpoint of a feedback resistor divider. When connected directly to the output capacitor, the device assumes that a fixed output voltage of either 3.3 V or 5 V is desired. The 3.3-V or 5-V fixed output options are factory trimmed and it is unique to a specific device. See Section 5 for the selection of fixed output voltage versions.

9.2.2.2.1 VOUT / FB for Adjustable Output

If other voltages are desired, VOUT / FB can be connected to a feedback resistor divider network to set the output voltage. The divider network is comprised of RFBT and RFBB, and closes the loop between the output voltage and the converter. The converter regulates the output voltage by holding the voltage on the V OUT / FB pin equal to the internal reference voltage, VREF. The converter determines whether fixed output voltage or adjustable output voltage is required by sensing the resistance of the feedback path during start-up. To ensure that the converter regulates to the desired output voltage, the typical minimum value for the parallel combination of R FBT and RFBB is 5 kΩ while the typical maximum value is 10 k Ω as shown in Equation 5. Equation 6 can be used as a starting point to determine the value of R FBT. Reference Table 9-4 for a list of acceptable resistor values for various output voltages. 5 k Ω < R FB T R F BB ≤ 10 k Ω (5) R FB T ≤ 10 k Ω* V OU T

1 V (6)

Table 9-4. Recommended Feedback Resistor Values for Various Output Voltages VOUT (V) RFBT (kΩ)(1) RFBB (kΩ) 2.5 24.9 16.5 3.3 33.2 14.3 5 49.9 12.4 6 60.4 12.1 9 90.9 11.3 (1) RFBT and RFBB based on 1% standard resistor values. For this 3.3-V example, the user can choose the LMQ66430MC3RXBRQ1 and connect VOUT / FB directly to the output capacitor.

9.2.2.3 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum output current. Note that when selecting the ripple current for applications with much smaller maximum load than the maximum available from the device, use the maximum device current. Equation 7 can be used to determine the value of inductance. The constant K is the percentage of inductor current ripple. For IN OUT maxOUTSW OUTIN V V I Kf VVL (7) LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, IPEAKMAX (see the Electrical Characteristics). This makes sure that the inductor does not saturate, even during a short circuit on the output. When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly. Although the valley current limit, I VALMAX, is designed to reduce the risk of current runaway, a saturated inductor can cause the current to rise to high values very rapidly. This can lead to component damage. Do not allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some relaxation in the current rating of the inductor. However, they have more core losses at frequencies above about 1 MHz. In any case, the inductor saturation current must not be less than the maximum peak inductor current at full load. The maximum inductance is limited by the minimum current ripple for the current mode control to perform correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device maximum rated current under nominal conditions.

9.2.2.4 Output Capacitor Selection

The current mode control scheme of the LMQ664x0-Q1 devices allows operation over a wide range of output capacitance. The output capacitor bank is usually limited by the load transient requirements and stability rather than the output voltage ripple. Refer to Table 9-1 for typical output capacitor values for 3.3-V and 5-V output voltages. Based on Table 9-1, for a 3.3-V output design, the user can choose the recommended 2 × 22-µF ceramic output capacitor for this example. For other designs with other output voltages, WEBENCH can be used as a starting point for selecting the value of output capacitor. In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic capacitor placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1 nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics. Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed.

9.2.2.5 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum ceramic capacitance of 4.7 µF is required on the input of the LMQ664x0-Q1. This must be rated for at least the maximum input voltage that the application requires, preferably twice the maximum input voltage. This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. For this example, a 4.7-µF, 50-V, X7R (or better) ceramic capacitor is chosen. It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramic capacitor. This is especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance. Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate RMS value of this current can be calculated from Equation 8 and must be checked against the manufacturers' maximum ratings. II OUT RMS # (8) www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMQ66430-Q1

9.2.2.6 CBOOT

The LMQ664x0-Q1 has an integrated bootstrap 0.1- μF capacitor connected internally between the BOOT pin and the SW pin. This capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. If needed, an additional high-quality ceramic capacitor can be added externally.

9.2.2.7 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the power-good function (see Section 8.3.4). A value in the range of 10 k Ω to 100 k Ω is a good choice in this case. The nominal output voltage on VCC is 3.3 V; see the Electrical Characteristics for limits.

9.2.2.8 CFF Selection

In some cases, a feedforward capacitor can be used across R FBT to improve the load transient response or improve the loop-phase margin. The Optimizing Transient Response of Internally Compensated DC-DC Converters with Feedforward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.

9.2.2.9 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This can be accomplished by using the circuit shown in Figure 9-2 . The input voltage at which the device turns on is designated as VON while the turn-off voltage is V OFF. First, a value for R ENB is chosen in the range of 10 k Ω to 100 kΩ, then Equation 9 and Equation 10 are used to calculate RENT and VOFF, respectively. EN RENT RENB VIN Figure 9-2. Setup for External UVLO Application R EN T = V O N V EN − VO U T − 1 * R E NB (9) V O FF = V ON * 1 − V EN − HY S V EN − V OU T (10) where

VON is the VIN turn-on voltage.
VOFF is the VIN turn-off voltage. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMQ66430-Q1

9.2.2.10 Maximum Ambient Temperature

As with any power conversion device, the LMQ664x0-Q1 dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance, RθJA, of the device, and PCB combination. The maximum junction temperature for the LMQ664x0-Q1 must be limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load current. Equation 11 shows the relationships between the important parameters. It is easy to see that larger ambient temperatures (T A) and larger values of R θJA reduce the maximum available output current. The converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions cannot be found in one of the curves, interpolation can be used to estimate the efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly. The correct value of R θJA is more difficult to estimate. For more information, refer to the Semiconductor and IC Package Thermal Metrics Application Report. OUTJA AJ MAXOUT V TTI K T (11) where

η is the efficiency. The effective RθJA is a critical parameter and depends on many factors such as the following:
Power dissipation
Air temperature/flow
PCB area
Copper heat-sink area
Number of thermal vias under the package
Adjacent component placement The IC junction temperature can be estimated for a given operating condition using Equation 12. T J ≈ T A + R θ J A * I C Pow er L os s (12) where
TJ is the IC junction temperature (°C).
TA is the ambient temperature (°C).
RθJA is the thermal resistance (°C/W).
IC power loss is the power loss for the IC (W). The IC power loss mentioned above is the overall power loss minus the loss that comes from the inductor DC resistance. The overall power loss can be approximated by using WEBENCH for a specific operating condition and temperature. Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given application environment:
Thermal Design by Insight not Hindsight Application Report
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
Semiconductor and IC Package Thermal Metrics Application Report
Thermal Design Made Simple with LM43603 and LM43602 Application Report
PowerPAD™ Thermally Enhanced Package Application Report
PowerPAD™ Made Easy Application Report
Using New Thermal Metrics Application Report
PCB Thermal Calculator www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LMQ66430-Q1

9.2.3 Application Curves

Unless otherwise specified, the following conditions apply: VIN = 12 V, TA = 25°C Output Current (A) Efficiency (%) 100 VIN = 12 V VIN = 18 V VIN = 24 V LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (Auto) Fixed Figure 9-3. Efficiency Output Current (A) Efficiency (%) 100 VIN = 12 V VIN = 18 V VIN = 24 V LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (FPWM) Fixed Figure 9-4. Efficiency Input Voltage (V) Output Voltage (V) 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.1 3.2 3.3 3.4 IOUT = 0.5 A IOUT = 1 A IOUT = 1.5 A IOUT = 2 A LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (Auto) Fixed Figure 9-5. Dropout Load Current (A) Output Voltage (V) 3.2925 3.294 3.2955 3.297 3.2985 3.3 3.3015 3.303 3.3045 3.306 VIN = 12 V VIN = 18 V VIN = 24 V LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (Auto) Fixed Figure 9-6. Line and Load Regulation Input Voltage (V) Input Current (µA) 0 5 10 15 20 25 30 35 40 0.5 1.5 2.5 3.5 4.5 LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (Auto) Fixed Figure 9-7. Input Switching Current vs Input Voltage Load Current (A) Input Current (A) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VIN = 12 V VIN = 18 V VIN = 24 V LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (Auto) Fixed Figure 9-8. Input Current vs Load Current LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMQ66430-Q1

VOUT (200mV/DIV) IOUT (1A/DIV) 100 µs/DIV LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (Auto)

0 A to 2 A,1 A / µs Fixed

Figure 9-9. Load Transient VOUT (200mV/DIV) IOUT (1A/DIV) 100 µs/DIV LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (Auto) 0.5 A to 1.5 A,1 A / µs Fixed Figure 9-10. Load Transient VOUT (200mV/DIV) IOUT (1A/DIV) 100 µs/DIV LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (FPWM)

0 A to 1 A,1 A / µs Fixed

Figure 9-11. Load Transient VOUT (200mV/DIV) IOUT (1A/DIV) 100 µs/DIV LMQ66430MC3 VOUT = 3.3 V 2.2 MHz (Auto) Figure 9-12. Load Transient VOUT (20mV/DIV) 1 µs/DIV LMQ66430MC3 VOUT = 3.3 V 2 A Load Fixed Figure 9-13. Output Voltage Ripple VOUT (50mV/DIV) 100 ms/DIV LMQ66430MC3 VOUT = 3.3 V No Load Fixed Figure 9-14. Output Voltage Ripple www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LMQ66430-Q1

LMQ66430MC3 VOUT = 3.3 V 12 VIN, 2 A, 2.2 MHz Fixed Figure 9-15. EVM Thermal Performance LMQ66430MC3 VOUT = 3.3 V 12 VIN, 3 A, 2.2 MHz Fixed Figure 9-16. EVM Thermal Performance VIN = 12.5 V VOUT = 3.3 V Fsw = 2.2 MHz Load = 2.2 A Figure 9-17. Typical CISPR 25 Conducted EMI 150 kHz–200 MHz Yellow: Peak Detect, Green: Average Detect LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMQ66430-Q1

9.3 What to Do and What Not to Do

Do not exceed the Absolute Maximum Ratings.
Do not exceed the Recommended Operating Conditions.
Do not exceed the ESD Ratings.
Do not allow the EN input to float.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
Follow all the guidelines and suggestions found in this data sheet before committing the design to production. TI application engineers are ready to help critique your design and PCB layout to help make your project a success.

10 Power Supply Recommendations

The characteristics of the input supply must be compatible with the Specifications found in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded regulator. The average input current can be estimated with Equation 13. K IN OUTOUT IN V IVI (13) where

η is the efficiency. If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily shut down and reset. The best way to solve these kinds of issues is to limit the distance from the input supply to the regulator or plan to use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors help dampen the input resonant circuit and reduce any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to hold the input voltage steady during large load transients. Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple Success With Conducted EMI From DC/DC Converters User's Guide provides helpful suggestions when designing an input filter for any switching regulator. In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the output voltage of the regulator, the output capacitors discharge through the device back to the input. This uncontrolled current flow can damage the device. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMQ66430-Q1

11 Layout

11.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground, as shown in Figure 11-1. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Figure 11-2 shows a recommended layout for the critical components of the LMQ664x0-Q1.

Place the input capacitors as close as possible to the VIN and GND terminals.
Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and routed with short, wide traces to the VCC and GND pins.
If an external CBOOT capacitor is desired: Place CBOOT close to the device with short/wide traces to the BOOT and SW pins.
Place the feedback divider as close as possible to the VOUT / FB pin of the device. Place RFBB, RFBT, and CFF, if used, physically close to the device. The connections to VOUT / FB and GND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, the latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator.
Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat dissipation path.
Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
Provide enough PCB area for proper heat-sinking. As stated in Section 9.2.2.10, enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. The top and bottom PCB layers must be made with two-ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer heat-spreading ground planes.
Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI. See the following PCB layout resources for additional important guidelines:
Layout Guidelines for Switching Power Supplies Application Report
Simple Switcher PCB Layout Guidelines Application Report
Construction Your Power Supply- Layout Considerations Seminar
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LMQ66430-Q1

Figure 11-1. Current Loops with Fast Edges

11.1.1 Ground and Thermal Considerations

As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the ground plane contains much less noise; use for sensitive routes. TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See Figure 11-2 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding, and lower thermal resistance. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMQ66430-Q1

11.2 Layout Example

Figure 11-2. Example Layout www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LMQ66430-Q1

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Device Nomenclature

Figure 12-1 shows the device naming nomenclature of the LMQ664x0-Q1. See Section 5 for the availability of each variant. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options; minimum order quantities apply. MODE M: Mode/SYNC Trim R: RT Trim PACKAGE RXBR = WQFN 15-pin large reel RXBT = WQFN 15-pin tape VOUT OPTION 3: 3.3 V Fixed 5: 5 V Fixed *Both variants can be setup for ADJ voltage output LM X 664 X 0 X X X RXBX – Q1 TRIM OPTION *No character defaults to: RT – Auto A: 400 kHz Fixed Frequency B: 1 MHz Fixed Frequency C: 2 MHz Fixed Frequency F: RT – FPWM AUTOOUTPUT CURRENT MAX 1: 1 A 2: 2 A 3: 3 A CAPACITOR INTEGRATION Q: With Internal Capacitors R: Without Internal Capacitors Figure 12-1. Device Naming Nomenclature

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, Thermal Design by Insight not Hindsight Application Report
Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report
Texas Instruments, PowerPAD™ Thermally Enhanced Package Application Report
Texas Instruments, PowerPAD™ Made Easy Application Report
Texas Instruments, Using New Thermal Metrics Application Report
Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report
Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar
Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMQ66430-Q1

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LMQ66430-Q1

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMQ66430-Q1

www.ti.com PACKAGE OUTLINE C 2.7 2.5 2.7 2.5 1.05 0.95 0.01 0.00 2X 1 10X 0.5 2X 1.5 10X 0.6 0.4 18X 0.3 0.2 1 0.1

0.1 MIN

(0.1) 4X 0.525 4X 0.775 0.575 VQFN-FCRLF - 1.05 mm max heightRXB0014A PLASTIC QUAD FLATPACK - NO LEAD 4225574/C 02/2021 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMMEXPOSED THERMAL PAD SYMM 6 7 SCALE 4.000 A-A 30.000 SECTION A-A TYPICAL AB www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LMQ66430-Q1

www.ti.com EXAMPLE BOARD LAYOUT 10X (0.5) (R0.05) TYP

0.05 MAX

0.05 MIN

10X (0.7) (2.3) (2.3) ( 1) ( 0.2) TYP VIA 4X (0.6) 18X (0.25) 4X (0.875) 4X (0.525) VQFN-FCRLF - 1.05 mm max heightRXB0014A PLASTIC QUAD FLATPACK - NO LEAD 4225574/C 02/2021 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be ﬁlled, plugged or tented. SYMM SYMM SEE SOLDER MASK DETAIL EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE: 30X 6 7 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMQ66430-Q1

www.ti.com EXAMPLE STENCIL DESIGN 10X (0.7) 10X (0.5) (2.3) (2.3) 1X ( 0.95) (R0.05) TYP 18X (0.25) 4X (0.875) 4X (0.6) 4X (0.525) VQFN-FCRLF - 1.05 mm max heightRXB0014A PLASTIC QUAD FLATPACK - NO LEAD 4225574/C 02/2021 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 30X EXPOSED PAD 15 90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 6 7 www.ti.com LMQ66430-Q1 SNVSBV1 – FEBRUARY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: LMQ66430-Q1

www.ti.com 19-Feb-2022 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMQ66430MC3RXBRQ1 ACTIVE VQFN-FCRLF RXB 14 3000 TBD Call TI Call TI -40 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMQ66430-Q1 :

www.ti.com 19-Feb-2022 Addendum-Page 2

Catalog : LMQ66430 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated

Product Information

LMQ66420MC3RXBRQ1 specifications and overview.

Summary

LMQ664x0-Q1, 36-V, 1-A, 2-A, and 3-A Ultra-Small Synchronous Automotive Step-Down Converter with Integrated VIN Bypass and CBOOT Capacitors FEBRUARY 2022

Description

LMQ664x0-Q1, 36-V, 1-A, 2-A, and 3-A Ultra-Small Synchronous Automotive Step-Down Converter with Integrated VIN Bypass and CBOOT Capacitors FEBRUARY 2022

Source title LMQ66420MC3RXBRQ1 Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer