LMK60XX High-Performance Low Jitter Oscillator datasheet (Rev. C)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNAS687,C]
- PDF pages: 18
Technical content
Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 LMK60XXHigh-PerformanceLowJitterOscillator
1 Features
1• Low Noise, High Performance – Jitter: 150 fs RMS typical Fout > 100 MHz – PSRR: –60 dBc, Robust Supply Noise Immunity
- Supported Output Format – LVPECL and LVDS up to 800 MHz – HCSL up to 400 MHz
- Total Frequency Tolerance of ±50 ppm (LMK60X2) and ±25 ppm (LMK60X0)
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7-mm × 5-mm 6-pin Package That is Pin- Compatible With Industry Standard 7050 XO Package
2 Applications
- High-Performance Replacement for Crystal-, SAW-, or Silicon-based Oscillators
- Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
- Test and Measurement
- Medical Imaging
- FPGA, Processor Attach
3 Description
The LMK60XX device is a low jitter oscillator that generates a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL, and LVDS up to 800 MHz, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ±5% supply. Device Information(1) PART NUMBER OUTPUT FREQ (MHz) AND FORMAT TOTAL FREQ STABILITY (ppm) PACKAGE / SIZE LMK60E2- 150M 150 LVPECL ±50 6-pin QFM, 7 mm × 5 mm LMK60E0- 156257 156.257 LVPECL ±25 LMK60A0- 148351 148 + 32/91 LVDS ±25 LMK60A0- 148M 148.5 LVDS ±25 (1) For all available packages, see the orderable addendum at the end of the data sheet. Pinout
LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 www.ti.com Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Table of Contents
10.2 Receiving Notification of Documentation Updates 12
11 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision B (December 2016) to Revision C Page Changes from Revision A (August 2016) to Revision B Page Changes from Original (June 2016) to Revision A Page
LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M www.ti.com SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated
5 Pin Configuration and Functions
NAME NO. POWER GND 3 Ground Device ground VDD 6 Analog 3.3-V power supply OUTPUT BLOCK OUTP, OUTN 4, 5 Universal Differential output pair (LVPECL, LVDS or HCSL). DIGITAL CONTROL / INTERFACES NC 2 N/A No connect OE 1 LVCMOS Output enable (internal pullup). When set to low, output pair is disabled and set at high impedance. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Device supply voltage –0.3 3.6 V VIN Output voltage for logic inputs –0.3 VDD + 0.3 V VOUT Output voltage for clock outputs –0.3 VDD + 0.3 V TJ Junction temperature 150 °C TSTG Storage temperature –40 125 °C (1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 www.ti.com Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Device supply voltage 3.135 3.3 3.465 V TA Ambient temperature –40 25 85 °C TJ Junction temperature 120 °C tRAMP VDD power-up ramp time 0.1 100 ms (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The package thermal resistance is calculated on a 4 layer JEDEC board. (3) Connected to GND with 3 thermal vias (0.3-mm diameter). (4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. See the Layout Guidelines section for more information on ensuring good system reliability and quality.
6.4 Thermal Information
THERMAL METRIC(1) LMK60XX (2) (3) (4) UNIT SIA (QFM)
6 PINS
Airflow (LFM) 0 Airflow (LFM) 200 Airflow (LFM) 400 RθJA Junction-to-ambient thermal resistance 55.2 46.4 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 34.6 n/a n/a °C/W RθJB Junction-to-board thermal resistance 37.7 n/a n/a °C/W ψJT Junction-to-top characterization parameter 11.3 17.6 22.5 °C/W ψJB Junction-to-board characterization parameter 37.7 41.5 40.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W (1) Refer to Parameter Measurement Information for relevant test conditions. (2) On-chip power dissipation should exclude 40 mW, dissipated in the 150 Ω termination resistors, from total power dissipation.
6.5 Electrical Characteristics - Power Supply(1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD Device current consumption LVPECL(2) 162 208 mALVDS 152 196 HCSL 155 196 IDD-PD Device current consumption when output is disabled OE = GND 136 mA (1) Refer to Parameter Measurement Information for relevant test conditions. (2) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec. (3) Ensured by characterization.
6.6 LVPECL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT Output frequency(2) 10 800 MHz VOD Output voltage swing (VOH – VOL)(2) 700 800 1200 mV VOUT, DIFF, PP Differential output peak-to-peak swing 2 × |VOD| V VOS Output common-mode voltage VDD – 1.55 V tR / tF Output rise/fall time (20% to 80%)(3) 150 250 ps ODC Output duty cycle(3) 45% 55%
LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M www.ti.com SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec. (2) Ensured by characterization.
6.7 LVDS Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT Output frequency(1) 10 800 MHz VOD Output voltage swing (VOH - VOL)(1) 300 390 480 mV VOUT, DIFF, PP Differential output peak-to-peak swing 2 × |VOD| V VOS Output common-mode voltage 1.2 V tR / tF Output rise/fall time (20% to 80%)(2) 150 250 ps ODC Output duty cycle(2) 45% 55% ROUT Differential output impedance 125 Ω (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential zero crossing. (3) Ensured by design. (4) Ensured by characterization.
6.8 HCSL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT Output frequency 10 400 MHz VOH Output high voltage 600 850 mV VOL Output low voltage –100 100 mV VCROSS-DELTA Variation of VCROSS (2)(3) 0 140 mV dV/dt Slew rate(4) 0.8 2 V/ns ODC Output duty cycle(4) 45% 55%
6.9 OE Input Characteristics
VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Input high voltage 1.4 V VIL Input low voltage 0.6 V IIH Input high current VIH = VDD –40 40 µA IIL Input low current VIL = GND –40 40 µA CIN Input capacitance 2 pF (1) Ensured by characterization.
6.10 Frequency Tolerance Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fT Total frequency tolerance LMK60X2: All output formats, frequency bands and device junction temperature up to 125°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (10 years) –50 50 ppm LMK60X0: All output formats, frequency bands and device junction temperature up to 115°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (5 years at 40°C) –25 25 ppm
LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 www.ti.com Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (1) Ensured by characterization. (2) Ensured by design.
6.11 Power-On/Reset Characteristics (VDD)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VTHRESH Threshold voltage(1) 2.72 2.95 V VDROOP Allowable voltage droop(2) 0.1 V tSTARTUP Start-up time (1) Time elapsed from VDD at 3.135 V to output enabled 10 ms tOE-EN Output enable time(2) Time elapsed from OE at VIH to output enabled 50 µs tOE-DIS Output disable time(2) Time elapsed from OE at VIL to output disabled 50 µs (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin (3) DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.
6.12 PSRR Characteristics(1)
VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR Spurs induced by 50-mV power supply ripple(2)(3) at 156.25-MHz output, all output types Sine wave at 50 kHz –60 dBc Sine wave at 100 kHz –60 Sine wave at 500 kHz –60 Sine wave at 1 MHz –60 (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer). (3) Ensured by characterization.
6.13 PLL Clock Output Jitter Characteristics(1)(2)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RJ RMS phase jitter(3) (12 kHz – 20 MHz) fOUT ≥ 100 MHz, All output types 150 250 fs RMS
6.14 Additional Reliability and Qualification
PARAMETER CONDITION / TEST METHOD Mechanical Shock MIL-STD-202, Method 213 Mechanical Vibration MIL-STD-202, Method 204 Moisture Sensitivity Level J-STD-020, MSL3
6.15 Typical Characteristics
Figure 1. LVPECL Differential Output Swing vs Frequency Figure 2. LVDS Differential Output Swing vs Frequency Figure 3. HCSL Differential Output Swing vs Frequency
7 Parameter Measurement Information
7.1 Device Output Configurations
Figure 4. LVPECL Output DC Configuration During Device Test Figure 5. LVDS Output DC Configuration During Device Test Figure 6. HCSL Output DC Configuration During Device Test Figure 7. LVPECL Output AC Configuration During Device Test Figure 8. LVDS Output AC Configuration During Device Test
LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 www.ti.com Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated
8 Power Supply Recommendations
For best electrical performance of LMK60XX, TI recommends using a combination of 10 µF, 1 µF and 0.1 µF on its power supply bypass network. TI also recommends using component side mounting of the power supply bypass capacitors, and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low impedance connection to the ground plane. Figure 12 shows the layout recommendation for power supply decoupling of LMK60XX.
9 Layout
9.1 Layout Guidelines
The following sections provides recommendations for board layout, solder reflow profile and power supply bypassing when using LMK60XX to ensure good thermal / electrical performance and overall signal integrity of entire system.
9.1.1 Ensuring Thermal Reliability
The LMK60XX is a high performance device. Therefore pay careful attention to device configuration and printed- circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to the ground plane of the PCB through three vias or more, as shown in Figure 12, to maximize thermal dissipation out of the package. Equation 1 describes the relationship between the PCB temperature around the LMK60XX and its junction temperature. TB = TJ – ΨJB * P where
- TB: PCB temperature around the LMK60XX
- TJ: Junction temperature of LMK60XX
- ΨJB: Junction-to-board thermal resistance parameter of LMK60XX (37.7°C/W without airflow)
- P: On-chip power dissipation of LMK60XX (1) To ensure that the maximum junction temperature of LMK60XX is below 120°C, it can be calculated that the maximum PCB temperature without airflow should be at 90°C or below when the device is optimized for best performance resulting in maximum on-chip power dissipation of 0.68 W.
9.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK60XX, TI recommends routing vias into decoupling capacitors and then into the LMK60XX. TI also recommends increasing the via count and width of the traces wherever possible. These steps ensure lowest impedance and shortest path for high-frequency current flow. Figure 12 shows the layout recommendation for LMK60XX.
Figure 12. LMK60XX Layout Recommendation for Power Supply and Ground
9.1.3 Recommended Solder Reflow Profile
recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.
10 Device and Documentation Support
10.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 1. Related Links
10.2 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
10.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
10.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
10.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C 5.08 2.54 6X (0.15) 6X 1.03 0.97
1.15 MAX
6X 1.43 1.37 3X 3.7 A 5.1 4.9 B 7.1 6.9 4X (0.26) QFM - 1.15 mm max heightSIA0006A QUAD FLAT MODULE 4222361/B 10/2015 PIN 1 INDEX AREA 0.1 C
0.1 C A B
0.05 C 3 4 SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 2.200 LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M www.ti.com SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated
www.ti.com EXAMPLE BOARD LAYOUT 6X (1)
0.07 MIN
6X (1.4) (3.7) 4X (2.54) (R ) TYP0.05 QFM - 1.15 mm max heightSIA0006A QUAD FLAT MODULE 4222361/B 10/2015 SYMM SYMM 3 4 1:1 RATIO WITH PACKAGE SOLDER PADS LAND PATTERN EXAMPLE SCALE:8X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED NOT TO SCALE SOLDER MASK DETAILS METAL UNDER SOLDER MASK SOLDER MASK OPENING SOLDER MASK DEFINED LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 www.ti.com Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated
www.ti.com EXAMPLE STENCIL DESIGN 12X (0.6) 12X (1) 4X (2.54) (3.7) (0.4) TYP (R )0.05 QFM - 1.15 mm max heightSIA0006A QUAD FLAT MODULE 4222361/B 10/2015 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA ALL PADS: 86% SCALE:10X 3 4 METAL TYP LMK60E2-150M,LMK60E0-156257 LMK60A0-148351,LMK60A0-148M www.ti.com SNAS687C – JUNE 2016– REVISED NOVEMBER 2017 Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated
www.ti.com 6-Feb-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMK60A0-148M35SIAR NRND Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60A0 148M35 LMK60A0-148M35SIAR.A NRND Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60A0 148M35 LMK60A0-148M35SIAT NRND Production QFM (SIA) | 6 250 | SMALL T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60A0 148M35 LMK60A0-148M35SIAT.A NRND Production QFM (SIA) | 6 250 | SMALL T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60A0 148M35 LMK60A0-148M50SIAR NRND Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60A0 148M50 LMK60A0-148M50SIAR.A NRND Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60A0 148M50 LMK60A0-148M50SIAT NRND Production QFM (SIA) | 6 250 | SMALL T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60A0 148M50 LMK60A0-148M50SIAT.A NRND Production QFM (SIA) | 6 250 | SMALL T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60A0 148M50 LMK60E0-156257SIAR Active Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E0 156257 LMK60E0-156257SIAR.A Active Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E0 156257 LMK60E0-156257SIAT Active Production QFM (SIA) | 6 250 | SMALL T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E0 156257 LMK60E0-156257SIAT.A Active Production QFM (SIA) | 6 250 | SMALL T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E0 156257 LMK60E2-150M00SIAR NRND Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E2 150M00 LMK60E2-150M00SIAR.A NRND Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E2 150M00 LMK60E2-150M00SIAR.B NRND Production QFM (SIA) | 6 2500 | LARGE T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E2 150M00 LMK60E2-150M00SIAT NRND Production QFM (SIA) | 6 250 | SMALL T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E2 150M00 Addendum-Page 1
www.ti.com 6-Feb-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMK60E2-150M00SIAT.A NRND Production QFM (SIA) | 6 250 | SMALL T&R Yes NIAU Level-3-260C-168 HR -40 to 85 LMK60E2 150M00 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
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