LMK3001

LMK3001 NSC | Alldatasheet

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Technical content

Precision Clock Conditioner with Integrated VCO Evaluation Board Operating Instructions 11-10-2006 National Semiconductor Corporation Interface 2900 Semiconductor Dr. MS A2-600 Santa Clara, CA, 95052-8090

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S TABLE OF C ONTENTS

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S General Description The LMK3001 Evaluation Board simplifies evaluation of the LMK3001 Precision Clock Conditioner with Integrated VCO. The package consists of a characterization board, a USB <--> uWire buffer board, and CodeLoader software. The CodeLoader software will run on a Windows 2000 or Windows XP PC. The purpose of the CodeLoader software is to program the internal registers of the LMK3001 device through a MICROWIRE TM interface. Loop Filter Phase Margin 74.4º K φφ φφ 3200 uA Loop Bandwidth 59.1 kHz Fcomp 10 MHz Crystal Frequency 10 MHz Output Frequency 1470 to 1570 MHz Supply Voltage 3.3 Volts VCO Gain 10 MHz/Volt VCO open 12 nF 1.8 k ΩΩΩΩ 100 pF 110 pF 100 ΩΩ ΩΩ 100 ΩΩ ΩΩ CPout Charge Pump C2 R2 R3 R4 C3 C4 This loop filter is located on the bottom side of the PCB and is selected by placing a 0 ohm resistor on pad R137. This loop filter has been designed for optimal RMS jitter using a low noise reference.

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Read first, Basic Operation Read the document, “Installing CodeLoader 4 & USB Driver” for instructions to prepare the computer for usage with the characterization board before continuing with the hardware setup. For basic operation… 1. Connect a low noise 3.3 V power supply to the Vcc connector located at the top left of the board 2. Connect a 10 MHz reference signal to the OSCin connector located on the right side of the board. 3. Connect the CodeLoader cable to the uWire header located in the lower left.

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Read first, Basic Operation (Continued) 4. Connect the USB <--> uWire board to the PC with the USB cable. The USB <--> uWire board must be connected and operating (both LEDs solid) before CodeLoader is started. If CodeLoader is started before the USB <--> uWire board is connected communications with target board will not work . If this is done, exit CodeLoader and start CodeLoader again. USB Setup

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Read first, Basic Operation (Continued) 5. Start CodeLoader 4. 6. Select the USB Communication Mode on the Port Setup tab. 7. Select the default mode by clicking “M ode” /barb2right “10 MHz OSC”

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Read first, Basic Operation (Continued) 8. Enable output to be measured , any of CLKout(0-7) or EN_Fout from either Clock Outputs or Bits/Pins tab. 9. Program the part by clicking “Keyboard Controls” /barb2right “Load Device” or by pressing Ctrl+L .

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Board Information Notes on the operation of the board are included here. OSCin The board is configured to accept a single ended OSCin source, however it is also possible to drive OSCin with a differential signal by changing the following components. Differential OSCin setup 0 ohm R35, R36, R38, R39 100 ohm R44 0.1 uF C24, C25 (C6 is a 0.1 uF 0402 cap which may be moved to C25) Open C6 The single ended setup uses the following components. Single ended OSCin setup 0 ohm R35, R38 51 ohm No pad for this. Place between R44 pad on C24 side and GND 0.1 uF C24, C6 (C25 is a 0.1 uF 0402 cap which may be moved to C6) Open C25 Fin Fin is placed on the board for testing other devices in the footprint compatible family. Fout Fout allows direct access to the internal VCO before the clock distribution section. The EN_Fout bit must be selected to enable Fout. A 3 dB pad is placed on R103, R104, and R105. Loop Filter R4 and R137 form a “resistor switch” which allows either one of two different loop filters to be selected. Resistor Switch Loop Filter Location Loop Filter Components Default Loop Bandwidth R4 Shorted Top of board C1, C2, R2, C101 77 Hz R137 Shorted Bottom of board C97, C4, R139, C100 59 .1 kHz The following table services as a cross reference from traditional loop filter component designators to the designators on the characterization board. Also, on the board below each loop filter is an offset diagram illustrating the positions of each loop filter component using traditional C1, C2, C2p, R2 designators. Traditional Textbook designators Top Loop Filter designators Bottom Loop Filter designators C1 C1 C97 C2 C2 C4 C2p C101 C100 R2 R2 R139

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Features of the board

• Either one of two loop filters can be selected by shorting either R137 or R4. More info about each loop filter can be found in the General Description and Appendix A.
• Test points for each of the uWire lines are scattered in the lower left corner of the board and include: GOE_TP, DATAuWire, CLKuWire, LEuWire, SYNC_TP, LD_TP, Pin10_TP, Pin7_TP, Pin5_TP.
• Ground is located on each pin GND_J1, the 10 pin header on the left side of the board.
• Ground is located on the GND_tp2 in the upper left corner of the board and GND_tp1 located to the right of the Vcc SMA connector.
• Ground is located on the bottom side of the board on each pad of the unstuffed 10 pin header GND_J2.
• Vcc is located on each pin of VCC_J1, the 10 pin header on the upper left side of the board.
• Vcc is located on VccPlane test point located to the right of the Vcc SMA.
• Vcc is located on the bottom side of the board on each pad of the unstuffed 10 pin header VCC_J2 Other Important Notes
• For both loop filters on the top and bottom side of the board, a helper silkscreen is offset from the loop filters to help identify the components by National Semiconductor’s traditional reference designators associated with loop filters.
• When changing the OSCin frequency, the OSCin frequency register needs to be changed to match.
• Toggle the SYNC* pin to synchronize the clock outputs
• Errata: SYNC* is labeled on the PCB as SYNC, however the logic of SYNC* is still active low!

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Recommended Equipment Power Supply The Power Supply should be a low noise power supply. An Agilent 6623A Triple power supply with LC filters on the output to reduce noise was used in creating these evaluation board instructions. Phase Noise / Spectrum Analyzer For measuring phase noise an Agilent E5052A is recommended. An Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the architecture of the E5052A is superior for phase noise measurements. Oscilloscope For measuring delay an Agilent Infiniium DSO81204A was used. Reference Oscillator Either a 10 MHz crystal or the reference output of any RF test equipment will serve as a 10 MHz output. Note: The default loop filter has a loop bandwidth of ~60 kHz. Inside the loop bandwidth of a PLL the noise is greatly affected by any noise on the reference oscillator (OSCin). Therefore any noise on the oscillator less than 60 kHz will be passed through and seen on the outputs. For this reason the main output of a Signal Generator is not recommended for driving OSCin in this setup. Instead use the 10 MHz reference output of the signal generator.

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Delays These delay measurements illustrate how skew errors due to different length traces may be tuned out. The delay may be adjusted in steps of 150 ps. Delays 150, 300, 450, 600, 750 CLKout0_DLY = 0 ps CLKout1_DLY = all delays programmed: 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800, 1950, 2100, and 2250 ps

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CodeLoader Settings The USB <--> uWire board must be connected and operating (both LEDs solid) before CodeLoader is started. If CodeLoader is started before the USB <--> uWire board is connected communications with target board will not work . If this is done, exit CodeLoader and start CodeLoader again. The Port Setup tab tells CodeLoader what signals are assigned to which pins. If this is wrong, the part will not program. Part setup can be restored to the default state by clicking Mode /barb2right “10 MHz OSC.” The default reference oscillator used for these instructions is 10 MHz and the restored mode expects a 10 MHz OSCin signal. For the loaded mode to take affect the device must be loaded by pressing Ctrl+L.

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S The Bits/Pins tab shows some of the internal registers which are not accessible from any of the other visual tabs like “PLL” and “Clock Outputs.” Program Bits POWERDOWN Powers the part down. EN_Fout Turns on the Fout pin for measuring the int ernal VCO. OSCin_FREQ Must be set to the OSCin frequency in MH z. INPUT_DIV This control also exists on the Clock Outputs page, it sets the value of the input divider. PLL_MUX Programmable to many different values to support Lock Detect or aid troubleshooting. VCO_R3_LF VCO_R4_LF VCO_C3_C4_LF Internal loop filter values, also accessible from Clock Outputs tab. EN_CLKout0..7 Enable CLKout bits from CLKout0 to CLKout7. Also accessible from Clock Outputs tab. EN_CLKout_Global Enable all clock outs. If unselected then the EN_CLKouts are overridden and the outputs are all disabled. Program Pins GOE Set Global Output Enable to high or low logic l evel SYNC* Set SYNC* pin to high or low logic level TRIGGER Set auxiliary trigger pin to high or low logic level.

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S The Registers tab shows the raw bits which will be programmed when device is loaded by clicking Keyboard Controls /barb2right Load Device or Ctrl+L. The Clock Outputs tab allows the user to visualize the clock distribution portions of the device. From this tab the device’s dividers, delays, clock output muxes, and output drivers can be programmed along with internal loop filter values. The PLL block shows the R and N divider values however to change these values either click on the PLL tab or the blue PLL box to access the PLL tab to make changes to the PLL.

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S The PLL tab shows a conventional PLL diagram along with the Input Divider. It is important to realize that the total effective N value is PLL N Counter * Input Divider. This means that the “channel spacing” is the Phase Detector Frequency * Input Divider . Depending on the situation, this may require the R Counter multiplied up by the value of the Input Divider to achieve desired VCO output frequencies. Example : If the desired VCO output frequency was 1501 MHz, R would need to be increased to 20 before 1501 MHz could be programmed because of the Input Divider of 2 would only allow programming of 1500, 1502, 1504, etc. with a 1 MHz phase detector frequency.

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix A: Schematic 1 2 3 4 5 6 A B C D 654321 D C B A Title N um ber Revisio n Size B D a te: 1-Sep -2 006 Sh eet o f File: C:\\w orksvn\\Timex-Eva lB oard\\Timex.ddb D raw n By: Tim ex - M ain Bo ard Tim ex - M ain Bo ard.sch Tim ex - Ou tp uts Tim ex - Ou tp uts.sc h SM A_ CO N N 1 2 3 4 5 6 7 8 9 10 G ND _J1 H EA D ER_2X 5 1 2 3 4 5 6 7 8 9 10 V CC_J1 H EA D ER_2X 5 V cc V cc 1 2 3 4 5 6 7 8 9 10 G ND _J2 H EA D ER_2X 5 1 2 3 4 5 6 7 8 9 10 V CC_J2 H EA D ER_2X 5 V cc V cc

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 1 2 3 4 5 6 A B C D 654321 D C B A Title Number Revision Size C Date: 8-Sep-2006 Sheet of File: C:\\worksvn\\Timex-EvalBoard\\Timex.ddb Drawn By: 820 nF Open C77 10 uF C51 Open Vcc SMA 10 uF C16 1 uF Vcc3 Vcc Vcc4 Vcc7 Vcc8 C76 47 pF R104 270 R103 270 R105 18 ohms 910 uWire HEADER_2X5 R24 15 k R66 27 k R60 27 k R59 27 k R22 15 k R58 27 k 820 R23 15 k Vcc10 C33 0.1 uF C54 100 pF C55 100 pF C23 1 uF C34 0.1 uF C20 1 uF Vcc5 R16 Vcc6 C42 0.1 uF C63 100 pF C64 100 pF C29 1 uF C43 0.1 uF R19 C21 1 uF Vcc11 R17 Vcc12 C44 0.1 uF C65 100 pF C66 100 pF C30 1 uF C45 0.1 uF R20 C22 1 uF Vcc13 R18 Vcc14 C46 0.1 uF C67 100 pF C68 100 pF C31 1 uF C47 0.1 uF R13 C17 1 uF Vcc1 R10 Vcc2 C36 0.1 uF C57 100 pF C58 100 pF C26 1 uF C37 0.1 uF R14 C18 1 uF Vcc7 R11 Vcc8 C38 0.1 uF C59 100 pF C60 100 pF C27 1 uF C39 0.1 uF R15 C19 1 uF Vcc9 R12 Vcc10 C40 0.1 uF C61 100 pF C62 100 pF C28 1 uF C41 0.1 uF Vcc3 Vcc4 Vcc5 Vcc6 Vcc11 Vcc12 Vcc13 Vcc14 Vcc1 Vcc2 Vcc Vcc9 R28 15 k LD_TP C52 0.1 uF Fin SMA Vt 1 Vcc 3 G 4 Fout 5 G 6 NC 7 Fout SMA CLKout7* CLKout7 CLKout6 CLKout6* CLKout4 CLKout4* CLKout5 CLKout5* CLKout0 CLKout0* CLKout1 CLKout1* CLKout2* CLKout2 CLKout3* CLKout3 LD GOE GOE GND 0 GND 1 Fout 2 Vcc1 3 CLKuWire 4 DATAuWire 5 LEuWire 6 NC 7 Vcc2 8 LDObyp1 9 LDObyp2 10 GOE 11 LD 12 Vcc3 13 CLKout0 14 CLKout0* 15 Vcc4 16 CLKout1 17 CLKout1* 18 Vcc5 19 CLKout2 20 CLKout2* 21 Vcc6 22 CLKout3 23 CLKout3* 24 GND 25 Vcc7 26 SYNC 27 OSCin 28 OSCin* 29 Vcc8 30 Vcc9 31 CPout 32 Vcc10 33 Fin 34 Fin* 35 Bias 36 Vcc11 37 CLKout4 38 CLKout4* 39 Vcc12 40 CLKout5 41 CLKout5* 42 Vcc13 43 CLKout6 44 CLKout6* 45 Vcc14 46 CLKout7 47 CLKout7* 48 DS8SF18I CLKuWire DATAuWire LEuWire LEuWire DATAuWire CLKuWire Fin* SMA Fout VCO DIG OSCin PDCP Synth CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 Vcc Vtune 1 NC 2 GND 3 RF 4 RF* 5 Vs 6 VCXO - C5310 R56 Open VtuneVCXO R57 Open VtuneVCO Vcc VCXO_RF* VCXO_RF R21 Open C50 Open C69 Open Pd 6 P4 S 3NC 2Sd 1 TC1-1-13M+ VCO_RF DUT_Fin DUT_Fin* DUT_Fin DUT_Fin* VCO_RF VCXO_RF* VCXO_RF DUT_OSCin* DUT_OSCin R46 0 ohm R47 Open R48 Open R55 Open C48 0.1 uF C49 0.1 uF R101 Open R102 Open R49 Open R50 Open R32 R31 Open R30 C32 1 uF OSCin SMA OSCin* SMA Pd 6 P4 S 3NC 2Sd 1 Open DUT_OSCin DUT_OSCin* TCXO_RF R35 0 ohm R36 Open R37 Open R44 Open C24 0.1 uF C25 Open R38 0 ohm R39 Open Open 0.1 uF R27 R64 Open C11 10 uF C10 10 uF Vtune Open R69 Open Pd 6 P 4S3 NC 2 Sd 1 Open Fout* Open R26 C70 Open C73 1 uF R68 27 k R29 15 k SYNC C74 100 pF SYNC R67 Open GOE Open SYNC Open Vcc R65 Open Vcc C71 Open C72 Open LD R63 Open Open R25 LD Open R62 15 k R61 Open Vcc Open Vin R33 Open LM317_out Vin VCXO VCO Fin OSCin R45 Open Vcc TCXO_RF Open C35 Open C56 Open TCXO Out 3GND 2 Vcont 1 Vcc 4Y1 TCXO Vin 1 Vout 3 Vadj 2 LM317 VinLDO R99 Open R98 Open C14 Open C12 Open C13 Open LM317_out Bypass 1GND 3 Input 4 NC 2 Output 5 Sense 6 /Error 7/Shutdown 8 LP2989 VinLDO C15 Open C75 Open C53 Open R100 Open LP2989_out LP2989_out R34 Open R135 0 ohm R134 Open C95 Open C96 Open C94 Open Open C97 Open C98 Open R140 Open R139 1.8 k R137 R138 Open Open C100 12 nF C101 10 uF C103 Open C102 Open R142 Open R143 Open R145 Open R146 Open VccLDO Open R144 Open C104 Open VinLDO C105 Open C106 Open VtuneVCXO VtuneVCO R40 Open LDObyp2 R42 Open R43 Open R51 Open R52 0 DIG_vcc_tp PDCP_vcc_tp DIG_vcc Open PDCP_vcc Open GOE_TP SYNC_TP 10 uF VCXO_pwr Open VCO_pwr Open TCXO_pwr Open R53 Open R54 Open R136 Open R141 Open R148 Open R147 Open R41 Open C99 Open C107 Open Pin10_TP Pin7_TP Pin5_TP LM317_out LP2989_out VccPlane GND_tp1 Vcc Vcc Vcc C110 Open C108 Open C111 Open C109 0.1 uF R149 Open R150 Open LDObyp1 GND_tp2 R153 Open R154 51 ohm R151 Open R152 51 ohm Vcc Vcc CLKuWire DATAuWire LEuWire TC1-1-13M+ R44_opt 51 ohm

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 1 2 3 4 5 6 A B C D 654321 D C B A Title N um be r Re visio n Siz e C D a te : 1- Sep -2 006 Sh e e t o f File : C:\\w or ksvn\\Tim ex-Eva lBoa rd\\Tim e x.ddb D ra w n By: CLK out4 CLK out4* R94 O pe n R119 O pe n R127 O pe n R118 O pe n R126 O pe n C86 0.1 uF C87 0.1 uF R111 125 R110 125 CLK out4* CLK out4 V c c V c c CLK out0 CLK out0* R106 O pe n R74 O pe n R75 O pe n R72 O pe n R73 O pe n C78 0.1 uF C79 0.1 uF R71 O pe n R70 O pe n CLK out0* CLK out0 V c c V c c CLK out5 CLK out5* R95 O pe n R121 O pe n R129 O pe n R120 O pe n R128 O pe n C88 0.1 uF C89 0.1 uF R113 125 R112 125 CLK out5* CLK out5 V c c V c c CLK out1 CLK out1* R107 O pe n R80 O pe n R81 O pe n R78 O pe n R79 O pe n C80 0.1 uF C81 0.1 uF R77 O pe n R76 O pe n CLK out1* CLK out1 V c c V c c CLK out6 CLK out6* R96 O pe n R123 O pe n R131 O pe n R122 O pe n R130 O pe n C90 0.1 uF C91 0.1 uF R115 125 R114 125 CLK out6* CLK out6 V c c V c c CLK out2 CLK out2* R108 O pe n R86 O pe n R87 O pe n R84 O pe n R85 O pe n C82 0.1 uF C83 0.1 uF R83 O pe n R82 O pe n CLK out2* CLK out2 V c c V c c CLK out7 CLK out7* R97 O pe n R125 O pe n R133 O pe n R124 O pe n R132 O pe n C92 0.1 uF C93 0.1 uF R117 125 R116 125 CLK out7* CLK out7 V c c V c c CLK out3 CLK out3* R109 O pe n R92 O pe n R93 O pe n R90 O pe n R91 O pe n C84 0.1 uF C85 0.1 uF R89 O pe n R88 O pe n CLK out3* CLK out3 V c c V c c CLKout0 CLKout1 CLKout2 CLKout3 CLKout4 CLKout5 CLKout6 CLKout7 PC4 PC0 PC1 PC2 PC3 PC5 PC6 PC7 PC0b PC4b PC5b PC6b PC7b PC3b PC2b PC1b

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix B: Bill of Materials Part Manufacturer Part Number Quant Identifier Capacitors 47 pF Kemet C0603C470J5GAC 1 C76 100 pF Kemet C0402C101J5GAC 14 C54, C55, C57, C58, C59, C60, C61, C62, C63, C64, C65, C66, C67, C68 100 pF Kemet C0603C101J5GAC 1 C74 0.1 uF Kemet C0402C104J4RAC 20 C6, C24, C48, C49, C78, C79, C80, C81, C82, C83, C84, C85, C86, C87, C88, C89, C90, C91, C92, C93 0.1 uF Kemet C0603C104J3RAC 15 C33, C34, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C52 0.1 uF Kemet C0603C104J3RAC 1 C109 12 nF Kemet C0805C123K4RAC 1 C100 820 nF Kemet C0603C824K4RAC 1 C1 1 uF Kemet C0603C105K8VAC 15 C16, C17, C18, C19, C20, C21, C22, C23, C26, C27, C28, C29, C30, C31, C73 1 uF Kemet C0603C105K8VAC 1 C32 10 uF Kemet C0805C106K9PAC 2 C77, C101 10 uF Kemet C0805C106K9PAC 4 C3, C9, C10, C11 Resistors 0 ohm Panasonic ERJ-2GE0R00X 15 R6, R7, R8, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R52 0 ohm Vishay CRCW0603000ZRT1 9 R1, R3, R5, R25, R35, R38, R46, R135, R137 0 ohm Vishay CRCW0603000ZRT1 1 R27 0 ohm Vishay CRCW0603000ZRT1 1 R26 1 ohm Vishay CRCW0603010JRT1 2 R30, R32 18 ohms Vishay CRCW0603180JRT1 1 R105 51 ohms Panasonic ERJ-2GEJ510X 2 R152, R154 51 ohms Vishay CRCW0603510JRT1 1 R44_opt (connected from one pad of R44 to GND) 120 ohms Panasonic ERJ-2GEJ121X 8 R110, R111, R112, R113, R114, R115, R116, R117 270 ohms Vishay CRCW0603271JRT1 2 R103, R104 820 ohms Vishay CRCW0603821JRT1 1 R2

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 1.8 k Vishay CRCW0603182JRT1 1 R139 15 k Vishay CRCW0603153JRT1 6 R22, R23, R24, R28, R 29, R62 27 k Vishay CRCW0603273JRT1 5 R58, R59, R60, R66, R 68 SMA Connectors SMA_EDGE Johnson Components 142-0701-851 1 Vcc SMA_EDGE Johnson Components 142-0701-851 8 CLKout0, CLKout0*, CLKout3, CLKout3*, CLKout4, CLKout4*, CLKout7, CLKout7* SMA_EDGE Johnson Components 142-0701-851 5 Fin, Fin *, OSCin, OSCin*, Fout Other HEADER_2X5 FCI Electronics 52601-S10-8 1 uWire HEADER_2X5 Comm Con Connectors HTSM3203-10G2 2 GND_J1, VCC_J1 BALUN - TC1-1-13M+ Minicircuits TC1-1-13M+ 1 B2 PCB Printed Circuits Corp. LMK30xxEB_PCB 1 - SPCS-8 SPC Technology SPCS-8 4 Standoffs in the fou r corners (insert from bottom) LMK3001 Device National LMK3001 1 U1 Open Open Capacitors 35 C2, C4, C5, C7, C8, C12, C13, C14, C15, C25, C35, C50, C51, C53, C56, C69, C70, C71, C72, C75, C94, C95, C96, C97, C98, C99, C102, C103, C104, C105, C106, C107, C108, C110, C111 Open Resistors 90 R4, R9, R21, R31, R33, R34, R36, R37, R39, R40, R41, R42, R43, R44, R45, R47, R48, R49, R50, R51, R53, R54, R55, R56, R57, R61, R63, R64, R65, R67, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R106, R107, R108, R109, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R136, R138, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R153 Open Comm Con Connectors HTSM3203-10G2 2 GND_J2, VCC_J2 Open Johnson Components 142-0701-851 19 CLKout1, CLKout1*, CLKout2, CLKout2*, CLKout5, CLKout5*, CLKout6, CLKout6*, Vtune, Fout*, LD, GOE, SYNC, VccLDO, DIG_vcc,

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PDCP_vcc, TCXO_pwr, VCO_pwr, VCXO_pwr Open Minicircuits TC1-1-13M+ 2 B1, B3

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix C: Build Diagram

L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bottom Build Diagram