LMK105BBJ475MV

MCP16501_V01 MICROCHIP | Alldatasheet

Document overview

• PDF pages: 44

Technical content

Features

• Input Voltage: 2.7V to 5.5V
• Three 1A Output Current Buck Channels with 100% Maximum Duty Cycle Capability
• 2 MHz Buck Channels PWM Operation
• One Auxiliary 300 mA Low-Dropout Linear Regulator (LDO)
• ±1% Voltage Accuracy for DDR (Buck2 Output) and Core (Buck3 Output)
• Pin-Selectable Output Voltages for Buck2: 1.25V
• MPU-Specific Built-in Default Channel Sequencing and nRSTO Assertion Delay
• Support of MPU Hibernate, Low-Power Modes
• Low Noise, Forced PWM (FPWM) and Low I Q, Light Load, High-Efficiency Mode Available
• Leakage-Free Interfacing to MPU in any Operating Condition through Optimized ESD Protection
• 250 µA Low-Power Mode Typical Quiescent Cur- rent Bucks and LDO On, No Load
• 6 µA Maximum Shutdown Current (VIN =4 . 5 V , TJ = +105°C)
• Separate LDO EN Input, Compatible to LV Logic
• Cost and Size-Optimized BOM
• Thermal Shutdown and Current Limit Protection
• 24-Pin 4 mm × 4 mm VQFN Package
• -40°C to +125°C Junction Temperature Range

Applications

• High-Performance MPUs Power Supply Solutions
• µC/µP, FPGA and DSP Power

Description

The MCP16501 is a cost and size optimized integrated PMIC, compatible with Microchip’s EMPUs (Embedded Microprocessor Units) and associated DRAM Memo- ries. It is compatible with SAMA5DX, SAM9X6 and SAMA7G MPUs, which are supported by dedicated device variants. The MCP16501 integrates three DC-DC Buck regulators and one auxiliary LDO, and provides a comprehensive interface to the MPU. All Buck channels can support loads up to 1A and are 100% duty cycle-capable. The 300 mA LDO is provided such that sensitive analog loads can be supported. The DDR memory voltage (Buck2 output) and MPU core voltage (Buck3 output) are selectable by means of two 3-state input pins. This method allows greater pre- cision in the output voltage setting by eliminating inac- curacies due to external feedback resistors, while minimizing external compone nt count. The voltage selection set allows easy migration across different generations of memory. The default power channel sequencing is built-in according to the requirements of the MPU. A dedicated pin (LPM) facilitates the transition to Low-Power modes and the implementation of Backup mode with DDR in self-refresh (Hibernate mode). The MCP16501 features a low no-load operational quiescent current and it draws less than 6 µA (V IN = 4.5V, TJ = +105°C) in full shutdown. Active discharge resistors are provided on each output. All Buck channels support safe start-up into pre-biased outputs. The MCP16501 is available in a 24-pin 4 mm x 4 mm VQFN package with an operating junction temperature range from -40°C to +125°C. Cost and Size Optimized PMIC for SAMA5DX/SAM9X6/ SAMA7G Series MPUs

DS20006388A-page 2  2020 Microchip Technology Inc. Package Types 24-Pin 4 mm x 4 mm VQFN – Top View

 2020 Microchip Technology Inc. DS20006388A-page 3 MCP16501 Typical Application Circuit See Table 3-1 for pin information.

DS20006388A-page 4  2020 Microchip Technology Inc. Functional Block Diagram 40kΩ SYSTEM CONTROL PVIN2 Buck2 SW2 PGND2 OUT2 PVIN1 Buck1 SW1 PGND1 OUT1 PVIN3 Buck3 SW3 PGND3 OUT3 LOUT LDO1 VIN SGND nSTRT PWRHLD LPM SELV2 SELV3 nSTRTO nRSTO LEN LFB VINVIN VINVIN

 2020 Microchip Technology Inc. DS20006388A-page 5 MCP16501

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings† ESD Protection on All Pins: †N o t i c e : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise specified: TA =T J =+ 2 5 ° C ; VIN =V I N=P V I N x=5 V ; L 1=L 2=L 3 =2 . 2µ H ; COUT1, COUT2,, COUT3=2 2µ F . Boldface type applies for junction temperatures TJ of -40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions System Input Supply Supply Voltage Range V IN 2.7 — 5.5 V Undervoltage Lockout Threshold VUVLO_TH 2.4 2.55 2.7 V Turn-on Undervoltage Lockout Hysteresis VUVLO_HYS —1 2 5— m V Shutdown (Off) Current I SHDN —7 10 µA PWRHLD = LPM = 0, nSTRT, nRSTO, nSTRTO floating, V IN =5 . 5 V ISHDN_105 (1) —4 . 5 6 µ A P W R H L D = L P M = 0, nSTRT, nRSTO, nSTRTO floating, V IN =4 . 5 V , TJ = -40°C to +105°C Hibernate Mode Non-Switching Quiescent Current I QNS_HIB1 —1 1 0 150 µA I OUT2 = 0 mA, Buck2 on, all other channels off, V OUT2 >V OUT2_NOM, LPM = 1, PWRHLD = 0 Hibernate Mode Non-Switching Quiescent Current MCP16501D Only I QNS_HIB2 —1 5 0 190 µA I OUT2 = 0 mA, Buck2 on, LDO on, all other channels off, V OUT2 >V OUT2_NOM, VLFB >V LFB_NOM LPM = 1, PWRHLD = 0 Note 1: Maximum limit for TJ = -40°C to +105°C based on characterization data. 2: Not production tested. 3: Typical value from bench characterization, maximum value production tested.

DS20006388A-page 6  2020 Microchip Technology Inc. Hibernate Mode Operational Quiescent Current (Switching, One Buck Channel On) (Note 2) IQOP_HIB1 —1 1 0— µ A I OUT2 = 0 mA, Buck2 on (VOUT2 = 1.2V), all other channels off, LPM =1, PWRHLD = 0 Hibernate Mode Operational Quiescent Current (Switching, One Buck Channel On and the LDO Channel On) (Note 2) IQOP_HIB2 —1 5 0 — µA I OUT2 =I LDO =0m A , Buck2 and LDO on OUT2 =1 . 2 V , VLDO=1 . 8 V ) , all other channels off, LPM =1, PWRHLD = 0 Low-Power Mode Operational Quiescent Current (Switching) (Note 2) IQOP_LPM —2 0 5— µ A I OUTx = 0 mA, all channels on excluding LDO, default settings, PWRHLD = LPM = Low-Power Mode Operational Quiescent Current (Switching) (Note 2) IQOP_LPM2 —2 5 0— µ A I OUTx = 0 mA, all channels on including LDO, default settings, PWRHLD = LPM = Active Mode Operational Quiescent Current (Switching) (Note 2) IQOP_ACT —1 4— m A I OUTx = 0 mA, all channels enabled including LDO, default settings, PWRHLD = 1, LPM = 0 SELV2 = LOW, SELV3 = HIGH Thermal Protection Overtemperature Shutdown Threshold (Note 2) TTSD —1 6 0— ° C Overtemperature Shutdown Hysteresis (Note 2) TTSD_HYS —2 0— ° C Buck1 Input Operating Voltage Range V PVIN1 2.7 — 5.5 V PVIN1 Shutdown Current I PVIN1_SHDN —0 . 0 5 2 µA Regulator disabled, V PVIN1 =5 V Output Voltage Accuracy, FPWM ACC_OUTPWM1 -2 — +2 %I OUT1 = 0 mA Output Voltage Accuracy, Auto-PFM ACC_OUTPFM1 -2 — +2 % IOUT1 = 0 mA, HCM off Output Voltage Line Regulation (Note 2) LINE_REGPWM1 —0 . 0 3—% IOUT1 =0m A , FPWM, VIN = PVIN1 = VIN = 3.6V to 5.5V LINE_REGPFM1 —0 . 0 7— I OUT1 =0m A , A u t o - P F M , VIN = PVIN1 = VIN = 3.6V to 5.5V Output Voltage Load Regulation (Note 2) LOAD_REGPWM1 —0 . 3— % I OUT1 = 0A to 1A, FPWM LOAD_REGPFM1 —0 . 5— % I OUT1 = 0A to 1A, Auto-PFM Hysteretic Control Mode Upper Regulation Threshold, Auto-PFM (MCP16501E only) HCM_TH 1.7 2.9 4.3 %I OUT1 =0m A , PWRHLD = LPM = 1, VIN = PVIN1 = 1.06 x VOUT1_NOM, OUT1 rising, % of VOUT1_NOM Hysteretic Control Mode Disable Threshold, Auto-PFM (MCP16501E only) HCM_DIS — 11.1 — % I OUT1 =0m A , PWRHLD = LPM = 1, VIN = PVIN1 rising, % of V OUT1_NOM AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified: TA =T J =+ 2 5 ° C ; VIN =V I N=P V I N x=5 V ; L 1=L 2=L 3 =2 . 2µ H ; COUT1, COUT2,, COUT3=2 2µ F . Boldface type applies for junction temperatures TJ of -40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions Note 1: Maximum limit for TJ = -40°C to +105°C based on characterization data. 2: Not production tested. 3: Typical value from bench characterization, maximum value production tested.

 2020 Microchip Technology Inc. DS20006388A-page 7 MCP16501 Hysteretic Control Mode Enable Threshold, Auto-PFM (MCP16501E only) HCM_EN 5 9 13 %I OUT1 =0m A , PWRHLD = LPM = 1, VIN = PVIN1 falling, % of V OUT1_NOM Switching Frequency f sw 1.8 2 2.2 MHz FPWM Maximum Duty Cycle D MAX 100 — — % Functionality test Minimum On Time T ON_MIN1 —3 5— n s F P W M High-Side Switch On-Resistance RDSonP1 — 140 160 m Ω PVIN1 = VIN = 3.6V Low-Side Switch On-Resistance RDSonN1 — 120 140 m Ω PVIN1 = VIN = 3.6V Start-up POK Bypass Threshold VPOKB_TH_B1 360 400 440 mV PVIN1 – OUT1, OUT1 rising, PVIN1 = 3.0V, VOUT1_NOM =3 . 3 V Start-up POK Bypass Threshold Hysteresis VPOKB_HYS_B1 — 50 — mV OUT1 falling, PVIN1 = 3.0V Soft Start Rate SSR — 3.125 — V/ms High-Side Peak Current Limit (Cycle by Cycle) ILIM_HS1 1.2 1.8 2.4 A Current Limit Frequency Foldback VOUT1 Threshold VTH_FFB1 —5 0 0— m V Hiccup Mode Short-Circuit Protection Wait Time tHICCUP — 3x Soft Start Time Low-Side Negative Peak Current Limit (FPWM) ILIM_NEG1 -1.4 -1 -0.8 A Zero Current Detection Threshold IZCD1 05 0 1 1 0 m A Active Discharge Resistance RDISCH_OUT1 —2 5— Ω DISCH enabled when regulator is disabled Buck2, Buck3 Input Operating Voltage Range V PVINx 2.7 — 5.5 V PVINx Shutdown Current I PVINx_SHDN —0 . 0 5 2 µA Regulator disabled, PVINx = 5V Output Voltage Accuracy, FPWM ACC_OUTPWMx -1 — +1 %I OUTx = 0 mA, 0.9V≤VOUTx ≤1.3V -1.5 — +1.5 IOUTx =0m A , VOUTx < 0.9V or VOUTx > 1.3V Output Voltage Accuracy, Auto-PFM ACC_OUTPFMx -1 — +1 %I OUTx = 0 mA, 0.9V≤VOUTx ≤1.3V -1.5 — +1.5 IOUTx =0m A , VOUTx <0 . 9 V o r VOUTx > 1.3V Output Voltage Line Regulation (Note 2) LINE_REGPWMx —0 . 0 3—% I OUT1 =0m A , F P W M , VIN = PVIN1 = VIN = 3.6V to 5.5V LINE_REGPFMx —0 . 0 7— I OUT1 = 0 mA, Auto-PFM, VIN = PVIN1 = VIN = 3.6V to 5.5V Output Voltage Load Regulation (Note 2) LOAD_REGPWMx —0 . 3— % I OUTx = 0A to 1A, FPWM LOAD_REGPFMx —0 . 5— I OUTx = 0A to 1A, Auto-PFM Switching Frequency f sw 1.8 2 2.2 MHz FPWM AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified: TA =T J =+ 2 5 ° C ; VIN =V I N=P V I N x=5 V ; L 1=L 2=L 3 =2 . 2µ H ; COUT1, COUT2,, COUT3=2 2µ F . Boldface type applies for junction temperatures TJ of -40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions Note 1: Maximum limit for TJ = -40°C to +105°C based on characterization data. 2: Not production tested. 3: Typical value from bench characterization, maximum value production tested.

DS20006388A-page 8  2020 Microchip Technology Inc. Maximum Duty Cycle D MAX 100 — — % Functionality test Minimum On Time T ON_MINx —3 5— n s F P W M High-Side Switch On-Resistance RDSonPx — 140 160 m Ω PVINx = VIN = 3.6V Low-Side Switch On-Resistance RDSonNx — 120 140 m Ω PVINx = VIN = 3.6V Soft Start Rate SSR — 3.125 — V/ms High-Side Peak Current Limit (Cycle-by-Cycle) ILIM_HSx 1.2 1.8 2.4 A Current Limit Frequency Foldback VOUTx Threshold VTH_FFBx —5 0 0— m V Hiccup Mode Short-Circuit Protection Wait Time tHICCUP —3 x S o f t Start Time Low-Side Negative Peak Current Limit (FPWM) ILIM_NEGx -1.4 -1 -0.8 A Zero Current Detection Threshold IZCDx 03 3 1 1 0 m A Active Discharge Resistance R DISCH_OUTx —2 5— Ω DISCH enabled when regulator is disabled LDO Input Operating Voltage Range V LVIN 2.7 — 5.5 V Output Voltage Range V LOUT 0.9 — 3.7 V Recommended application settings. Stable Output Capacitor Range (Note 2) CLOUT 2.2 — 20 µF ILOUT ≤ 150 mA – application requirement 4.7 — 20 µF ILOUT ≤ 300 mA – application requirement Operational Quiescent Current IVIN_Q —1 1 0— µ A I LOUT= 0 mA; only LDO on; Bucks off LDO Operation Quiescent Current IVIN_Q_LDO —4 5— µ A I LOUT= 0 mA; all channels on including LDO, ΔVIN current when turning on LDO Feedback Voltage ACC_LFB 0.8865 0.9 0.9135 V VIN = 3.6V Dropout Voltage (Note 3) VDO —1 7 0 500 mV I LOUT =3 0 0 m A Output Voltage Line Regulation LINE_REG — 0.024 — % VIN = 3.6V to 5.5V, ILOUT =0 . 1m A Output Voltage Load Regulation LOAD_REG — 0.3 — % I LOUT = 0.1 mA to 300 mA PSRR (Note 2) PSRR — 63 — dB f = 1 kHz, I OUT =2 0m A , VLOUT = 1.8V, VIN modulated — 46 — dB f = 10 kHz, I OUT =2 0m A , VLOUT = 1.8V, VIN modulated Soft Start Rate SSR_LFB — 3.125 — V/ms measured on LFB AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified: TA =T J =+ 2 5 ° C ; VIN =V I N=P V I N x=5 V ; L 1=L 2=L 3 =2 . 2µ H ; COUT1, COUT2,, COUT3=2 2µ F . Boldface type applies for junction temperatures TJ of -40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions Note 1: Maximum limit for TJ = -40°C to +105°C based on characterization data. 2: Not production tested. 3: Typical value from bench characterization, maximum value production tested.

 2020 Microchip Technology Inc. DS20006388A-page 9 MCP16501 Note 1: TA = +25°C; VIN = PVINx = 5V; unless otherwise specified. Bold values indicate -40°C ≤ TJ ≤ +125°C. Current Limit I LIM_LOUT 310 420 550 mA VIN = 4.5V, VLOUT = 80% of nominal Active Discharge Resistance R DISCH_LOUT —2 5— Ω DISCH =enabled when regulator is disabled LEN Input LEN Logic High Input Voltage, V IH VIH_LEN 1.15 —— V LEN Logic Low Input Voltage, VIL VIL_LEN —— 0.4 V LEN Input leakage current I LK_LENT -1 — 1 µA nSTRT Input Logic High Input Voltage, VIH VIH_nSTRT 0.66 VVIN — — V VIN = 3.6V-5.5V Logic Low Input Voltage, VIL VIL_nSTRT —— 0.36 VVIN V VIN = 3.6V-5.5V Pull-up Resistance R PU_nSTRT —4 0— k Ω nSTRT Deglitch Time t DT_nSTRT — 10 — µs Falling edge of nSTRT pin SELV2, SELV3 Three-State Inputs (x = 2, 3) High State Threshold Voltage, VIHT VIHT_SELVx VVIN – 0.9V — VVIN – 0.4V V Low State Threshold Voltage, VILT VILT_SELVx 0.5 — 1.0 V Input Leakage Current High I lkgH_SELVx —0 . 7 1 µA SELVx = VIN – 0.4V Input Leakage Current Low I lkgL_SELVx -1 0.7 — µA SELVx = 0.4V PWRHLD, LPM Logic Inputs (x= PWRHLD, LPM) Logic High Input Voltage, VIH VIH_x 1.5 — — V VIN = 3.6V-5.5V Logic Low Input Voltage, VIL VIL_x —— 0.4 V VIN = 3.6V-5.5V Input Leakage Current I lkg_x -1 — 1 µA Deglitch Time t DT_x —1 0— µ s nRSTO, nSTRTO Logic Outputs (x = nRSTO, nSTRTO) Output Voltage Low, VOL VOL_x —— 0.4 V VIN = 3.6V-5.5V, I OL =2 m A Leakage Current I lkg_x —— 1 µA 5.5V applied, output driver off TEMPERATURE SPECIFICATIONS(1) Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Junction Temperature Range TJ -40 — +125 °C Steady state Maximum Junction Temperature T J_MAX — — +150 °C Transient Package Thermal Resistance θJA —3 8— ° C / W AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified: TA =T J =+ 2 5 ° C ; VIN =V I N=P V I N x=5 V ; L 1=L 2=L 3 =2 . 2µ H ; COUT1, COUT2,, COUT3=2 2µ F . Boldface type applies for junction temperatures TJ of -40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions Note 1: Maximum limit for TJ = -40°C to +105°C based on characterization data. 2: Not production tested. 3: Typical value from bench characterization, maximum value production tested.

DS20006388A-page 10  2020 Microchip Technology Inc.

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise specified: VIN = VIN= PVINx = 5V; L1 = L2 = L3 = 2.2 µH; COUT1 = COUT2 = COUT3= 22 µF, TA = +25°C FIGURE 2-1: VIN Operating Current vs. Input Voltage and Temperature – Hibernate Mode (LPM = High, PWRHLD = Low). FIGURE 2-2: V IN Quiescent Current vs. Input Voltage and Temperature – Low-Power Mode (LPM = PWRHLD = High). FIGURE 2-3: V IN Quiescent Current vs. Input Voltage and Temperature – Active Mode (LPM = Low, PWRHLD = High). FIGURE 2-4: Buck1 Efficiency vs. Load Current Measured on PVIN1 (V OUT1 =3 . 3 V ) . FIGURE 2-5: Buck2 Efficiency vs. Load Current Measured on PVIN2 (VOUT2 =1 . 2 V ) . FIGURE 2-6: Buck3 Efficiency vs. Load Current Measured on PVIN3 (VOUT3 =1 . 2 5 V ) . Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes on ly. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tabl es, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 9,1 2SHUDWLQJ&XUUHQW ,QSXW9ROWDJH 7$ ƒ& 7$ ƒ& 9287 9 9/'2 9 0&3' 7$ ƒ& 7$ ƒ& 0&3$ 0&3' 200 250 300 350 400 450 500 550 600 650 700 VIN Operating Current (μA) Input Voltage (V) TA = -40°C TA = 25°C TA= 15°C TA= 15°C MCP16501A MCP16501E VIN Operating Current (mA) Input Voltage (V) TA = -40°C TA = 25°C TA=1 5°C TA= 15°C 100 Efficiency (%) IOUT (mA) VIN = 5V FPWM AUTOPFM 100 Efficiency (%) IOUT (mA) VIN = 5V FPWM AUTOPFM 100 Efficiency (%) IOUT (mA) VIN = 5V FPWM AUTOPFM

DS20006388A-page 14  2020 Microchip Technology Inc.

3.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Number Pin Name Description 1 OUT1 Output Sensing for Buck Channel 1. Connect to the regulation point for V OUT1. 2 nRSTO Active-Low, Open-Drain Reset Output. 3 PWRHLD Power Hold Input. Typically asserted as high by the MPU to maintain power after the initial start-up is triggered by nSTRT. PWRHLD is to be asserted as low by the MPU to initiate a PMIC shutdown sequence. 4 LPM Low-Power Mode Input Pin. In combination with PWRHLD, this pin defines the power mode status of the MCP16501. 5 nSTRTO Active-Low, Open-Drain Start Event Output. nSTRTO is asserted low whenever nSTRT is low. 6 OUT2 Output Sensing for Buck Channel 2. Connect to the regulation point for V OUT2. 7 PVIN2 Power Input Voltage of Buck Channel 2. Connect a ceramic capacitor from PVIN2 to the PGND2 pin to localize pulsed current loops and decouple switching noise. 8 SW2 Switch Node of Buck Channel 2. Internal power MOSFET switches and external inductor connection. 9 PGND2 Power Ground of Buck Channel 2. 10 PGND3 Power Ground of Buck Channel 3. 11 SW3 Switch Node of Buck Channel 3. Inter nal power MOSFET switches and external inductor connection. 12 PVIN3 Power Input Voltage of Buck Channel 3. Connect a ceramic capacitor from PVIN3 to the PGND3 pin to localize pulsed current loops and decouple switching noise. 13 OUT3 Output Sensing for Buck Channel 3. Connect to the regulation point for V OUT3. 14 nSTRT Start Event Input. Drive nSTRT to low to initiate a start-up sequence. nSTRT is pulled up internally. A capacitor can be connected to nSTRT to automatically initiate a power-up sequence when the main supply rises. 15 SELV3 Buck Channel 3 Output Voltage Selection Pin. Three-state input. 16 SGND Signal Ground. Connect to reference ground plane. 17 VIN Input voltage for the LDO and for the a nalog control circuitry. Decouple VIN to SGND with a 2.2uF (minimum) ceramic capacitor. 18 LOUT LDO Output. Decouple LOUT to ground with a 2.2 µF (minimum) ceramic capacitor. 19 LFB LDO FB pin. Connect to an external re sistor divider to LOUT for output voltage adjustment. 20 SELV2 Buck Channel 2 Output Voltage Selection Pin. Three-state input. 21 LEN LDO Enable input. 22 PGND1 Power Ground of Buck Channel 1. 23 SW1 Switch Node of Buck Channel 1. Inter nal power MOSFET switches and external inductor connection. 24 PVIN1 Power Input Voltage of Buck Channel 1. Connect a ceramic capacitor from PVIN1 to the PGND1 pin, to localize pulsed current loops and decouple switching noise. - EP Exposed Pad. Connect to ground plane with vias to ensure good thermal properties.

 2020 Microchip Technology Inc. DS20006388A-page 15 MCP16501

4.0 DEVICE OPTIONS

The MCP16501 is offered in different options, depending on the target I/O voltage needed external memory type and behavior in bypass situations. The options currently available, also shown in Table 4-1, are the following: TABLE 4-1: DEFAULT CONFIGURATIONS Note: All device variants are generated at the factory with One-Time-Programmable memory, which configures default settings at power-up. Please contact your nearest Microchip Sales Office for further assis- tance on the developm ent of customized device variants. Device Options MCP16501A MCP16501B MCP16501C MCP16501D MCP16501E VOUT1 3.3V 2.8V 3V 3.3V 3.3V LPDDR2/3 Not supported Not supported N ot supported Supported Not supported Hysteretic Control Mode (HCM) Not supported Not supported Not supported Not supported Supported

DS20006388A-page 16  2020 Microchip Technology Inc.

4.1 Buck Channels and Related

The MCP16501 Buck channels are based on Peak Current mode control architecture and have internal frequency compensation for the voltage regulation loop. The slope compensation is optimized for induc- tors in the 1.5 µH to 2.2 µH range. A minimum output capacitor of 22 µF is required for stability. Output capacitance can be increased if necessary; however, the maximum output capacitance value should be lim- ited to avoid engaging the Hiccup mode overcurrent protection during the initial soft start ramp. Further details are given in Section 5.5 “Maximum Simulta- neous Capacitive and DC Loading in Soft Start”. The recommended input decoupling capacitance on each Buck channel is 4.7 µF. The Buck channels can operate in either Forced PWM mode (Continuous Inductor Current mode), where the inductor current is allowed to go negative, or in Auto- matic PFM mode, where the inductor current is prevented from going negative through Zero-Current Detection (ZCD) and diode emulation of the low-side MOSFET. The switching frequency in Forced PWM Mode is nominally 2 MHz.

4.2 LDO Channel and Related

The MCP16501 LDO is designed for operation with low-ESR ceramic output capacitors of 2.2 µF (minimum value) for loads up to 150 mA, and of 4.7 µF (minimum value) for loads up to 300 mA. The total output capaci- tance should not exceed 20 µF. Recommended capac- itor part numbers are given in Section 5.1 “Recommended External Components” .

4.3 Control Signals and Power States

4.3.1 INTERFACING SIGNALS

The MCP16501 is interfaced to the host MPU by means of the following signals: nSTRTO (open-drain output), nRSTO (open-drain output), PWRHLD (input) and LPM (input).The ESD protection on each interfacing signal is purposely designed to prevent any leakage from the MPU I/Os, even in the case where the main input power is removed from the MCP16501. 4.3.2 nSTRT, nSTRTO, PWRHLD FUNCTIONALITY The nSTRT (push button input) serves as an external wake-up input to the PMIC+MPU system. nSTRT is internally pulled up to VIN and monitored. When the nSTRT is pulled/detected as low (e.g., by means of a push button or any other pull-down device) for longer than a minimum debouncing time, the MCP16501 initiates the turn-on sequence. The nSTRTO signal is asserted low whenever the nSTRT is detected to be lo w; otherwise, it is High-Z (typically, nSTRTO has an external pull-up resistor). The only exception to this input (nSTRT)/output (nSTRTO) relationship is the so called Automatic Wake-up Pulse (AWKP) that is described in Section 4.4.6 “Restart Sequence After Fault and Automatic Wake-up Pulse (AWKP) Genera- tion-MCP16501D only” (applicable to MCP16501D only). After the start-up sequence has been initiated, the MCP16501 expects the assertion of the PWRHLD signal (Power-Hold) from the MPU to validate the start-up. PWRHLD could already be high in a typical application using a backup supply. If PWRHLD has not been asserted high by the MPU before the completion of the start-up sequence (i.e., when nRSTO is about to be asserted high), the MCP16501 will automatically initiate a turn-off sequence. During run time (PWRHLD = high), the nSTRT (thus nSTRTO) can again be asserted low. No automatic action is taken by the MCP16501 in this case. 4.3.3 nSTRT/PWRHLD TYPICAL USE CASES Depending on the presence of a backup supply and the availability of an external wake-up signal connected at nSTRT (“Button”), four di fferent scenarios can be defined for the turn-on of the MCP16501, as described in Figure 4-1.

 2020 Microchip Technology Inc. DS20006388A-page 17 MCP16501 FIGURE 4-1: Illustration of Start-up Mechanisms for Various MPU Configurations. Applications With a Backup Supply Ap plications Without a Backup Supply Applications Without Start-up Push Button The application starts when VIN ramps up because of the capacitor C, which delays the rise of nSTRT with respect to VIN and causes nSTRT to appear low as soon as the MCP16501 is powered. Note that PWRHLD (= SHDN from MPU) was set to ‘1’ at the time the battery was mounted on the PCB (i.e., at the time of manufacturing). The power channels of MCP16501 are turned off by the MPU by setting SHDN = 0. The MPU is then in Backup mode. If supported, the DDR can also be placed in Backup Self-Refresh (BSR) mode by setting LPM = 1 before SHDN = 0. To wake up the application from Backup mode, a wake-up event must be generated for the SHDWC (Shutdown and Wake-up Controller) of the MPU. This can be an internal event (e.g., RTC, RTT alarm, TAMPER detection) or an event on an I/O of the SHDWC (e.g., wake-up from a wireless module). The MPU will then set SHDN = 1 and the low-to-high transition of PWRHLD will cause the MCP16501 to restart. If VIN is cycled while the MPU is in Backup mode (SHDN = 0), the MCP16501 restarts automatically and sends a wake-up event to the MPU on nSTRTO (WKUP). If this wake-up event was not enabled in the MPU SHDWC configuration, SHDN will stay low and the MCP16501 will turn off at the end of the start-up sequence, because PWRHLD has not been set high. If this wake-up event is enabled, SHDN will immediately go high, thus confirming the start-up sequence for the MCP16501 and the application will restart. The application starts when V IN ramps up because of the capacitor C, which delays the rise of nSTRT with respect to VIN and causes nSTRT to appear low as soon as the MCP16501 is powered. PWRHLD (= SHDN from MPU) is set to ‘1’ as soon as VBAT (= VDDIO) is above its internal POR threshold (around 1.5V). The power channels of MCP16501 are turned off by the MPU by setting SHDN = 0. In this case, the MPU is not in Backup mode; it is simply completely off. LPM cannot be used, nor can SHDN be set to ‘1’ because the supply voltage of the SHDWC controller is missing. From the OFF state, the application can only be restarted by cycling power on V IN. Applications With Start-up Push Button (at nSTRT) The application does not immediately start when VIN ramps up. The button must be pressed (nSTRT = Low) to start the MCP16501. Note that PWRHLD (= SHDN from MPU) was set to ‘1’ at the time the battery was mounted on the PCB (i.e., at the time of manufacturing). The power channels of MCP16501 are turned off by the MPU by setting SHDN = 0. The MPU is then in Backup mode. If supported, the DDR can also be placed in backup self-refresh mode (BSR) by setting LPM = 1 before SHDN = 0. To wake up the application from Backup mode, a wake-up event must be generated for the SHDWC (Shutdown and Wake-up Controller) of the MPU. This can be an internal event (e.g., RTC, RTT alarm, TAMPER detection) or an event on an I/O of the SHDWC (e.g., wake-up from a wireless module). The MPU will then set SHDN = 1 and the low-to-high transition of PWRHLD will cause the MCP16501 to restart. If VIN is cycled while the MPU is in Backup mode (SHDN = 0), the MCP16501 does not restart automatically. To restart the application, the button must be pressed and nSTRTO (WKUP) be an enabled wake-up event. The DDR supply loss, due to an input power loss while in BSR mode, will be managed by software (i.e., by reloading the contents of the DDR). The application does not immediately start when VIN ramps up. The button must be pressed to start the MCP16501. PWRHLD (= SHDN from MPU) is set to ‘1’ as soon as VBAT (= VDDIO) is above its internal POR threshold (around 1.5V). The power channels of MCP16501 are turned off by the MPU by setting SHDN = 0. In this case, the MPU is not in Backup mode; it is simply completely off. LPM cannot be used, nor can SHDN be set to ‘1’ because the supply voltage of the SHDWC controller is missing. To restart the application, the push button must be pressed. MCP16501 MPU VDDIO VDDCORE VDDIODDR VIN SHDN LPM WKUP PWRHLD LPM nSTRTO VBATC nSTRT PVINx, VIN MCP16501 MPU VDDIO VDDCORE VDDIODDR VIN SHDN LPM WKUP PWRHLD LPM nSTRTO VBAT nSTRT PVINx, VIN

DS20006388A-page 18  2020 Microchip Technology Inc.

4.3.4 PWRHLD, LPM, LEN AND POWER

PWRHLD and LPM define different power states which are illustrated in Table 4-2. These are default definitions for the MCP16501A. Other default definitions are possi- ble for different or customized product variants. The LDO operation is completely independent of the power states and is controlled by the LEN pin. The only exception to this is in the case of MCP16501D, used in LPDDR2 applications where the LDO is used to power the memory alongside Buck2. For more details on this see Section 5.3, LPDDR2 Support with Hibernate Mode-MCP16501D Only. Other logic combinations of PWRHLD and LPM are for- bidden. The initial state is the OFF state (shutdown). The process by which the MCP16501 abandons the OFF state and enters the other possible power states is defined as the power-up sequence, which is described in Section 4.4.1 “Typical Power-up Sequence and Timing”. The following state diagram in Figure 4-2 illus- trates the power states of MCP16501 and their typical and/or permissible dynamic transitions. FIGURE 4-2: Finite State Machine (FSM) States Diagram for MCP16501. TABLE 4-2: DEFAULT POWER STATES DEFINITION (MCP16501A) PWRHLD LPM Buck1 Buck2 Buck3 LDO nRSTO Power State

00 Off Off Off LEN Controlled Low Off

01 Off On

Off LEN Controlled Low Hibernate mode 11 On Auto-PFM On Auto-PFM On Auto-PFM LEN Controlled High-Z Low-Power mode 10 On FPWM On FPWM On FPWM LEN Controlled High-Z Active mode

 2020 Microchip Technology Inc. DS20006388A-page 19 MCP16501

4.3.5 SELV2 AND SELV3 PINS

Pins SELV2 and SELV3 ar e meant to program the default settings of some rails that must be activated during the power-up sequence, but whose voltage val- ues are application-dependent. These are Buck2 and Buck3, the first being dedicated to DDRx/LPDDRx power, while the latter being dedicated to core power. The default values are selectable among three options, corresponding to three different states of the relevant pin: connected to ground (Low), connected to input supply (High) or left unconnected (High-Z). The Buck2 default voltage can be selected by means of the SELV2 pin as follows: TABLE 4-3: V OUT2 DEFAULT VOLTAGE VS. SELV2 PIN The Buck3 default voltage can be selected by means of the SELV3 pin as follows: TABLE 4-4: V OUT3 DEFAULT VOLTAGE VS. SELV3 PIN The statuses of SELV2 and SELV3 are frozen in a snap- shot as soon as the VIN voltage exceeds the turn-on Undervoltage Lockout Threshold (UVLO), as specified in the “Electrical Characteristics” table. Any changes of the SELV2 and SELV3 pins will have no effect after the snapshot, and VIN must fall under the turn-off (lower) UVLO threshold to unfreeze the snapshot. Both pins are intended to be connected to GND (0V), to VIN or left floating in the application. When left float- ing, internal circuitry is initially activated to bias SELV2 and SELV3 at start-up for proper three-state (floating state) detection. For “Electrical Characteristics” table specification purposes, the High State Threshold Voltage (V IHT) and Low State Threshold Voltage (VILT) of pins SELV2 and SELV3 are given. They have both a minimum and a maximum value specification. At the time the snapshot is taken, those Min. and Max. values should be used and interpreted as follows:

• I f VIHT(MAX) < V(SELVx) ≤ V(VIN)  SELVx is considered HIGH
• I f 0 V ≤ V(SELVx) < VILT(MIN)  SELVx is considered LOW
• I f VILT(MAX) < V(SELVx) < VIHT(MIN)  SELVx is considered floating If VIHT(MIN) ≤ V(SELVx) ≤ V IHT(MAX) or V ILT(MIN) ≤ V(SELVx) ≤ VILT(MAX), then the logic status of SELVx may not be interpreted correctl y. Therefore, if the end user chooses a connection different than the recom- mended connection to GND, VIN or no connection, then any usage of the SELVx pi ns within those boundaries should be avoided. This is also illustrated in Figure 4-3 shown below: FIGURE 4-3: SELVx High, Low and Float States Threshold. 4.3.6 nRSTO (RESET OUTPUT) PIN Pin nRSTO is an active-low, open-drain output pin that keeps the MPU in a Reset state. The nRSTO pin is released (i.e., goes High-Z) with a 16ms delay upon successful completion of a start-up sequence. nRSTO is immediately asserted low when either the VIN volt- age falls below the UVLO threshold, or a Fault condi- tion is detected at system level (such as a Thermal Shutdown) or an overcurrent condition is detected on the Buck channels. Please see Section 5.4 “Protec- tions” for more details on the Faults that would cause the nRSTO signal low assertion. nRSTO also goes low when the Hibernate mode is entered.

4.4 Power-up/Power-Down/Hibernate

4.4.1 TYPICAL POWER-UP SEQUENCE

The typical scenario applies to MPU applications, where:

• I/O voltage (VDDIO) and, if applicable, auxiliary SELV2 Status V OUT2 Voltage DDR Type Low 1.2V LPDDR2, LPDDR3 High-Z 1.35V DDR3L High 1.8V DDR2 SELV3 Status V OUT3 Voltage eMPU Type Low 1V SAM9-5 High-Z 1.15V SAM9-6 and SAMA7G High 1.25V SAMA5D2x Note: SELV2 and SELV3 are always hardwired in the final application and they cannot be changed on-the-fly during operation.

DS20006388A-page 20  2020 Microchip Technology Inc. LDO rail is started first (at time t1), by connecting LEN to the VDDIO output (MCP16501D only).

• DDR supply/DDRIO voltage (VDDIODDR) is started next after delay t2. From the MPU perspective, t2 is not mandatory, but it facilitates the use of an external 1.8V DC-DC or LDO for LPDDR2/3 (VDDIODDR being the 1.2V supply of the LPDDR2/3). This DC-DC can be initially sequenced to VDDIO at start-up and maintained on by VDDIODDR for Hibernate mode (backup self-refresh).
• VDDCORE (and VDDCPU for other MPUs) voltages are started last, after a delay of t
• Upon successful start-up of all the rails in the power-up sequence, after delay t4, the Reset signal (nRSTO) is deasserted and software execution can start. The start-up sequence can be initiated in two different ways, also depending on the presence of a back-up supply in the application: 1. nSTRT event (nSTRT pin pulled low), maintained by PWRHLD assertion. In applications with a backup battery, the PWRHLD signal is typically already high before the nSTRT event. 2. A low-to-high transi tion of the PWRHLD signal, regardless of the nSTRT event. This is only possible in applications with backup supply. This mode is typically originated by an external wake-up event asserted by a peripheral device to the MPU Shutdown and Wake-up Controller (SHDWC), which is still powered in Backup mode. Delay t 1 acts as a debouncing delay of the nSTRT event. Therefore, nSTRT must be detected as low continuously during t1 to validate the start-up event and initiate the first sequence step. After the first sequence step is started (at t1), nSTRT can be released to its high level at any time. Also, subsequent high-low-high tog- gling of nSTRT during the execution of the start-up sequence, while visible at the nSTRTO output, will be ignored by the sequencer and it will NOT reset the start-up sequence under execution. The following timing diagram in Figure 4-4 shows the typical sequence for Case 1: FIGURE 4-4: Start-Up from nSTRT Timing Diagram. Note: The nSTRT event needs the assertion of PWRHLD to have the power-up sequence completed successfully. If PWRHLD is not yet high at the time nRSTO is to be asserted, the MCP16501 automatically initiates a turn-off sequence without any positive glitches on nRSTO. Where: t1 = Delay from nSTRT falling to first output VOUT1 starting (default 0.5 ms + device wake-up time, about 100 µs) t2 = Time from V OUT1 established to VOUT2 starting (default 8 ms) t3 = Time from V OUT2 established to VOUT3 starting (default 4 ms) t4 = Time from V OUT3 established to nRSTO deassertion (default 16 ms) t5 = Setup/hold times, min. 0 µs (internal filtering applies)

 2020 Microchip Technology Inc. DS20006388A-page 21 MCP16501 For the different OTP options for the t1 to t4 timings see the respective values in “Configuration Options”. For power supplies starting at t1, additional delay time interval is added to the device wake-up time. The following timing diagram in Figure 4-5 shows the typical sequence for Case 2: FIGURE 4-5: Start-Up from PWRHLD Timing Diagram. For all sequences described above, LPM can be assumed to be low. The MPU will assert LPM after some time, based on software decision, to enter the Low-Power mode. Where: t1 = Delay from PWRHLD asserted to first output VOUT1 starting (default 0.5 ms + device wake-up time, about 100 µs) t2 = Time from V OUT1 established to VOUT2 starting (default 8 ms) t3 = Time from V OUT2 established to VOUT3 starting (default 4 ms) t4 = Time from V OUT3 established to nRSTO deassertion (default 16 ms)

DS20006388A-page 22  2020 Microchip Technology Inc.

4.4.2 POWER-UP SEQUENCE

The start-up sequence is divided into three steps and each Buck regulator is assigned to a specific sequence step:

• Step 1 (Buck1) regulator is started after a delay (t1) from the start-up event. If the start-up event is no longer valid as the instant t1 expires, the start-up sequence is aborted before the first regu- lator is started.
• Step 2 (Buck2) regulator is started after a delay (t2) since the completion of the sequence Step 1 (regulator enabled at Step 1 has been powered up correctly).
• Step 3 (Buck3) regulator is started after a delay 3) from the completion of the sequence Step 2 (regulator enabled at Step 2 has been powered up correctly). The subsequent assertion of nRSTO is determined by the status of all regulators that have been turned on during the power-up sequence Their status is checked before starting counter t 4 and again checked at the expiration of t4 to have nRSTO deasserted. After the completion of the power-up sequence (i.e., at the time instant nRSTO is deasserted), the MCP16501 will enter the Power Modes state machine operation defined by the LPM and PWRHLD signals, and the cor- responding device setting. Some regulators which are supposed to turn on in the power-up sequence may fail to power up correctly. In this case , the sequencing engine adds a 32 ms waiting time to allow the affected regulators to recover. After the expiration of the 32 ms period, if the affected regulators have still not recovered, the start-up sequence is aborted and the MCP16501 returns to its OFF state. The start-up sequence flowchart is described in Figure 4-6 on the next page.

 2020 Microchip Technology Inc. DS20006388A-page 23 MCP16501 FIGURE 4-6: Start-up Sequence Flowchart.

DS20006388A-page 24  2020 Microchip Technology Inc.

4.4.3 DROPOUT SAFE START-UP

The start-up sequence management of MCP16501 ensures predictable timing between subsequent steps, even if some power channels may operate in dropout conditions with moderate loading. This situation might occur for Buck1 because its output voltage range (up to 3.7V) is overlapping the input sup- ply range (2.7V-5.5V). This operating condition is frequently encountered in battery-powered applications. For example, some loads designed for a 3.3V nominal supply voltage may not be able to withstand t he fully replenished battery voltage (around 4.2V), and therefore, they would require a front-end regulator. However, they could still operate when the battery voltage has decreased low enough to push their front-end regulator into dropout. For example, if the battery voltage is around 3.1V and the Buck1 output voltage is also set to 3.3V, it is still desirable to start Buck1 and proceed throughout the start-up sequence, even if the POK (Power OK) threshold for Buck1 may not be reached, since Buck1 is still delivering a voltage within the I/O oper ating voltage range. This would allow a better exploitation of the battery because the cutoff voltage is no longer dictated by the onset of the dropout of the 3.3V regulat or (Buck1) and by its POK threshold. By means of a dedicated circuit that monitors the input-output differential during start-up of the potentially affected regulators, the MCP16501 can still ensure a proper start-up. The MPU can then detect the anomaly (e.g. by measuring the output of Buck1) and decide either to continue operation or to shut down the system. The Start-up POK Bypass Threshold is the relevant “Electrical Characteristics” table parameter that defines the acceptable level of input-output differential, to continue through the star t-up sequence, in lack of the normal POK.

4.4.4 TYPICAL POWER-DOWN

The power-down (shutdown) sequence can be initiated by the MPU by deasserting PWRHLD (LPM being already low or deasserted simultaneously). This method assumes that the MCP16501 is in any operating state (i.e., is outside the start-up sequence). After PWRHLD has been deasserted nRSTO will immediately be asserted low by the MCP16501. After that, all active channels will be turned off, with the exception of the LDO which is controlled by LEN. For the MCP16501D, the LDO will be turned off by virtue of the connection of LEN to VOUT1. The turn-off of each channel also activates the active discharge (if enabled) on the same channel. The timing diagram in Figure 4-7 shows the typical sequence for the power down FIGURE 4-7: Power-Down (Shutdown) Sequence Timing Diagram.

4.4.5 TYPICAL HIBERNATE SEQUENCES

The Hibernate mode entering sequence is similar to the power-down, with the only difference is that LPM will be asserted high by the MP U before deassertion of PWRHLD, or at least at the same time PWRHLD is deasserted (due to internal filtering, the setup time t can be as low as 0 µs). For example, taking the MCP16501A variant into consideration, the V OUT2 rail (and/or other rails which are defined as ON in Hibernate mode by overwriting the default settings) will remain active, while V OUT1 and VOUT3, will be immedi- ately disabled. In Hibernate mode, the DDRx/LPDDRx will typically be in Backup Self-Refresh mode (BSR). The following timing diagram in Figure 4-8 shows the typical Hibernate mode sequence for a device variant that keeps only V OUT2 on in Hibernate mode (such as MCP16501A). Where: t5 = Setup time, LPM = 0 to PWRHLD = 0: Min. 0 µs (internal filtering applies) t6 = Delay from PWRHLD deasserted to nRSTO asserted: Min. 0 µs, max. 10 µs (not a strict requirement) t7 = Delay from nRSTO asserted to first VOUTx turn-off: Min. 0 µs, max. 10 µs (not a strict requirement)

 2020 Microchip Technology Inc. DS20006388A-page 25 MCP16501 FIGURE 4-8: Entering Hibernate Mode Timing Diagram. From the Hibernate state, the system can: 1. Move to OFF state (if LPM also goes low, the VOUT2 can be immediately turned off); or 2. Initiate another start-up sequence (with the exception of Buck2 which is already active) by a low-to-high transition of PWRHLD. The timing diagram of a start-up sequence from Hibernate mode is shown in Figure 4-9. After the assertion of PWRHLD, the MPU may deassert LPM at any time. Due to internal filtering, simultaneous transition of LPM and PWRHLD is allowed (hold time t 5 can be 0 µs). Depending on the time at which LPM is deasserted, the MCP16501 may transition through the Low-Power state or not. FIGURE 4-9: Start-up Sequence Exiting Hibernate Mode Timing Diagram.

4.4.6 RESTART SEQUENCE AFTER

FAULT AND AUTOMATIC WAKE-UP PULSE (AWKP) GENERATION-MCP16501D ONLY Due to the support for LPDDRx, which require correct sequencing between the LPDDRx memory rails, the MCP16501D features a di fferent fault management sequence. This consists in the turn-off of all channels followed by an automatic ally executed restart sequence, which ensures t hat the power rails will be restarted in the correct order. Please see Section 5.4 “Protections” for information on which Faults may trigger a new restart sequence. In the default configuration of the MCP16501D as soon as a Fault is detected, the power delivery on all channels Where: t5 = Setup time, LPM = 1 to PWRHLD = 0: Min. 0 µs (internal filtering applies) t6 = Delay from PWRHLD deasserted to nRSTO asserted: Min. 0 µs, max. 10 µs (not a strict requirement) t 7 = Delay from nRSTO asserted to first VOUTX turn-off: Min. 0 µs, max. 10 µs (not a strict requirement) Note: Upon exit of Hibernate mode, Buck2 is not part of the sequence because it is already on (being in Auto-PFM mode). However, also depending on the instant at which the MPU deasserts LPM, it can toggle to FPWM mode at the time nRSTO is deas- serted. Where: t1 = Delay from PWRHLD asserted to first supply VOUT1 starting (default 0.5 ms) t3 =T i m e f r o m VOUT1 established to VOUT3 starting (default 4 ms) t4 =T i m e f r o m VOUT3, established to nRSTO deassertion (default 16 ms) t5 = Minimum hold time, PWRHLD = 1 to LPM = 0: Min. 0 µs (internal filtering applies)

DS20006388A-page 26  2020 Microchip Technology Inc. is terminated and the MCP16501D waits for 100 ms. After this wait time, a new start-up sequence is gener- ated in the attempt to restart the system correctly. A special feature is provided to enable system recovery if there is a restart sequence after a Fault occurs while in Hibernate mode . In Hibernate mode, the PWRHLD had been previously set to low by the MPU and the MPU expects a wake-up event in order to set PWRHLD to high again. This must be a hardware event, which is flagged to some I/O inside the MPU Shutdown and Wake-up Controller (SHDWC) block (e.g., a logic transition on a WKUPx or PIOBUx pin). However, if a Fault causes a restart sequence while in Hibernate mode, the restart sequence is not success- fully completed until a wake-up event is generated for the MPU SHDWC, because the PWRHLD remains low. It is necessary for the PWRHLD signal to be high just prior to the completion of the start-up sequence so that nRSTO can be deasserted. This is solved by generating from the MCP16501 an Automatic Wake-up Pulse (AWKP) on the nSTRTO output if the Fault that generates a restart sequence has occurred while in Hibernate mode. In the MCP16501D, the AWKP function is enabled by default. The timing diagram of a restart sequence caused by a Fault while in Hibernate mode is shown in Figure 4-10. Just before initiating the restart sequence, the MCP16501D generates a 25 ms (nominal duration) Automatic Wake-up Pulse on the nSTRTO output, even in lack of a low level on the nSTRT input. This is the only situation where the nSTRTO logic level does not reflect the nSTRT input status. The duration of the AWK Pulse erodes into the 100 ms waiting time that precedes the automatic restart sequence. PWRHLD will typically return high as soon as the nSTRTO signal is detected to be low by the MPU SHDWC. If LPM stays high for any reason, the MCP16501D will go in Low-Power mode immediately after the automatic start-up sequence. This behavior is shown in Figure 2-21 in Section 2.0 “Typical Perfor- mance Curves”. If the restart sequence after a Fault is executed in any other operational state but Hibernate, PWRHLD will either be already high (in applications with backup power) or it would return high as soon as the VDDIO rail is started, thus making the generation of the Automatic Wake-up Pulse not necessary. FIGURE 4-10: Automatic Wake-Up Pulse Generation Timing Diagram (Fault during Hibernate). VIN Fault Event PWRHLD Wait 100 ms (internal logic signal) nSTRTO nRSTO time LPM Hibernate Automatic Start-up SequenceState nSTRT 25 ms 100 ms Wait after Fault ACTIVE 75 ms trestart Where: trestart = Duration of the automatic start-up (restart) sequence t5 = Minimum setup/hold time: Min. 0 µs (internal filtering applies)

 2020 Microchip Technology Inc. DS20006388A-page 27 MCP16501

4.5 Configuration Options

The device variants highlighted in Section 4.0 “Device Options” are generated at the factory with One-Time-Programmable memory, which configures default settings at power-up. To accommodate future possible MPUs or application architectures the following configurations can be taken into account to define other device options. TABLE 4-5: DEVICE CONFIGURATION Note 1: [1,2,3]-refers to each individual Buck channel setting Note: Please contact your nearest Microchip Sales Office for further assistance on the development of customized device vari- ants. Setting Description RSTDLY nRSTO assertion delay (t 4 in the start-up sequence); options are: 1 ms, 2 ms, 4 ms, 8 ms, 16 ms, 32 ms, 64 ms and 128 ms; default is 16 ms AWKPDIS Enables or disables the automat ic wake-up pulse; default is enabled VOUT[1,2,3] Buck output voltage, Buck1 output range is between 1.2V and 3.7V with a 50 mV resolution, while Buck2 and Buck3 have an output range between 0.6V and 1.85V with a 25mV resolu- tion EN[1,2,3] Enables or disables each Buck converters for all individual power state MODE[1,2,3] FPWM or Auto PFM for each Buck converters for all individual power state SSR[1,2,3] Soft Start rate for Bu ck converters; options are: 3.125 V/ms, 1.563 V/ms, 1.042 V/ms and 0.781 V/ms; default is 3.125 V/ms SEQ[1,2,3] Startup sequence step for each Buck converter DELAY[1,2,3] Time delay from the co mpletion of the previous Start-Up Sequence Step or Start-Up Event to the turn-on (beginning of Soft Start); option s a r e : 0m s , 0 . 5m s , 1ms, 2 ms, 4 ms, 8 ms, 12 ms, 16 ms B1HCEN Enables or disables the Hysteretic Cont rol Mode for Buck1 in AutoPFM operation; only enabled for MCP16501E HCPEN[1,2,3] Enables or disables the Hiccup short-circ uit protection for each Buck converter; default is enabled with the exception of MCP16501D. When disabled, a short circuit will cause the immediate turn-off of all channels followed by a 100 ms wait time and an automatic restart sequence. DISCH[1,2,3] Enables or disables the active output di scharge when the channel is turned off; default is enabled PHASE[1,2,3] Enables operation 180° out of phase with the oscillator for each Buck

DS20006388A-page 28  2020 Microchip Technology Inc.

4.6 Device Variants Default Settings

The summary of all currently available device variants with their default register settings is shown in Table 4-6 below: Note 1: [1,2,3]-refers to each individual Buck channel setting TABLE 4-6: DEFAULT REGISTERS SETTING S VS. MCP16501 DEVICE VARIANTS Setting Power State SELVx Status Default Settings of MCP16501 Variants ABCDE RSTDLY Irrelevant Irrelevant 16ms 16ms 16ms 16ms 16ms AWKPDIS Irrelevant Irrelevant Enabled Enabled Enabled Enabled Enabled VOUT[1] Irrelevant Irrelevant 3.3V 3V 2.8V 3.3V 3.3V VOUT[3] Irrelevant SELV3 = Low 1V 1V 1V 1V 1V EN[1,2,3] Active Irrelevant Enabled Enabled Enabled Enabled Enabled EN[1,2,3] Low Power Irrelevant Enabled Enabled Enabled Enabled Enabled EN[1,3] Hibernate Irrelevant Disabled Disabled Disabled Disabled Disabled EN[2] Hibernate Irrelevant Enabled Enabled Enabled Enabled Enabled MODE[1,2,3] Active Irrelevant FPWM FPWM FPWM FPWM FPWM MODE[1,2,3] Low Power Irrelevant Auto-P FM Auto-PFM Auto-PFM Auto-PFM Auto-PFM MODE[1,2,3] Hibernate Irrelevant Auto-P FM Auto-PFM Auto-PFM Auto-PFM Auto-PFM SEQ[1] Irrelevant Irrelevant 1st 1st 1st 1st 1st SEQ[2] Irrelevant Irrelevant 2nd 2nd 2nd 2nd 2nd SEQ[3] Irrelevant Irrelevant 3rd 3rd 3rd 3rd 3rd DELAY[2] Irrelevant Irre levant 8ms 8ms 8ms 8ms 8ms DELAY[3] Irrelevant Irre levant 4ms 4ms 4ms 4ms 4ms B1HCEN Irrelevant Irrelevant Disabled Disabled Disabled Disabled Enabled HCPEN[1,3] Irrelevant Irrelevant Enabled Enabled Enabled Disabled Enabled HCPEN[2] Irrelevant Irrelevant Enabled Enabled Enabled Disabled Enabled DISCH[1,2,3] Irrelevant Irrelevant Enabled Enabled Enabled Enabled Enabled PHASE[1,3] Irrelevant Irre levant 180° 180° 180° 180° 180° PHASE[2] Irrelevant Irrelevant 0° 0° 0° 0° 0°

 2020 Microchip Technology Inc. DS20006388A-page 29 MCP16501

5.0 APPLICATION INFORMATION

5.1 Recommended External

Table 5-1 lists possible part numbers that can be used in the MCP16501 application. Please refer to the “Typical Application Circuit” section for component designators’ reference. TABLE 5-1: RECOMMENDED EXTERNAL COMPONENTS Item Part Number Manufacturer Description C1-C3 C1608X5R1A226M080AC TDK Corporation Capacitor, 22 µF, 6.3V/10V, X5R, 20%, Size 0603 GRM188R61A226ME15D Murata Electronics® C1608X5R0J226M080AC TDK Corporation GRM188R60J226MEA0 Murata Electronics JMK107BBJ226MA Taiyo Yuden Co., Ltd. CL10A226MQ8NRNC Samsung Electro-Mechanics America, Inc. 06036D226MAT2A AVX Corporation C4-C6, C8 (for 300 mA max. LDO current), C1005X5R1A475M050BC TDK Corporation Capacitor, 4.7 µF, 10V, X5R, 10%/20%, Size 0402 GRM155R61A475MEAA Murata Electronics LMK105BBJ475MV Taiyo Yuden Co., Ltd. CL05A475M(K)P5NRNC Samsung Electro-Mechanics America, Inc. 0402ZD475MAT2A AVX Corporation C7, C8 (for 150 mA max. LDO current) C1005X5R1A225K050BC TDK Corporation Capacitor, 2.2 µF, 10V/16V, X5R, 10%, Size 0402 GRM155R61C225KE11 Murata Electronics LMK105BJ225KV Taiyo Yuden Co., Ltd. CL05A225KP5NSNC Samsung Electro-Mechanics America, Inc. 0402ZD225KAT2A AVX Corporation R1 RC0402KR-07100KL Yageo Corporation Resistor, 100 k Ω, 5%, Size 0402 R2 RC0402KR-0710K0L Yageo Corporation Resistor, 10 k Ω, 5%, Size 0402 R3 MCMR04X1823FTL Multicomp Inc. Resistor, 182 k Ω, 1%, Size 0402 R4 MCMR04X1823FTL Multicomp Inc. Resistor, 182 k Ω, 1%, Size 0402 L1, L2, L3 MLP2520W1R5MT0S1 TDK Corporation 1.5 µH, 1.8A, 75 m Ω, Size 2520, Multilayer Ferrite LQM2HPN1R5MGH Murata Electronics 1.5 µH, 1.6A, 65 m Ω, Size 2520, Multilayer Ferrite VLS252012CX-1R5M TDK Corporation 1.5 µH, 2.3A, 62 m Ω, Size 2520, Wirewound Ferrite LQH2HPN1R5MGR Murata Electronics 1.5 µH, 1.85A, 87 m Ω, Size 2520, Wirewound Ferrite CDPH28D11FNP-1R5MC Sumida Corporation 1.5 µH, 1.74A, 69 m Ω, Size 3.0 mm x 3.2 mm, Wirewound Ferrite DFE252012P-1R5M=P2 Murata Electronics 1.5 µH, 2.6A, 60 m Ω Max, Size 2520, Metal Alloy DFE252012P-2R2M=P2 Murata Electronics 2.2 µH, 2.2A, 84 m Ω Max, Size 2520, Metal Alloy VLS252012HBX-1R5M-1 TDK Corporation 1.5 µH, 2.5A, 68 m Ω, Size 2520, Metal Alloy VLS252012HBX-2R2M-1 TDK Corporation 2.2 µH, 2.04A, 85 m Ω, Size 2520, Metal Alloy 74438324015 Würth Elektronik 1.5 µH, 2.2A, 82 m Ω, Size 2520, Metal Alloy 74438324022 Würth Elektronik 2.2 µH, 1.6A, 123 m Ω, Size 2520, Metal Alloy 74404024015 Würth Elektronik 1.5 µH, 1.9A, 65 m Ω, Size 2520, Wirewound Ferrite 74405024022 Würth Elektronik 2.2 µH, 1.6A, 100 m Ω, Size 2520, Wirewound Ferrite

DS20006388A-page 30  2020 Microchip Technology Inc.

5.2 Buck1 Hysteretic Control Mode

(HCM)/B1HCEN-MCP16501E only If Buck1 is set in Auto-PFM mode while the input voltage (e.g., a discharging battery) is decreasing and eventually pushing Buck1 to 100% duty cycle (Bypass mode), the operational no-load quiescent current shows some increase due to the augmented switching activity of Buck1. This is intrinsic to the Auto-PFM architecture. The peaking in the quiescent current is in the 1 mA range, and it may or may not be detrimental to the overall system efficiency and/or battery life, depending mostly on the minimum loading of Buck1. If the increase in quiescent current when approaching Bypass mode on Buck1 is an important factor for the application, the user can choose MCP16501E which features a different mode of light load, high-efficiency operation (called Hysteret ic Control mode, HCM), where the output voltage is controlled in a hysteretic fashion between the nominal output voltage and 2.9% of it. This control method significantly reduces the aver- age switching activity of Buck1, especially in the prox- imity of the bypass operatio n, at the expense of an increase of the output ripple amplitude. The user should therefore carefully evaluate the need for Hysteretic Control Mo de and balance the increase in output ripple against the real benefit achieved in pro- longing battery life. If the minimum loading on Buck1 is always significantly higher than 1 mA, HCM is typically not needed. The relevant EC Table parameter that defines the upper voltage regulation threshold (typically +2.9% of the nominal output voltage) is the Hysteretic Control Mode Upper Regulation Threshold. HCM mode will only be activated when the input-to-out- put voltage differential decreases below a certain value. This is done to prev ent fast inductor charging, which in turn may cause a poorer control of the effec- tive upper regulation voltage. The relevant “Electrical Characteristics” table parameter that defines the input voltage threshold (fall- ing input voltage), below which HCM is enabled, is the Hysteretic Control Mode Enable Threshold and it is also expressed as a percentage of the nominal output voltage value (typically, +9%).

5.3 LPDDR2 Support with Hibernate

To support LPDDR2 applicat ions, which require two power supplies, the LDO block is used for the genera- tion of the 1.8V of LPDDR2. In the case of the MCP16501D the LDO is partially included in the internal States machine such that the LDO stays on during Hibernate mode. The LDO LEN pin must be connected to rail V OUT1 (VDDIO) such that the LDO (1.8V for LPDDR2) will immediately turn on after the VDDIO rail and before Buck2 (1.2V for LPDDR2), according to the LPDDR2 power-up specifications. In this particular application the SELV2 will be con- nected to GND in order to have VOUT2 regulated to 1.2V for VDD2/VDDCA/VDDQ of LPDDR2, while the LDO feedback resistors (R3 and R4) will be selected to be equal, so that the LDO output is regulated to 1.8V for the LPDDR2 VDD1 rail. The “Typical Application Circuit” section highlights this specific use case. In the particular case of the MCP16501D, HCPEN is disabled, such that any short circuit event on one of the channels will trigger a turn off of all the channels and a startup procedure. This method ensures proper re-sequencing of the LPDDR2 supply rails, regardless of the particular channel being affected by short-circuit.

5.4 Protections

The MCP16501 offers the following:

• Thermal Shutdown
• Overcurrent Protection Thermal Shutdown protection will immediately termi- nate power delivery on all channels when the die temperature exceeds the upper Thermal Shutdown threshold. At the same time, nRSTO will be asserted low. After the die temperature has decreased below the lower Thermal Shutdown threshold (hysteresis = 20°C) and an additional 100 ms delay, the MCP16501 will automatically attempt a new start-up sequence without the need of an external Start condition (from nSTRT or PWRLHD).

5.4.1 OVERCURRENT PROTECTION

(BUCK CHANNELS) The overcurrent protection consists of a cycle-by-cycle, high-side current limit with di gital filtering, followed by the Hiccup mode for protecti on against short-circuit conditions. The cycle-by-cycle, high-side current limit includes frequency foldback. Because of Leading-Edge Blank- ing (LEB) in Peak Current mode control, frequency foldback (with a factor = 4) is used to allow more time for inductor discharge and prevent current runaway in a deep overload condition. Frequency foldback operation is entered when: 1. A high-side current limit event has been detected; and 2. The feedback voltage is less than 500 mV (typical).

 2020 Microchip Technology Inc. DS20006388A-page 31 MCP16501 Cycle-by-cycle overcurrent protection with frequency foldback is always active and it is the first current limit protection mechanism. The second current limit mechanism is Hiccup mode protection, which is also always enabled , including during the soft start ramp. Since the Hiccup mode protection is also active during soft start, there will be a limitation on the maximum simultaneous DC and capacitive loading to ensure that the Hiccup mode protection will not be engaged during the soft start ramp. This is further explained in Section 5.5 “Maximum Simultaneous Capacitive and DC Loading in Soft Start”. Hiccup mode is invoked based on digital counting of High-Side Overcurrent (HS OC) events, regardless of the frequency at which they take place (full switching frequency or foldback switching frequency). Each time the overcurrent protection detects a high-side current limit even t, the current on-time is terminated and a HS OC event counter is incremented. The length of the counter is four bits. If the counter reaches its End-of-Count (EOC) while the instantaneous value of the PO K signal is still low, the Buck converter is turned off (both high-side and low-side transistors are turned off) and Hiccup mode protection is triggered. The intervention of Hiccup mode on any of the Buck channels can have two different behaviors, depending on the HCPEN status of the channel affected by overcur- rent conditions. By default all device options of the MCP16501 come with HCPEN enabled, with the excep- tion of MCP16501D. If HCPEN is disabled, the intervention of Hiccup mode will immediately terminate the power delivery on all channels, including LDO. At the same time, nRSTO will be asserted low. After a 100 ms delay, the MCP16501D will automati- cally attempt a new start-up sequence without the need of an external Start condition (from nSTRT or PWRHLD). If HCPEN is enabled, the intervention of Hiccup mode only affects the responsible Buck channel. All other channels will continue to operate normally. If the affected channel is part of the power-up sequence, nRSTO will be asserted low. The affected channel will be kept off for a certain Hiccup time (t HICCUP), which corresponds to 3x soft start time on that channel, and after the Hiccup time, a new soft start is attempted. If the short-circuit condition is removed and the affected channel resumes normal operation, nRSTO will be asserted high after the Reset delay (t4). The HS OC event counter is reset only after 15 consecutive HS turn-on pulses without any overcurrent event. This counting is done by the Reset counter. Note that all counting is switching event-based, so it is not relevant if the switching takes place at fsw or at fsw/4 (i.e., in frequency foldback). The Hiccup mode flowchart is detailed in Figure 5-1.

DS20006388A-page 32  2020 Microchip Technology Inc. FIGURE 5-1: Hiccup Mode Protection Flowchart. HS OC Event Detected in Current TON? LS Turn-Off HS Turn-On (clocked event) START N Y HS OC Event Counter = EOC? N Y Clear HS OC Event Counter Hiccup Sequence Reset Counter = EOC? Y Idle Loop in Normal Operation Clear HS OC Events Counter and Reset Counter Turn-Off HS and LS Wait tHICCUP LEB Increment Reset Counter Y Clear Reset Counter Increment HS OC Event Counter N Terminate Current TON HCPEN = 1 Y Restart Sequence N Turn-Off ALL Channels Wait 100 ms Comparator POK = 0 Y N tHICCUP = 3 x Soft Start Duration

 2020 Microchip Technology Inc. DS20006388A-page 33 MCP16501

5.4.2 PWM MODE NEGATIVE CURRENT

LIMIT PROTECTION (BUCK CHANNELS) The Buck channels of the MCP16501 also feature a negative inductor current limit protection when operat- ing in Forced PWM mode. This prevents dangerous current levels in the power train. If the inductor current reaches the low-side Negative Peak Current Limit LIM_NEGx) while the low-side MOSFET is conducting, the low-side MOSFET is turned off and the inductor current is pushed to the in put voltage, either through the body diode of the high-side MOSFET (if off) or its channel (when turned on by the control loop). The intervention of this protection does not cause the asser- tion of the nRSTO (Reset) signal. This protection should never be exercised continuously and/or without a large input bulk capacitor, because it may quickly destroy the device. When this protection is engaged, energy is pumped back from the output into the input voltage. If the input supply has no sinking capability and/or the input bulk decoupling cap is not large enough, the input voltage will rise to the point where the device is permanently damaged.

5.4.3 LDO CURRENT LIMIT PROTECTION

The LDO is protected against short circuit by a linear constant-voltage/constant-current (i.e., brick wall) output characteristic. The output current under short-circuit conditions is not intermitt ent. Therefore, the internal power dissipation in the MCP16501 can reach high levels under LDO short-circuit conditions. The interven- tion of the LDO current limit protection by itself does not cause the assertion of the nRSTO (Reset) signal.

5.5 Maximum Simultaneous

Capacitive and DC Loading in Soft Start The Current-mode architecture of the Buck channels in the MCP16501 make them tolerant to additional capacitive loads from the stability point of view. However, since the Hiccup mode overcurrent protection is also enabled during soft start, the user needs to be aware that additional load capacitance, distributed on the application board, may cause the intervention of the Hiccup mode protections under dynamic conditions (ris- ing output voltage). This is especially important for Buck1 since the I/O rail (typically 3.3V) can be used for a wide variety of loads and its total distributed capacitive load could significantly exceed the minimum recommended nominal capacitance value (i.e., 22 µF). Using the symbols listed in the “AC/DC Characteristics” table, Equation 5-1 establishes the maximum allowable capacitive load, C add_max, to prevent the cycle-by-cycle current limit from being engaged. Complying with this condition will ensure that Hiccup mode overcurrent protection will not be activated during the soft start ramp. Failing to comply with the condition formulated below does not necessarily mean that Hiccup mode protection will be engaged. The digital filtering provided in the Hiccup mode overcurrent algorithm, as described in Section 5.4.1 “Overcurrent Protection (Buck Channels)”, provides immunity to single, and even multiple cycle-by-cycle current limit events and allows operation in proximity of the high-side current limit for a significant amount of time during the soft start. EQUATION 5-1: As a consequence, the maximum value of additional capacitance, C add_max, that can be observed by experiments is significant ly higher than the limit calculated with the aforementioned formula. Cadd _max ILIM _HS  1 Where: ILIM_HS = High-Side MOSFET Current Limit r = Ratio of the peak inductor current, ILpk, to average inductor current at the point where ILpk =I LIM_HS. For simplicity, assume r = 1 since the peak-to-peak inductor current ripple will be small in comparison to the average inductor current value when the high-side current limit is engaged. IOUT = Output Current of the Buck Converter SSR = Soft Start Rate COUT = Output capacitance already present on the Buck converter output (typically, COUT =2 2 µ F )

DS20006388A-page 34  2020 Microchip Technology Inc. 5.6 nSTRT Capacitor for Automatic Turn-On on VIN Ramping As shown in Figure 4-1, it is possible to configure the MCP16501 for automatic st art-up upon input voltage (VIN) ramping/power cycling by connecting a capacitor on pin nSTRT. The purpose of the capacitor (C in Figure 4-1) is to delay the rise of the nSTRT pin when VIN ramps up, such that af ter the VIN pin voltage (connected to VIN) has stabilized, the logic level of the nSTRT pin will still be low long enough to be interpreted as a valid start-up event (i.e., longer than t 1; see Section 4.4.1 “Typical Power-up Sequence and Timing”). Under the assumption that the V IN ramping is much shorter than the rise time of the nSTRT pin voltage, the recommended amount of capacitance needed for generation of a valid start- up event is given by the formula in Equation 5-2: EQUATION 5-2: After the selection of capa citor C, the resulting C RPU_nSTRT time constant must be compared to the actual VIN ramping time to verify that indeed the nSTRT rise time is much slower. The time constant C RPU_nSTRT should be at least one order of magnitude larger than the slowest VIN ramping time expected in the application. If this is not true, the capacitor value C must be increased further. Using a 1 µF capacitor for C, the C R PU_nSTRT time constant will be 40 ms, which is adequate for VIN ramping times in the ms range. C t1 Δt+ RPU _nSTRT e VIN log⋅ t1 Δt+ RPU _nSTRT e 1 log⋅ t1 Δt+ RPU _nSTRT Where: RPU_nSTRT = nSTRT Pin Pull-up Resistance (40 k Ω typical value) VIL_nSTRT = nSTRT Logic Low Input Voltage (0.36 V IN, maximum value) VIN = Input Voltage (VIN pin is connected to the voltage V IN) t1 = Delay from nSTRT Falling to First Output V OUT1 Starting (≈ 0.5 ms); see Section 4.4.1 “Typical Power-up Sequence and Timing” Δt = Additional Delay from VIN Voltage establishe d to the Detection of a Logic Low Level on nSTRT (due to internal logic wake-up time): ≈ 100 µs

 2020 Microchip Technology Inc. DS20006388A-page 35 MCP16501

6.0 PACKAGE MARKING INFORMATION

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part num ber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. MCP16501 4x4m m V Q F N - 2 4 Example PIN 1 PIN 1 16501B E/RMB 021256

DS20006388A-page 36  2020 Microchip Technology Inc. BA 0.15 C 0.15 C

0.10 C A B

0.05 C (DATUM B) (DATUM A) CSEATING PLANE NOTE 1 2X TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing C04-21387 Rev A Sheet 1 of 2 24X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 24-Lead Very Thin Plastic Quad Flat, No Lead Package (RMB) - 4x4 mm Body [VQFN] Atmel Legacy Global Package Code ZZP E E e e/2 L K 0.25 24X b (A3) A N

 2020 Microchip Technology Inc. DS20006388A-page 37 MCP16501 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Microchip Technology Drawing C04-21387 Rev A Sheet 2 of 2 24-Lead Very Thin Plastic Quad Flat, No Lead Package (RMB) - 4x4 mm Body [VQFN] Atmel Legacy Global Package Code ZZP Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.50 BSC

0.203 REF

0.30 0.18 0.00 0.25 0.40

4.00 BSC

0.50 0.30 0.90 0.05 MAX K- 0.20 -Terminal-to-Exposed-Pad Overall Length Exposed Pad Length D D2 2.60 2.70 2.80 2.60 2.70 2.80

DS20006388A-page 38  2020 Microchip Technology Inc. RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Contact Pad Spacing Optional Center Pad Length Contact Pitch 2.80 2.80 MILLIMETERS E MAX 4.00 Contact Pad Length (X24) Contact Pad Width (X24) 0.80 0.30 NOM C1Contact Pad Spacing 4.00 Contact Pad to Contact Pad (X20) G2 0.20 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Contact Pad to Center Pad (X24) G1 0.20 EV EV E ØV SILK SCREEN Microchip Technology Drawing C04-23387 Rev A 24-Lead Very Thin Plastic Quad Flat, No Lead Package (RMB) - 4x4 mm Body [VQFN] Atmel Legacy Global Package Code ZZP

 2020 Microchip Technology Inc. DS20006388A-page 39 MCP16501 APPENDIX A: REVISION HISTORY Revision A (July 2020)

• Initial release of this document.

DS20006388A-page 40  2020 Microchip Technology Inc. NOTES:

 2020 Microchip Technology Inc. DS20006388A-page 41 MCP16501 NOTES:

DS20006388A-page 41  2020 Microchip Technology Inc. PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. /XX PackageDevice Device: MCP16501 Cost and Size Optimized PMIC Tape and Reel Option: Blank T Standard packaging (tube or tray) Tape and Reel (1) Device Option: A B C D E A option B option C option D option E option Junction Temperature Range: E = -40°C to +125°C (Extended) Package RMB = 24-Lead Very Thin Plastic Quad Flat, No Lead (VQFN) Package- 4x4 mm Body Examples: a) MCP16501A-E/RMB: Cost and Size Optimized PMIC, A Option, -40°C to +125°C, 24-Lead 4 x 4 VQFN package b) MCP16501TA-E/RMB: Cost and Size Optimized PMIC, Tape and Reel, A Option, -40°C to +125°C, 24-Lead 4 x 4 VQFN package Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. X(1) Tape and Reel Option X Junction Temperature Range X Option Device

 2020 Microchip Technology Inc. DS20006388A-page 42 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-6449-5 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of pr oducts is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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