LMK02000 TI1 | Alldatasheet

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OSCin* R Divider Phase Detector N Divider CLKout0 CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* CLKout4 CLKout4* CLKout5 CLKout5* CLKout6 CLKout6* CLKout7 CLKout7* Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Distribution Path CLK DATA LE Control Registers PWire Port Device Control LDGOE SYNC* Fin Fin* Charge Pump CPout Low Clock Buffers High Clock Buffers LMK02000 www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 PrecisionClockConditionerwithIntegratedPLL Check forSamples: LMK02000 1FEATURES DESCRIPTION The LMK02000 precisionclockconditionercombines 2• 20 fsAdditiveJitter the functions of jittercleaning/reconditioning,• IntegratedInteger-NPLL withOutstanding multiplication,and distributionof a referenceclock.NormalizedPhase Noise Contributionof-224 The deviceintegratesa highperformanceInteger-N dBc/Hz Phase Locked Loop (PLL),three LVDS, and five LVPECL clockoutputdistributionblocks.• Clock Output Frequency Range of1 to800 MHz Each clock distributionblock includes a

  • 3 LVDS and 5 LVPECL Clock Outputs programmable divider,a phase synchronization circuit,a programmable delay,a clockoutputmux,• DedicatedDividerand Delay Blocks on Each and an LVDS or LVPECL outputbuffer.ThisallowsClock Output multipleinteger-relatedand phase-adjustedcopiesof• Pin Compatible FamilyofClockingDevices the referenceto be distributedto eight system
  • 3.15to3.45V Operation components.
  • Package: 48 Pin WQFN (7.0x 7.0x 0.8mm) The clock conditionercomes in a 48-pin WQFN package and is footprintcompatible with other TARGET APPLICATIONS clockingdevicesinthesame family.
  • Data ConverterClocking
  • Networking,SONET/SDH, DSLAM
  • WirelessInfrastructure
  • Medical
  • Testand Measurement
  • Military/Aerospace FunctionalBlock Diagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2007,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* GND SYNC* OSCin OSCin* CPout Fin Fin* Bias CLKout4 CLKout4* CLKout5 CLKout5* CLKout6 CLKout6* CLKout7 CLKout7* WQFN-48 Top Down View 4748 46 45 44 43 42 41 40 39 38 37 1413 15 16 17 18 19 20 21 22 23 24 DAP LMK02000 SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com Connection Diagram Figure1. 48-PinWQFN Package Pin Descriptions Pin # Pin Name I/O Description 1,25 GND - Ground 2,7 NC - No Connectiontothesepins 3,8,13,16,19,22,26, Vcc1,Vcc2,Vcc3,Vcc4,Vcc5,Vcc6,Vcc7,Vcc8, - Power Supply30,31,33,37,40,43,46 Vcc9,Vcc10,Vcc11,Vcc12,Vcc13,Vcc14

4 CLKuWire I MICROWIRE ClockInput

5 DATAuWire I MICROWIRE Data Input

6 LEuWire I MICROWIRE LatchEnableInput

9,10 LDObyp1, LDObyp2 - LDO Bypass

11 GOE I GlobalOutputEnable

12 LD O Lock Detectand TestOutput

14,15 CLKout0,CLKout0* O LVDS ClockOutput0 17,18 CLKout1,CLKout1* O LVDS ClockOutput1 20,21 CLKout2,CLKout2* O LVDS ClockOutput2 23,24 CLKout3,CLKout3* O LVPECL ClockOutput3

27 SYNC* I GlobalClockOutputSynchronization

28,29 OSCin, OSCin* I OscillatorClockInput;Must be AC coupled

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www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 Pin Descriptions(continued) Pin # Pin Name I/O Description

32 CPout O Charge Pump Output

34,35 Fin,Fin* I FrequencyInput;Must be AC coupled

36 Bias I BiasBypass

38,39 CLKout4,CLKout4* O LVPECL ClockOutput4 41,42 CLKout5,CLKout5* O LVPECL ClockOutput5 44,45 CLKout6,CLKout6* O LVPECL ClockOutput6 47,48 CLKout7,CLKout7* O LVPECL ClockOutput7 DAP DAP - DieAttachPad isGround These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2)(3) Parameter Symbol Ratings Units Power SupplyVoltage VCC -0.3to3.6 V InputVoltage VIN -0.3to(VCC + 0.3) V StorageTemperatureRange TSTG -65to150 °C Lead Temperature(solder4 s) TL +260 °C JunctionTemperature TJ 125 °C (1) "AbsoluteMaximum Ratings"indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) Thisdeviceisa highperformanceintegratedcircuitwithESD handlingprecautions.Handlingofthisdeviceshouldonlybe done atESD protectedwork stations.The deviceisratedtoa HBM-ESD of> 2 kV,a MM-ESD of> 200 V,and a CDM-ESD of> 1.2kV. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Parameter Symbol Min Typ Max Units AmbientTemperature TA -40 25 85 °C Power SupplyVoltage VCC 3.15 3.3 3.45 V Package Thermal Resistance Package θJA θJ-PAD (ThermalPad) 48-LeadWQFN (1) 27.4° C/W 5.8° C/W (1) Specificationassumes 16 thermalviasconnectthedieattachpad totheembedded copperplaneon the4-layerJEDEC board.These viasplaya key roleinimprovingthethermalperformanceoftheWQFN. Itisrecommended thatthemaximum number ofviasbe used in theboardlayout. Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMK02000

SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com ElectricalCharacteristics(1) (3.15V ≤ Vcc ≤ 3.45V,-40°C ≤ TA ≤ 85 °C, DifferentialInputs/Outputs;exceptas specified.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproduct characterizationand arenotspecified). Symbol Parameter Conditions Min Typ Max Units CurrentConsumption Entiredevice;CLKout0 & CLKout4 145.8enabledinBypass ModePower SupplyCurrentICC mA(2) Entiredevice;AllOutputsOff(no 70emitterresistorsplaced) ICC PD Power Down Current POWERDOWN = 1 1 mA ReferenceOscillator ReferenceOscillatorInputFrequencyfOSCin square 1 200 MHzRange forSquare Wave AC coupled;Differential(VOD ) Square Wave InputVoltageforOSCin andVOSCin square 0.2 1.6 VppOSCin* Frequency Input fFin FrequencyInputFrequencyRange 1 800 MHz SLEW Fin FrequencyInputSlew Rate (3)(4)0.5 V/ns DUTY Fin FrequencyInputDutyCycle 40 60 % PFin InputPower Range forFinorFin* AC coupled -13 8 dBm PLL fCOMP Phase DetectorFrequency 40 MHz VCPout = Vcc/2,PLL_CP_GAIN = 1x 100 VCPout = Vcc/2,PLL_CP_GAIN = 4x 400 ISRCE CPout Charge Pump SourceCurrent µA VCPout = Vcc/2,PLL_CP_GAIN = 16x 1600 VCPout = Vcc/2,PLL_CP_GAIN = 32x 3200 VCPout = Vcc/2,PLL_CP_GAIN = 1x -100 VCPout = Vcc/2,PLL_CP_GAIN = 4x -400 ISINKCPout Charge Pump SinkCurrent μA VCPout = Vcc/2,PLL_CP_GAIN = 16x -1600 VCPout = Vcc/2,PLL_CP_GAIN = 32x -3200 ICPoutTRI Charge Pump TRI-STATE Current 0.5V < VCPout < Vcc -0.5V 2 10 nA MagnitudeofCharge Pump VCPout = Vcc /2ICPout%MIS 3 %Sinkvs.SourceCurrentMismatch TA = 25°C MagnitudeofCharge Pump 0.5V < VCPout < Vcc -0.5VICPoutVTUNE 4 %Currentvs.Charge Pump VoltageVariationTA = 25°C MagnitudeofCharge Pump Currentvs.ICPoutTEMP 4 %TemperatureVariation PLL_CP_GAIN = 1x -117PLL 1/fNoiseat10 kHz Offset(5) PN10kHz dBc/HzNormalizedto1 GHz OutputFrequency PLL_CP_GAIN = 32x -122 (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) See CURRENT CONSUMPTION /POWER DISSIPATION CALCULATIONS formore currentconsumption/power dissipation calculationinformation. (3) Forallfrequenciestheslewrate,SLEW Fin,ismeasured between 20% and 80%. (4) Specificationisensuredby characterizationand isnottestedinproduction. (5) A specificationinmodelingPLL in-bandphase noiseisthe1/fflickernoise,LPLL_flicker(f),whichisdominantclosetothecarrier.Flicker noisehas a 10 dB/decadeslope.PN10kHz isnormalizedtoa 10 kHz offsetand a 1 GHz carrierfrequency.PN10kHz = LPLL_flicker(10 kHz)-20log(Fout/1 GHz),where LPLL_flicker(f)isthesinglesideband phase noiseofonlytheflickernoise's contributiontototalnoise, L(f).To measure LPLL_flicker(f)itisimportanttobe on the10 dB/decadeslopeclosetothecarrier.A highphase detectorfrequencyand a cleancrystalareimportanttoisolatingthisnoisesourcefromthetotalphase noise,L(f).LPLL_flicker(f)can be masked by thereference oscillatorperformanceifa lowpower ornoisysourceisused.The totalPLL inbandphase noiseperformanceisthesum ofLPLL_flicker(f) and LPLL_flat(f).

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www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 ElectricalCharacteristics(1)(continued) (3.15V ≤ Vcc ≤ 3.45V,-40°C ≤ TA ≤ 85 °C, DifferentialInputs/Outputs;exceptas specified.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproduct characterizationand arenotspecified). Symbol Parameter Conditions Min Typ Max Units PLL_CP_GAIN = 1x -219NormalizedPhase NoiseContributionPN1Hz dBc/Hz(6) PLL_CP_GAIN = 32x -224 Clock DistributionSection(7)-LVDS Clock Outputs (CLKout0 toCLKout2) CLKoutX_MUX = 20R L = 100 Ω Bypass DistributionPath= CLKoutX_MUX =JitterADD AdditiveRMS Jitter(7) 800 MHz fs DividedBandwidth= 75CLKoutX_DIV =12 kHz to20 MHz Equalloadingand identicalclock tSKEW CLKoutX toCLKoutY (4) configuration -30 ±4 30 ps R L = 100 Ω VOD DifferentialOutputVoltage R L = 100 Ω 250 350 450 mV Change inmagnitudeofVOD forΔVOD R L = 100 Ω -50 50 mVcomplementaryoutputstates VOS OutputOffsetVoltage R L = 100 Ω 1.070 1.25 1.370 V Change inmagnitudeofVOS forΔVOS R L = 100 Ω -35 35 mVcomplementaryoutputstates ISA ClockOutputShortCircuitCurrent Singleended outputsshortedtoGND -24 24 mAISB singleended ClockOutputShortCircuitCurrentISAB Complementaryoutputstiedtogether -12 12 mAdifferential Clock DistributionSection(7)-LVPECL Clock Outputs (CLKout3 toCLKout7) CLKoutX_MUX = 20R L = 100 Ω Bypass DistributionPath= CLKoutX_MUX =JitterADD AdditiveRMS Jitter(7) 800 MHz fs DividedBandwidth= 75CLKoutX_DIV =12 kHz to20 MHz Equalloadingand identicalclock tSKEW CLKoutX toCLKoutY (8) configuration -30 ±3 30 ps Termination= 50 Ω toVcc -2 V Vcc -VOH OutputHighVoltage V0.98 Termination= 50 Ω toVcc -2 V Vcc -VOL OutputLow Voltage V1.8 VOD DifferentialOutputVoltage 660 810 965 mV DigitalLVTTL Interfaces(9) VIH High-LevelInputVoltage 2.0 Vcc V VIL Low-LevelInputVoltage 0.8 V IIH High-LevelInputCurrent VIH = Vcc -5.0 5.0 µA IIL Low-LevelInputCurrent VIL= 0 -40.0 5.0 µA Vcc -VOH High-LevelOutputVoltage IOH = +500 µA V0.4 (6) A specificationinmodelingPLL in-bandphase noiseistheNormalizedPhase NoiseContribution,LPLL_flat(f),ofthePLL and isdefined as PN1Hz = LPLL_flat(f)– 20log(N)– 10log(fCOMP ).LPLL_flat(f)isthesinglesideband phase noisemeasured atan offsetfrequency,f,ina 1 Hz Bandwidthand fCOMP isthephase detectorfrequencyofthesynthesizer.LPLL_flat(f)contributestothetotalnoise,L(f).To measure LPLL_flat(f)theoffsetfrequency,f,must be chosen sufficientlysmallerthentheloopbandwidthofthePLL,and yetlargeenough toavoid a substantialnoisecontributionfromthereferenceand flickernoise.LPLL_flat(f)can be masked by thereferenceoscillatorperformanceif a lowpower ornoisysourceisused. (7) The ClockDistributionSectionincludesallpartsofthedeviceexceptthePLL section.TypicalAdditiveJitterspecificationsapplytothe clockdistributionsectiononly. (8) Specificationisensuredby characterizationand isnottestedinproduction. (9) AppliestoGOE, LD, and SYNC*. Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMK02000

SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com ElectricalCharacteristics(1)(continued) (3.15V ≤ Vcc ≤ 3.45V,-40°C ≤ TA ≤ 85 °C, DifferentialInputs/Outputs;exceptas specified.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproduct characterizationand arenotspecified). Symbol Parameter Conditions Min Typ Max Units VOL Low-LevelOutputVoltage IOL = -500µA 0.4 V DigitalMICROWIRE Interfaces(10) VIH High-LevelInputVoltage 1.6 Vcc V VIL Low-LevelInputVoltage 0.4 V IIH High-LevelInputCurrent VIH = Vcc -5.0 5.0 µA IIL Low-LevelInputCurrent VIL= 0 -5.0 5.0 µA MICROWIRE Timing tCS Data toClockSetUp Time See Data InputTiming 25 ns tCH Data toClockHoldTime See Data InputTiming 8 ns tCWH ClockPulseWidthHigh See Data InputTiming 25 ns tCWL ClockPulseWidthLow See Data InputTiming 25 ns tES ClocktoEnableSetUp Time See Data InputTiming 25 ns tCES EnabletoClockSetUp Time See Data InputTiming 25 ns tEWH EnablePulseWidthHigh See Data InputTiming 25 ns (10)AppliestoCLKuWire,DATAuWire, and LEuWire. SerialData Timing Diagram Data bitsseton theDATAuWire signalare clockedintoa shiftregister,MSB first,on each risingedge ofthe CLKuWire signal.On the risingedge of the LEuWire signal,the data issent from the shiftregisterto the addressedregisterdeterminedby theLSB bits.Aftertheprogramming iscompletetheCLKuWire, DATAuWire, and LEuWire signalsshouldbe returnedtoa lowstate.

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www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 Charge Pump CurrentSpecificationDefinitions I1= Charge Pump SinkCurrentatVCPout = Vcc -ΔV I2= Charge Pump SinkCurrentatVCPout = Vcc/2 I3= Charge Pump SinkCurrentatVCPout = ΔV I4= Charge Pump SourceCurrentatVCPout = Vcc -ΔV I5= Charge Pump SourceCurrentatVCPout = Vcc/2 I6= Charge Pump SourceCurrentatVCPout = ΔV ΔV = Voltageoffsetfromthepositiveand negativesupplyrails.Definedtobe 0.5V forthisdevice. Charge Pump Output CurrentMagnitude Variationvs.Charge Pump Output Voltage Charge Pump Sink Currentvs.Charge Pump Output Source CurrentMismatch Charge Pump Output CurrentMagnitude Variationvs.Temperature Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMK02000

SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com Charge Pump CurrentSpecificationDefinitions(continued) FunctionalDescription The LMK02000 precisionclockconditionercombines thefunctionsofjittercleaning/reconditioning,multiplication, and distributionofa referenceclock.The deviceintegratesa highperformanceInteger-NPhase Locked Loop (PLL),threeLVDS, and fiveLVPECL clockoutputdistributionblocks. Each clockdistributionblockincludesa programmabledivider,a phase synchronizationcircuit,a programmable delay,a clockoutputmux, and an LVDS or LVPECL outputbuffer.This allowsmultipleinteger-relatedand phase-adjustedcopiesofthereferencetobe distributedtoeightsystemcomponents. The clockconditionercomes ina 48-pinWQFN package and isfootprintcompatiblewithotherclockingdevices inthesame family. BIAS PIN To properlyuse thedevice,bypass Bias(pin36) witha low leakage1 µF capacitorconnectedtoVcc.Thisis importantforlownoiseperformance. LDO BYPASS To properlyuse thedevice,bypass LDObyp1 (pin9)witha 10 µF capacitorand LDObyp2 (pin10)witha 0.1µF capacitor. OSCILLATOR INPUT PORT (OSCin,OSCin*) The purposeofOSCin istoprovidethePLL witha referencesignal.The OSCin portmust be AC coupled,refer to the System LevelDiagram in the ApplicationInformationsection.The OSCin portmay be drivensingle endedlyby AC groundingOSCin* witha 0.1µF capacitor. FREQUENCY INPUT PORT (Fin,Fin*) The purposeofFinistoprovidethePLL witha feedbacksignalfroman externaloscillator.The Finportmay be drivensingleendedlyby AC groundingFin*. CLKout DELAYS Each individualclockoutputincludesa delayadjustment.Clockoutputdelayregisters(CLKoutX_DLY) supporta 150 ps stepsizeand rangefrom0 to2250 ps oftotaldelay. LVDS/LVPECL OUTPUTS Each LVDS or LVPECL outputmay be disabledindividuallyby programming the CLKoutX_EN bits.Allthe outputsmay be disabledsimultaneouslyby pullingtheGOE pinloworprogrammingEN_CLKout_Globalto0. GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pinsynchronizesthe clockoutputs.When the SYNC* pinisheldina logiclow state,the divided outputsarealsoheldina logiclow state.When theSYNC* pingoes high,thedividedclockoutputsareactivated and willtransitiontoa highstatesimultaneously.Clocksinthebypassed stateare notaffectedby SYNC* and arealwayssynchronizedwiththedividedoutputs.

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SYNC* CLKout0 CLKout1 CLKout2 LMK02000 www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 The SYNC* pinmust be heldlow forgreaterthanone clockcycleoftheFrequencyInputport,alsoknown as the distributionpath.Once thislow eventhas been registered,theoutputswillnotreflectthelow stateforfourmore cycles.Similarlyonce theSYNC* pinbecomes high,theoutputswillnotsimultaneouslytransitionhighuntilfour more distributionpathclockcycleshave passed.See thetimingdiagrambelow forfurtherdetail.Inthetiming diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2,CLKout2_MUX = Divided,and CLKout2_DIV = 4. SYNC* Timing Diagram The SYNC* pinprovidesan internalpull-upresistoras shown on thefunctionalblockdiagram.IftheSYNC* pin isnot terminatedexternallythe clockoutputswilloperatenormally.Ifthe SYNC* functionisnot used,clock outputsynchronizationisnotspecified. CLKout OUTPUT STATES Each clockoutputmay be individuallyenabledwiththeCLKoutX_EN bits.Each individualoutputenablecontrol bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). Allclockoutputscan be disabledsimultaneouslyifthe GOE pin is pulledlow by an externalsignalor EN_CLKout_Globalissetto0. CLKoutX EN_CLKout GOE pin Clock X Output State _EN bit _Globalbit 1 1 Low Low Don'tcare 0 Don'tcare Off

0 Don'tcare Don'tcare Off

1 1 High/No Connect Enabled When an LVDS outputisinthe Offstate,the outputsare at a voltageof approximately1.5 volts.When an LVPECL outputisintheOffstate,theoutputsareata voltageofapproximately1 volt. GLOBAL OUTPUT ENABLE AND LOCK DETECT The GOE pinprovidesan internalpull-upresistor.Ifitisnotterminatedexternally,theclockoutputstatesare determinedby theClockOutputEnablebits(CLKoutX_EN) and theEN_CLKout_Globalbit. By programming the PLL_MUX registerto DigitalLock DetectActiveHigh (See PLL_MUX[3:0] --Multiplexer ControlforLD Pin),theLock Detect(LD)pincan be connectedtotheGOE pininwhichcase alloutputsareset lowautomaticallyifthesynthesizerisnotlocked. POWER ON RESET When supplyvoltagetothedeviceincreasesmonotonicallyfrom ground toVcc,thepower on resetcircuitsets allregistersto theirdefaultvalues,see RESET Bit--R0 onlyformore informationon defaultregistervalues. Voltageshouldbe appliedtoallVcc pinssimultaneously. Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMK02000

SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com GeneralProgramming Information The LMK02000 deviceisprogrammed usingseveral32-bitregisterswhich controlthe device'soperation.The registersconsistofa datafieldand an addressfield.The last4 registerbits,ADDR[3:0]formtheaddressfield. The remaining28 bitsformthedatafieldDATA[27:0]. Duringprogramming,LEuWire islow and serialdataisclockedinon therisingedge ofclock(MSB first).When LEuWire goes high,dataistransferredtotheregisterbank selectedby theaddressfield.Only registersR0 to R7, R11, R14, and R15 need tobe programmed forproperdeviceoperation. ItisrequiredtoprogramregisterR14. RECOMMENDED PROGRAMMING SEQUENCE The recommended programming sequence involvesprogramming R0 withthe resetbitset (RESET = 1) to ensurethedeviceisina defaultstate.Itisnotnecessarytoprogram R0 again,butifR0 isprogrammed again, the resetbitisprogrammed clear(RESET = 0).Registersare programmed inorderwithR15 beingthe last registerprogrammed.An example programmingsequence isshown below.

  • Program R0 withtheresetbitset(RESET = 1).Thisensuresthedeviceisina defaultstate.When thereset bitissetinR0, theotherR0 bitsareignored. – IfR0 isprogrammed again,theresetbitisprogrammed clear(RESET = 0).
  • Program R0 toR7 as necessarywithdesiredclockswithappropriateenable,mux, divider,and delaysettings.
  • Program R11 withDIV4 settingifnecessary.
  • Program R14 withglobalclockoutputbit,power down setting,PLL mux setting,and PLL R divider.Itis requiredtoprogramregisterR14. – R14 must be programmed in accordance withthe registermap as shown in the registermap (see Table1).
  • Program R15 withPLL chargepump gain,and PLL N divider.

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www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 Table1.LMK02000 REGISTER MAP Re gist 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 er Data [27:0] A3 A2 A1 A0 CLRE CLKout0 Kou CLKout0_DIV CLKout0_DLYR0 SE 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 0 0 0t0_ [7:0] [3:0]T [1:0] EN CLCLKout1 Kou CLKout1_DIV CLKout1_DLYR1 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 0 0 1t1_ [7:0] [3:0][1:0] EN CLCLKout2 Kou CLKout2_DIV CLKout2_DLYR2 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 0 1 0t2_ [7:0] [3:0][1:0] EN CLCLKout3 Kou CLKout3_DIV CLKout3_DLYR3 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 0 1 1t3_ [7:0] [3:0][1:0] EN CLCLKout4 Kou CLKout4_DIV CLKout4_DLYR4 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 1 0 0t4_ [7:0] [3:0][1:0] EN CLCLKout5 Kou CLKout5_DIV CLKout5_DLYR5 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 1 0 1t5_ [7:0] [3:0][1:0] EN CLCLKout6 Kou CLKout6_DIV CLKout6_DLYR6 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 1 1 0t6_ [7:0] [3:0][1:0] EN CLCLKout7 Kou CLKout7_DIV CLKout7_DLYR7 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 1 1 1t7_ [7:0] [3:0][1:0] EN DIVR11 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 14 EN PO TRI PLL_CL WE - _CKou PLL_MUX PLL_RR14 0 0 1 0 RD ST P_ 0 0 0 0 1 1 1 0t_Gl [3:0] [11:0]OW AT POoba N E Ll Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMK02000

SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com Table1.LMK02000 REGISTER MAP (continued) Re gist 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 er PLL_ CP_ PLL_NR15 0 0 0 0 0 0 0 0 1 1 1 1GAIN [17:0] [1:0]

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www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 REGISTER R0 toR7 RegistersR0 throughR7 controlthe eightclockoutputs.RegisterR0 controlsCLKout0, RegisterR1 controls CLKout1,and so on.There isone additionalbitinregisterR0 calledRESET. Asidefrom this,thefunctionsof thesebitsare identical.The X inCLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denotethe actualclockoutputwhichmay be from0 to7. RESET Bit--R0 only ThisbitisonlyinregisterR0. The use ofthisbitisoptionaland itshouldbe setto'0'ifnotused.Settingthisbit toa '1'forcesallregisterstotheirpower on resetconditionand thereforeautomaticallyclearsthisbit.Ifthisbitis set,allotherR0 bitsare ignoredand R0 needs to be programmed againifused withitspropervaluesand RESET = 0. Default BitBitName BitState BitDescription RegisterBitValue Location RESET 0 No reset,normaloperation Resettopower on defaults R0 31 CLKoutX_MUX 0 Bypassed CLKoutX mux mode 18:17 CLKoutX_EN 0 Disabled CLKoutX enable 16 R0 toR7 CLKoutX_DIV 1 Divideby 2 CLKoutX clockdivide 15:8 CLKoutX_DLY 0 0 ps CLKoutX clockdelay 7:4 DIV4 0 PDF ≤ 20 MHz Phase DetectorFrequency R11 15 EN_CLKout_Global 1 Normal -CLKouts normal Globalclockoutputenable 27 POWERDOWN 0 Normal -Deviceactive Devicepower down 26 PLL_CP_TRI 0 Normal -PLL active TRI-STATE PLL chargepump 25 R14 PLL_CP_POL 0 NegativePolarityCP Polarityofchargepump 24 PLL_MUX 0 Disabled MultiplexercontrolforLD pin 23:20 PLL_R 10 R divider= 10 PLL R dividevalue 19:8 PLL_CP_GAIN 0 100 uA Charge pump current 31:30 R15 PLL_N 760 N divider= 760 PLL N dividevalue 25:8 CLKoutX_MUX[1:0] --Clock Output Multiplexers These bitscontrolthe Clock OutputMultiplexerforeach clockoutput.Changing between the differentmodes changes the blocksinthe signalpath and thereforeincursa delayrelativeto the bypass mode. The different MUX modes and associateddelaysarelistedbelow. CLKoutX_MUX[1:0] Mode Added Delay RelativetoBypass Mode

0 Bypassed (default) 0 ps

1 Divided 100 ps

400 ps2 Delayed (Inadditiontotheprogrammed delay) 500 ps3 Dividedand Delayed (Inadditiontotheprogrammed delay) CLKoutX_DIV[7:0]--Clock Output Dividers These bitscontrolthe clockoutputdividervalue.In orderforthese dividersto be active,the respective CLKoutX_MUX (See CLKoutX_MUX[1:0] --Clock Output Multiplexers) bitmust be set to either"Divided"or "Dividedand Delayed"mode. Afterallthedividersareprogramed,theSYNC* pinmust be used toensurethatall edges oftheclockoutputsare aligned(See GLOBAL CLOCK OUTPUT SYNCHRONIZATION ).By addingthe dividerblocktotheoutputpatha fixeddelayofapproximately100 ps isincurred. The actualClockOutputDividevalueistwicethebinaryvalueprogrammed as listedinthetablebelow. Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMK02000

SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com CLKoutX_DIV[7:0] Clock Output Dividervalue 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 1 2 (default) 0 0 0 0 0 0 1 0 4 0 0 0 0 0 0 1 1 6 0 0 0 0 0 1 0 0 8 0 0 0 0 0 1 0 1 10 1 1 1 1 1 1 1 1 510 CLKoutX_DLY[3:0] --Clock Output Delays These bitscontrolthedelaystagesforeach clockoutput.Inorderforthesedelaystobe active,therespective CLKoutX_MUX (See CLKoutX_MUX[1:0] --Clock OutputMultiplexers) bitmust be setto either"Delayed"or "Dividedand Delayed"mode. By addingthedelayblocktotheoutputpatha fixeddelayofapproximately400 ps isincurredinadditiontothedelayshown inthetablebelow. CLKoutX_DLY[3:0] Delay (ps) 0 0 (default) 1 150 2 300 3 450 4 600 5 750 6 900 7 1050 8 1200 9 1350 10 1500 11 1650 12 1800 13 1950 14 2100 15 2250 CLKoutX_EN bit--Clock Output Enables These bitscontrolwhether an individualclockoutputis enabled or not.Ifthe EN_CLKout_Global bit(See EN_CLKout_Global Bit--GlobalClockOutputEnable)issettozeroorifGOE pinisheldlow,allCLKoutX_EN bitstateswillbe ignoredand allclockoutputswillbe disabled.See CLKout OUTPUT STATES formore informationon CLKout states. CLKoutX_EN bit Conditions CLKoutX State

0 EN_CLKout_Globalbit= 1 Disabled(default)

GOE pin= High/No Connect11 Enabled REGISTER R11 Thisregisteronlyhas one bitand onlyneeds tobe programmed inthecase thatthephase detectorfrequencyis greaterthan20 MHz and digitallockdetectisused.Otherwise,itisautomaticallydefaultedtothecorrectvalues. DIV4 Thisbitdividesthefrequencypresentedtothedigitallockdetectcircuitryby 4.Itisnecessarytogeta reliable outputfromthedigitallockdetectoutputinthecase ofa phase detectorfrequencygreaterthan20 MHz.

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www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 DIV4 DigitalLock DetectCircuitryMode

0 Not divided;Phase detectorfrequency≤ 20 MHz (default)

1 Dividedby 4;Phase detectorfrequency> 20 MHz

The LMK02000 requiresregisterR14 tobe programmed as shown intheregistermap (seeTable1). PLL_R[11:0]--R DividerValue These bitsprogramthePLL R Dividerand areprogrammed inbinaryfashion. PLL_R[11:0] PLL R DivideValue 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 1 0 10 (default) 1 1 1 1 1 1 1 1 1 1 1 1 4095 PLL_MUX[3:0] --MultiplexerControlforLD Pin These bitssettheoutputmode oftheLD pin.The tablebelowlistsseveraldifferentmodes. PLL_MUX[3:0] Output Type LD Pin Function

0 Hi-Z Disabled(default)

1 Push-Pull LogicHigh

2 Push-Pull LogicLow

3 Push-Pull DigitalLock Detect(ActiveHigh)

4 Push-Pull DigitalLock Detect(ActiveLow)

5 Push-Pull AnalogLock Detect

6 Open DrainNMOS AnalogLock Detect

7 Open DrainPMOS AnalogLock Detect

8 Invalid

9 Push-Pull N DividerOutput/2(50% DutyCycle)

10 Invalid

11 Push-Pull R DividerOutput/2(50% DutyCycle)

POWERDOWN Bit--Device Power Down Thisbitcan power down thedevice.Enablingthisbitpowers down theentiredeviceand allblocks,regardlessof thestateofany oftheotherbitsorpins. POWERDOWN bit Mode

0 Normal Operation(default)

1 EntireDevicePowered Down

EN_CLKout_Global Bit--GlobalClock Output Enable ThisbitoverridestheindividualCLKoutX_EN bits(See CLKoutX_EN bit--ClockOutputEnables).When thisbit issetto0,allclockoutputsare disabled,regardlessofthestateofany oftheotherbitsor pins.See CLKout OUTPUT STATES formore informationon CLKout states. Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMK02000

SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com EN_CLKout_Global bit Clock Outputs

0 AllOff

1 Normal Operation(default)

PLL_CP_TRI Bit--PLL Charge Pump TRI-STATE ThisbitsetsthePLL chargepump TRI-STATE. PLL_CP_TRI PLL Charge Pump

1 TRI-STATE

PLL_CP_POLBbit --PLL Charge Pump Polarity Thisbitsetsthepolarityofthechargepump toeithernegativeorpositive.A negativechargepump isused witha VCO orVCXO whichdecreasesfrequencywithincreasingtuningvoltage.A positivechargepump isused witha VCO orVCXO whichincreasesfrequencywithincreasingtuningvoltage. PLL_CP_POL PLL Charge Pump Polarity

0 Negative(default)

1 Positive

PLL_N[17:0]--PLL N Divider These bitsprogram thedividevalueforthePLL N Divider.The PLL N DividerprecedesthePLL phase detector. The VCO or VCXO frequencyiscalculatedas,fVCO = fOSCin × PLL N Divider/PLL R Divider.SincethePLL N dividerisa purebinarycounter,thereareno illegaldividevaluesforPLL_N[17:0]exceptfor0. PLL_N[17:0] PLL N DividerValue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 760 (default) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 262143 PLL_CP_GAIN[1:0] --PLL Charge Pump Gain These bitssetthechargepump gainofthePLL. PLL_CP_GAIN[1:0] Charge Pump Gain 0 1x (default) 1 4x 2 16x 3 32x

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(optional) To Host CLKout0 CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* CLKout4 CLKout4* CLKout5 CLKout5* CLKout6 CLKout6* CLKout7 CLKout7* To SystemSYNC* OSCin OSCin* Bias Vcc LDObyp1 LDObyp2 10 PF 0.1 PF 1 PF0.1 PF 0.1 PF LMK02000 Fin Fin* 0.1 PF0.1 PF 100: 100: LMK02000 www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007

APPLICATION INFORMATION

The followingshows the LMK02000 in a typicalapplication.In thissetup the clock may be multiplied, reconditioned,and redistributed. Figure2. TypicalApplication BIAS PIN To properlyuse thedevice,bypass Bias(pin36) witha low leakage1 µF capacitorconnectedtoVcc.Thisis importantforlownoiseperformance. LDO BYPASS To properlyuse thedevice,bypass LDObyp1 (pin9)witha 10 µF capacitorand LDObyp2 (pin10)witha 0.1µF capacitor. CURRENT CONSUMPTION /POWER DISSIPATION CALCULATIONS Due tothemyriadofpossibleconfigurationsthefollowingtableservestoprovideenough informationtoallowthe usertocalculateestimatedcurrentconsumptionoftheLMK02000. UnlessotherwisenotedVcc = 3.3V, TA = 25 °C. Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LMK02000

SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 www.ti.com Table2.Block CurrentConsumption Current Power DissipatedinPower DissipatedBlock Condition Consumption at LVPECL emitterindevice(mW)3.3V (mA) resistors(mW) Entiredevice, Alloutputsoff;No LVPECL emitterresistors 70 231 -corecurrent connected Low clockbuffer The lowclockbufferisenabledanytimeone of 9 29.7 -(internal) CLKout0 throughCLKout3 areenabled Highclockbuffer The highclockbufferisenabledanytimeone ofthe 9 29.7 -(internal) CLKout4 throughCLKout7 areenabled LVDS output,bypassmode 17.8 58.7 - LVPECL output,bypassmode (includes120 Ω 40 72 60emitterresistors) Outputbuffers LVPECL output,disabledmode (includes120 Ω 17.4 38.3 19.1emitterresistors) LVPECL output,disabledmode. No emitter 0 0 -resistorsplaced;open outputs Divideenabled,divide= 2 5.3 17.5 -Dividecircuitry peroutput Divideenabled,divide> 2 8.5 28.0 - Delayenabled,delay< 8 5.8 19.1 -Delaycircuitryper output Delayenabled,delay> 7 9.9 32.7 - Entiredevice CLKout0 & CLKout4 enabledinbypassmode 145.8 421.1 60 From Table2 thecurrentconsumptioncan be calculatedinany configuration.For example,thecurrentforthe entiredevicewith1 LVDS (CLKout0)& 1 LVPECL (CLKout4)outputin bypass mode can be calculatedby addingup thefollowingblocks:corecurrent,low clockbuffer,highclockbuffer,one LVDS outputbuffercurrent, and one LVPECL outputbuffercurrent.There willalsobe one LVPECL outputdrawingemittercurrent,butsome ofthepower fromthecurrentdraw isdissipatedintheexternal120 Ω resistorswhichdoesn'tadd tothepower dissipationbudgetforthedevice.Ifdelaysordividesareswitchedin,thentheadditionalcurrentforthesestages needs tobe added as well. For power dissipatedby thedevice,thetotalcurrententeringthedeviceismultipliedby thevoltageatthedevice minus the power dissipatedin any emitterresistorsconnectedto any of the LVPECL outputs.Ifno emitter resistorsareconnectedtotheLVPECL outputs,thispower willbe 0 watts.For example,inthecase of1 LVDS (CLKout0)& 1 LVPECL (CLKout4)operatingat3.3volts,we calculate3.3V × (70+ 9 + 9 + 17.8+ 40)mA = 3.3 V × 145.8mA = 481.1mW. Because theLVPECL output(CLKout4)has theemitterresistorshooked up and the power dissipatedby theseresistorsis60 mW, thetotaldevicepower dissipationis481.1mW -60 mW = 421.1 mW. When theLVPECL outputisactive,~1.9V istheaveragevoltageon each outputas calculatedfromtheLVPECL Voh & Voltypicalspecification.Thereforethepower dissipatedineach emitterresistorisapproximately(1.9V)2 / 120 Ω = 30 mW. When the LVPECL outputisdisabled,the emitterresistorvoltageis~1.07 V. Thereforethe power dissipatedineach emitterresistorisapproximately(1.07V)2 /120 Ω = 9.5mW. THERMAL MANAGEMENT Power consumptionof the LMK02000 can be high enough to requireattentionto thermalmanagement. For reliabilityand performancereasonsthedietemperatureshouldbe limitedtoa maximum of125 °C. Thatis,as an estimate,TA (ambienttemperature)plusdevicepower consumptiontimesθJA shouldnotexceed 125 °C. The package ofthedevicehas an exposed pad thatprovidestheprimaryheatremovalpathas wellas excellent electricalgroundingtotheprintedcircuitboard.To maximize theremovalofheatfrom thepackage a thermal landpatternincludingmultipleviastoa groundplanemust be incorporatedon thePCB withinthefootprintofthe package.The exposed pad must be soldereddown toensureadequateheatconductionoutofthepackage.A recommended landand viapatternisshown inFigure3.More informationon solderingWQFN packages can be obtainedatwww.ti.com.

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0.33 mm, typ 1.2 mm, typ 5.0 mm, min LMK02000 www.ti.com SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007 Figure3. To minimizejunctiontemperatureitisrecommended thata simpleheatsinkbe builtintothePCB (iftheground planelayerisnotexposed).Thisisdone by includinga copperarea ofabout2 squareincheson theopposite sideof the PCB from the device.Thiscopper area may be platedor soldercoatedto preventcorrosionbut shouldnot have conformalcoating(ifpossible),which couldprovidethermalinsulation.The viasshown in Figure3 shouldconnectthesetopand bottomcopperlayersand totheground layer.These viasactas “heat pipes” tocarrythethermalenergyaway from thedevicesideoftheboard towhere itcan be more effectively dissipated. Copyright© 2006–2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LMK02000

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LMK02000ISQ/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K02000 I LMK02000ISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K02000 I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK02000ISQ/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK02000ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 2

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