LMK01010ISQE/NOPB

LMK01000_14 TI1 | Alldatasheet

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www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 LMK01000FamilyLMK01000Family1.6GHzHighPerformanceClockBuffer,Divider,and Distributor Check forSamples: LMK01000 1FEATURES • 3.15to3.45V operation

• Package: 48 pinLLP (7.0x 7.0x 0.8mm) 2• 30 fsadditivejitter(100Hz to20 MHz)
• Dual clockinputs LVDS LVPECLDevice• Programmable outputchannels (0to1600 Outputs Outputs MHz) LMK01000 3 5
• Externalsynchronization LMK01010 8 0 LMK01020 0 8• Pin compatiblefamilyofclockingdevices TARGET APPLICATIONS
• High performance Clock Distribution
• WirelessInfrastructure
• MedicalImaging
• Wired Communications
• Testand Measurement
• Military/Aerospace

DESCRIPTION

The LMK01000 familyprovidesan easy way todivideand distributehighperformanceclocksignalsthroughout the system.These devicesprovidebest-in-classnoise performanceand are designed to be pin-to-pinand footprintcompatiblewithLMK03000/LMK02000 familyofprecisionclockconditioners. The LMK01000 familyfeaturestwo programmable clockinputs(CLKin0 and CLKin1) thatallowthe user to dynamicallyswitchbetween differentclockdomains. Each devicefeatures8 clockoutputswithindependentlyprogrammable dividersand delayadjustments.The outputsofthedevicecan be easilysynchronizedby an externalpin(SYNC*). Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2008–2009,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

CLKin0* CLKout0 CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* CLKout4 CLKout4* CLKout5 CLKout5* CLKout6 CLKout6* CLKout7 CLKout7* Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Distribution Path CLK DATA LE Control Registers PWire Port Device Control GOE SYNC*CLKin1 CLKin1* Low Clock Buffers High Clock Buffers Mux LMK010x0 Clock Divider and Distributor CLKout7 CLKout4 CLKout1 CLKout0 Serializer/ Deserializer LMX2531 PLL+VCO ADC FPGA CLKin0 CLKin1 LMK010x0 Clock Divider and Distributor CLKout7 CLKout0 LMX2531 PLL+VCO ADC CLKin1 ADC LMK01000 SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com System Diagram FunctionalBlock Diagram

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CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* GND SYNC* CLKin0 CLKin0* NC CLKin1 CLKin1* Bias CLKout4 CLKout4* CLKout5 CLKout5* CLKout6 CLKout6* CLKout7 CLKout7* 4748 46 45 44 43 42 41 40 39 38 37 1413 15 16 17 18 19 20 21 22 23 24 DAP LLP-48 Top Down View LMK01000 www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 Connection Diagram Figure1. 48-PinLLP Package Pin Functions Pin Descriptions Pin # Pin Name I/O Description 1,25 GND - Ground 2,7,9,10,32 NC - No Connect.Pinisnotconnectedtothedie. 3,8,13,16,19,22,26, Vcc1,Vcc2,Vcc3,Vcc4,Vcc5,Vcc6,Vcc7,Vcc8, - Power Supply30,31,33,37,40,43,46 Vcc9,Vcc10,Vcc11,Vcc12,Vcc13,Vcc14

4 CLKuWire I MICROWIRE ClockInput

5 DATAuWire I MICROWIRE Data Input

6 LEuWire I MICROWIRE LatchEnableInput

11 GOE I GlobalOutputEnable

Thisisan outputpinused strictlyfortestpurposes and shouldbe notconnectedfornormaloperation.12 Test O However,any loadofan impedance ofmore than1 kΩ isacceptable. 14,15 CLKout0,CLKout0* O ClockOutput0 17,18 CLKout1,CLKout1* O ClockOutput1 20,21 CLKout2,CLKout2* O ClockOutput2 23,24 CLKout3,CLKout3* O ClockOutput3

27 SYNC* I GlobalClockOutputSynchronization

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SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com Pin Descriptions(continued) Pin # Pin Name I/O Description 28,29 CLKin0,CLKin0* I CLKin 0 Input;Must be AC coupled 34,35 CLKin1,CLKin1* I CLKin 1 Input;Must be AC coupled

36 Bias I BiasBypass

38,39 CLKout4,CLKout4* O ClockOutput4 41,42 CLKout5,CLKout5* O ClockOutput5 44,45 CLKout6,CLKout6* O ClockOutput6 47,48 CLKout7,CLKout7* O ClockOutput7 DAP DAP - DieAttachPad shouldbe connectedtoground. The LMK01000 familyisfootprintcompatiblewiththeLMK03000/02000 familyofdevices.AllCLKout pinsare pin-to-pincompatible,and CLKin0 and CLKin1 areequivalenttoOSCin and Fin,respectively. Device ConfigurationInformation Output LMK01000 LMK01010 LMK01020 CLKout0 LVDS LVDS LVPECL CLKout1 LVDS LVDS LVPECL CLKout2 LVDS LVDS LVPECL CLKout3 LVPECL LVDS LVPECL CLKout4 LVPECL LVDS LVPECL CLKout5 LVPECL LVDS LVPECL CLKout6 LVPECL LVDS LVPECL CLKout7 LVPECL LVDS LVPECL These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) Parameter Symbol Ratings Units Power SupplyVoltage VCC -0.3to3.6 V InputVoltage VIN -0.3to(VCC + 0.3) V StorageTemperatureRange TSTG -65to150 °C Lead Temperature(solder4 s) TL +260 °C JunctionTemperature TJ 125 °C (1) "AbsoluteMaximum Ratings"indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) Thisdeviceisa highperformanceintegratedcircuitwithESD handlingprecautions.Handlingofthisdeviceshouldonlybe done atESD protectedwork stations.The deviceisratedtoa HBM-ESD of> 2 kV,a MM-ESD of> 200 V,and a CDM-ESD of> 1.2kV. Recommended OperatingConditions Parameter Symbol Min Typ Max Units AmbientTemperature TA -40 25 85 °C Power SupplyVoltage VCC 3.15 3.3 3.45 V

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www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 Package Thermal Resistance Package θJA θJ-PAD (ThermalPad) 48-LeadLLP (1) 27.4° C/W 5.8° C/W (1) Specificationassumes 16 thermalviasconnectthedieattachpad totheembedded copperplaneon the4-layerJEDEC board.These viasplaya key roleinimprovingthethermalperformanceoftheLLP.Itisrecommended thatthemaximum number ofviasbe used in theboardlayout. Copyright© 2008–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMK01000

SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com ElectricalCharacteristics(1) (3.15V ≤ Vcc ≤ 3.45V,-40°C ≤ TA ≤ 85 °C, DifferentialInputs/Outputs;exceptas specified.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproduct characterizationand arenotguaranteed). Symbol Parameter Conditions Min Typ Max Units CurrentConsumption Alloutputs LMK01000 271 enabled,no LMK01010 160divideordelay (CLKoutX_MUX LMK01020 338= Bypassed )Power SupplyCurrentICC (2) LVDS 17.8 mAPer channel,no LVPECLdivideordelay (Includes(CLKoutX_MUX 40Emitter= Bypassed ) Resistors) ICC PD Power Down Current POWERDOWN = 1 1 CLKin0, CLKin0*,CLKin1, CLKin1* fCLKin CLKin FrequencyRange 1 1600 MHz (3)(4) SLEW CLKin CLKin FrequencyInputSlew Rate V/ns0.5 fCLKin ≤ 800 MHz 30 70 DUTY CLKin CLKin FrequencyInputDutyCycle % fCLKin > 800 MHz 40 60 PCLKin InputPower Range forCLKin orCLKin* AC coupled -13 5 dBm Clock DistributionSection--Delays fCLKoutX ≤ 1 GHz (Delayislimitedtomaximum 2250 programmablevalue) DelayCLKout Maximum AllowableDelay(4) ps fCLKoutX > 1 GHz 0.5/f (Delayislimitedto1/2ofa CLKou period) tX Clock DistributionSection-Divides fCLKinX ≤ 1300 MHz 1 510 Allowabledividerange.(Notethat1 istheonlyDivideCLKoutX n/a1300 MHz < fCLKinX ≤ 1600allowableodd dividevalue) 1 2MHz Clock DistributionSection-LVDS Clock Outputs fCLKoutX = 80R L = 100 Ω 200 MHz Bandwidth= fCLKoutX =JitterADD AdditiveRMS Jitter(5) 100 Hz to20 30 fs800 MHzMHz fCLKoutX =Vboost= 1 251600 MHz fCLKoutX = -156200 MHz R L = 100 Ω fCLKoutX =NoiseFloor DividerNoiseFloor(5) -153 dBc/HzVboost= 1 800 MHz fCLKoutX = -1481600 MHz (1) The ElectricalCharacteristicstableslistguaranteedspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotguaranteed. (2) See section3.2formore currentconsumption/power dissipationcalculationinformation. (3) Forallfrequenciestheslewrate,SLEW CLKin1,ismeasured between 20% and 80%. (4) Specificationisguaranteedby characterizationand isnottestedinproduction. (5) The noisefloorofthedividerismeasured as thefaroutphase noiseofthedivider.Typicallythisoffsetis40 MHz, butforlower frequenciesthismeasurement offsetcan be as lowas 5 MHz due tomeasurement equipmentlimitations.Ifthedelayisused,thenuse section1.3.

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www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 ElectricalCharacteristics(1)(continued) (3.15V ≤ Vcc ≤ 3.45V,-40°C ≤ TA ≤ 85 °C, DifferentialInputs/Outputs;exceptas specified.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproduct characterizationand arenotguaranteed). Symbol Parameter Conditions Min Typ Max Units Equalloadingand identical tSKEW CLKoutX toCLKoutY (4) clockconfiguration -30 ±4 30 ps R L = 100 Ω Vboost=0 250 350 450 VOD DifferentialOutputVoltage (6) mV Vboost=1 390 Change inmagnitudeofVOD forcomplementaryΔVOD R L = 100 Ω -50 50 mVoutputstates 1.07 1.37VOS OutputOffsetVoltage R L = 100 Ω 1.25 V0 0 Change inmagnitudeofVOS forcomplementaryΔVOS R L = 100 Ω -35 35 mVoutputstates ISA ClockOutputShortCircuitCurrent Singleended outputsshorted -24 24 mAISB singleended toGND ClockOutputShortCircuitCurrent ComplementaryoutputstiedISAB -12 12 mAdifferential together Clock DistributionSection-LVPECL Clock Outputs fCLKoutX = 65R L = 100 Ω 200 MHz Bandwidth= fCLKoutX =JitterADD AdditiveRMS Jitter(5) 100 Hz to20 25 fs800 MHzMHz fCLKoutX =Vboost= 1 251600 MHz fCLKoutX = -158200 MHz R L = 100 Ω fCLKoutX =NoiseFloor DividerNoiseFloor(7) -154 dBc/HzVboost= 1 800 MHz fCLKoutX = -1481600 MHz Equalloadingand identical clockconfigurationtSKEW CLKoutX toCLKoutY (8) -30 ±3 30 psTermination= 50 Ω toVcc -2 V Vcc -VOH OutputHighVoltage V0.98Termination= 50 Ω toVcc -2 V Vcc -VOL OutputLow Voltage V1.8 Vboost= 0 660 810 965 VOD DifferentialOutputVoltage (9) mV Vboost= 1 865 DigitalLVTTL Interfaces(10) VIH High-LevelInputVoltage 2.0 Vcc V VIL Low-LevelInputVoltage 0.8 V IIH High-LevelInputCurrent VIH = Vcc -5.0 5.0 µA IIL Low-LevelInputCurrent VIL= 0 -40.0 5.0 µA Vcc -VOH High-LevelOutputVoltage IOH = +500 µA V0.4 VOL Low-LevelOutputVoltage IOL = -500µA 0.4 V (6) See characterizationplotstosee how thisparametervariesoverfrequency. (7) The noisefloorofthedividerismeasured as thefaroutphase noiseofthedivider.Typicallythisoffsetis40 MHz, butforlower frequenciesthismeasurement offsetcan be as lowas 5 MHz due tomeasurement equipmentlimitations.Ifthedelayisused,thenuse section1.3. (8) Specificationisguaranteedby characterizationand isnottestedinproduction. (9) See characterizationplotstosee how thisparametervariesoverfrequency. (10)AppliestoGOE, LD, and SYNC*. Copyright© 2008–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMK01000

SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com ElectricalCharacteristics(1)(continued) (3.15V ≤ Vcc ≤ 3.45V,-40°C ≤ TA ≤ 85 °C, DifferentialInputs/Outputs;exceptas specified.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproduct characterizationand arenotguaranteed). Symbol Parameter Conditions Min Typ Max Units DigitalMICROWIRE Interfaces(11) VIH High-LevelInputVoltage 1.6 Vcc V VIL Low-LevelInputVoltage 0.4 V IIH High-LevelInputCurrent VIH = Vcc -5.0 5.0 µA IIL Low-LevelInputCurrent VIL= 0 -5.0 5.0 µA MICROWIRE Timing tCS Data toClockSetUp Time See Data InputTiming 25 ns tCH Data toClockHoldTime See Data InputTiming 8 ns tCWH ClockPulseWidthHigh See Data InputTiming 25 ns tCWL ClockPulseWidthLow See Data InputTiming 25 ns tES ClocktoEnableSetUp Time See Data InputTiming 25 ns tCES EnabletoClockSetUp Time See Data InputTiming 25 ns tEWH EnablePulseWidthHigh See Data InputTiming 25 ns (11)AppliestoCLKuWire,DATAuWire, and LEuWire. SerialData Timing Diagram Data bitsseton theDATAuWire signalare clockedintoa shiftregister,MSB first,on each risingedge ofthe CLKuWire signal.On the risingedge of the LEuWire signal,the data issent from the shiftregisterto the addressedregisterdeterminedby theLSB bits.Aftertheprogramming iscompletetheCLKuWire, DATAuWire, and LEuWire signalsshouldbe returnedtoa low state.The slew rateofCLKuWire, DatauWire,and LEuWire shouldbe atleast30 V/µs.

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SYNC* CLKout0 CLKout1 CLKout2 LMK01000 www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 FunctionalDescription The LMK01000 familyincludesa programmabledivider,a phase synchronizationcircuit,a programmabledelay, a clockoutputmux, and an LVDS orLVPECL outputbufferineach channel.Thisallowsmultipleinteger-related and phase-adjustedcopiesofthereferencetobe distributedtoup toeightsystemcomponents. This familyof devicescomes in a 48-pinLLP package thatispin-to-pinand footprintcompatiblewithother LMK02000/LMK03000 familyofclockingdevices. BIAS PIN To properlyuse thedevice,bypass Bias(pin36) witha low leakage1 µF capacitorconnectedtoVcc.Thisis importantforlownoiseperformance. CLKin0/CLKin0* and CLKin1/CLKin1 INPUT PORTS The devicecan be driveneitherby theCLKin0/CLKin0*ortheCLKin1/CLKin1*pins.The choiceofwhichone to use issoftwareselectable.These inputportsmust be AC coupled.To drivethese inputsin a singleended fashion,AC groundthecomplementaryinput. When choosingAC couplingcapacitorsforclocksignals0.1µF isa good startingpoint,butlowerfrequencies may requirehighervaluecapacitorswhilehigherfrequenciesmay use lowervaluecapacitors. CLKout DELAYS Each individualclockoutputincludesa delayadjustment.Clockoutputdelayregisters(CLKoutX_DLY) supporta 150 ps stepsizeand range from 0 to2250 ps oftotaldelay.When thedelayisenableditadds totheoutput noisefloor;thetotaladditivenoiseis10(log(10^(OutputNoiseFloor/10)+ 10^(DelayNoiseFloor/10)).Referto theTypicalPerformanceCharacteristicsplotsfortheDelayNoiseFloorinformation. LVDS/LVPECL OUTPUTS Each LVDS or LVPECL outputmay be disabledindividuallyby programming the CLKoutX_EN bits.Allthe outputsmay be disabledsimultaneouslyby pullingtheGOE pinloworprogrammingEN_CLKout_Globalto0. GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pinsynchronizesthe clockoutputs.When the SYNC* pinisheldina logiclow state,the divided outputsarealsoheldina logiclow state.When theSYNC* pingoes high,thedividedclockoutputsareactivated and willtransitiontoa highstatesimultaneously.ClocksintheBypassed stateare notaffectedby SYNC* and arealwayssynchronizedwiththedividedoutputs. The SYNC* pinmust be heldlow forgreaterthanone clockcycleoftheFrequencyInputport,alsoknown as the distributionpath.Once thislow eventhas been registered,theoutputswillnotreflectthelow stateforfourmore cycles.When the SYNC* pinbecomes high,the outputswillnot simultaneouslytransitionhighuntilfourmore distributionpath clockcycleshave passed. See the SYNC* timingdiagram forfurtherdetail.In the timing diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2,CLKout2_MUX = Divided,and CLKout2_DIV = 4. SYNC* Timing Diagram Copyright© 2008–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMK01000

SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com The SYNC* pinprovidesan internalpull-upresistoras shown on thefunctionalblockdiagram.IftheSYNC* pin isnot terminatedexternallythe clockoutputswilloperatenormally.Ifthe SYNC* functionisnot used,clock outputsynchronizationisnotguaranteed. CONNECTION TO LVDS OUTPUTS LMK01000 and LMK01010 LVDS outputscan be connectedinAC orDC couplingconfigurations;however,inDC couplingconfiguration,properconditionsmust be presentedby theLVDS receiver.To ensuresuch conditions, we recommend the usage of LVDS receiverswithoutfail-safeor internalinputbias such as National Semiconductor'sDS90LV110T. The LMK01000 familyLVDS driversprovidetheadequateDC biasfortheLVDS receiver.We recommend AC couplingwhen usingLVDS receiverswithfail-safeorinternalinputbias. CLKout OUTPUT STATES Each clockoutputmay be individuallyenabledwiththeCLKoutX_EN bits.Each individualoutputenablecontrol bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). Allclockoutputscan be disabledsimultaneouslyifthe GOE pin is pulledlow by an externalsignalor EN_CLKout_Globalissetto0. CLKoutX EN_CLKout GOE pin Clock X Output State _EN bit _Globalbit 1 1 Low Low Don'tcare 0 Don'tcare Off

0 Don'tcare Don'tcare Off

1 1 High/No Connect Enabled When an LVDS outputisinthe Offstate,the outputsare at a voltageof approximately1.5 volts.When an LVPECL outputisintheOffstate,theoutputsareata voltageofapproximately1 volt. GLOBAL OUTPUT ENABLE The GOE pinprovidesan internalpull-upresistor.Ifitisnotterminatedexternally,theclockoutputstatesare determinedby theClockOutputEnablebits(CLKoutX_EN) and theEN_CLKout_Globalbit. POWER-ON-RESET When supplyvoltagetothedeviceincreasesmonotonicallyfrom ground toVcc,thepower-on-resetcircuitsets allregisterstotheirdefaultvalues,whicharespecifiedintheGeneralProgramming Informationsection.Voltage shouldbe appliedtoallVcc pinssimultaneously. GeneralProgramming Information The LMK01000 familydeviceisprogrammed usingseveral32-bitregisters.The registersconsistofa datafield and an addressfield.The last4 registerbits,ADDR[3:0]formtheaddressfield.The remaining28 bitsformthe datafieldDATA[27:0]. Duringprogramming,LEuWire islow and serialdataisclockedinon therisingedge ofclock(MSB first).When LEuWire goes high,dataistransferredtotheregisterbank selectedby theaddressfield.OnlyregistersR0 toR7 and R14 need tobe programmed forproperdeviceoperation. ItisrequiredtoprogramregisterR14. RECOMMENDED PROGRAMMING SEQUENCE The recommended programming sequence involvesprogramming R0 withthe resetbitset (RESET = 1) to ensurethedeviceisina defaultstate.Itisnotnecessarytoprogram R0 again,butifR0 isprogrammed again, theresetbitisprogrammed clear(RESET = 0).An example programmingsequence isshown below.

• Program R0 withtheresetbitset(RESET = 1).Thisensuresthedeviceisina defaultstate.When thereset bitissetinR0, theotherR0 bitsareignored. – IfR0 isprogrammed again,theresetbitisprogrammed clear(RESET = 0).

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• Program R0 toR7 as necessarywithdesiredclockswithappropriateenable,mux, divider,and delaysettings.
• Program R14 withglobalclockoutputbit,power down setting. – R14 must be programmed inaccordancewiththeregistermap as shown intheregistermap (See Section 2.2). Table1.RegisterMap Re gis 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ter Data [27:0] A3 A2 A1 A0 CL RE CLKout0 Ko CLKout0_DIV CLKout0_DLYR0 SE 0 0 0 0 0 0 0 0 0 0 0 0 _MUX ut0 0 0 0 0[7:0] [3:0]T [1:0] _E N CL CLKout1 Ko CLKout1_DIV CLKout1_DLYR1 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX ut1 0 0 0 1[7:0] [3:0][1:0] _E N CL CLKout2 Ko CLKout2_DIV CLKout2_DLYR2 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX ut2 0 0 1 0[7:0] [3:0][1:0] _E N CL CLKout3 Ko CLKout3_DIV CLKout3_DLYR3 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX ut3 0 0 1 1[7:0] [3:0][1:0] _E N CL CLKout4 Ko CLKout4_DIV CLKout4_DLYR4 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX ut4 0 1 0 0[7:0] [3:0][1:0] _E N CL CLKout5 Ko CLKout5_DIV CLKout5_DLYR5 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX ut5 0 1 0 1[7:0] [3:0][1:0] _E N CL CLKout6 Ko CLKout6_DIV CLKout6_DLYR6 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX ut6 0 1 1 0[7:0] [3:0][1:0] _E N CL CLKout7 Ko CLKout7_DIV CLKout7_DLYR7 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX ut7 0 1 1 1[7:0] [3:0][1:0] _E N Vb R9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 o 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 ost ENCL PO_CKin WLKR1 _S ER0 1 0 out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 04 EL DO_GEC WlobT Nal REGISTER R0 toR7 RegistersR0 throughR7 controlthe eightclockoutputs.RegisterR0 controlsCLKout0, RegisterR1 controls CLKout1,and so on.There isone additionalbitinregisterR0 calledRESET. Asidefrom this,thefunctionsof thesebitsare identical.The X inCLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denotethe actualclockoutputwhichmay be from0 to7. Table2.DefaultRegisterSettingsafterPower-on-Reset Default BitBitName BitState BitDescription RegisterBitValue Location RESET 0 No reset,normaloperation Resettopower on defaults R0 31 Copyright© 2008–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMK01000

SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com Table2.DefaultRegisterSettingsafterPower-on-Reset(continued) Default BitBitName BitState BitDescription RegisterBitValue Location CLKoutX_MUX 0 Bypassed CLKoutX mux mode 18:17 CLKoutX_EN 0 Disabled CLKoutX enable 16 R0 toR7 CLKoutX_DIV 1 Divideby 2 CLKoutX clockdivide 15:8 CLKoutX_DLY 0 0 ps CLKoutX clockdelay 7:4 CLKin_SELECT 0 CLKin1 SelectCLKin0 orCLKin1 29 EN_CLKout_Global 1 Normal -CLKouts normal Globalclockoutputenable R14 27 POWERDOWN 0 Normal -Deviceactive Devicepower down 26 Reset Bit--R0 only ThisbitisonlyinregisterR0. The use ofthisbitisoptionaland itshouldbe setto'0'ifnotused.Settingthisbit toa '1'forcesallregisterstotheirpower-on-resetconditionand thereforeautomaticallyclearsthisbit.Ifthisbitis set,allotherR0 bitsare ignoredand R0 needs to be programmed againifused withitspropervaluesand RESET = 0. CLKoutX_MUX[1:0] --Clock Output Multiplexers These bitscontrolthe Clock OutputMultiplexerforeach clockoutput.Changing between the differentmodes changes theblocksinthesignalpathand thereforeincursa delayrelativetotheBypassed mode. The different MUX modes and associateddelaysarelistedbelow. CLKoutX_MUX[1:0] Mode Added Delay RelativetoBypassed Mode

0 Bypassed (default) 0 ps

1 Divided 100 ps

400 ps2 Delayed (Inadditiontotheprogrammed delay) 500 ps3 Dividedand Delayed (Inadditiontotheprogrammed delay) CLKoutX_DIV[7:0]--Clock Output Dividers These bitscontrolthe clockoutputdividervalue.In orderforthese dividersto be active,the respective CLKoutX_MUX (See Section2.3.2) bitmust be settoeither"Divided"or "Dividedand Delayed"mode. Afterall the dividersare programed,the SYNC* pin must be used to ensure thatalledges of the clockoutputsare aligned(See Section1.5).By addingthedividerblocktotheoutputpatha fixeddelayofapproximately100 ps is incurred. The actualClockOutputDividevalueistwicethebinaryvalueprogrammed as listedinthetablebelow. CLKoutX_DIV[7:0] Clock Output Dividervalue 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 1 2 (default) 0 0 0 0 0 0 1 0 4 0 0 0 0 0 0 1 1 6 0 0 0 0 0 1 0 0 8 0 0 0 0 0 1 0 1 10 1 1 1 1 1 1 1 1 510

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www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 CLKoutX_DLY[3:0] --Clock Output Delays These bitscontrolthedelaystagesforeach clockoutput.Inorderforthesedelaystobe active,therespective CLKoutX_MUX (See Section2.3.2) bitmust be set to either"Delayed"or "Dividedand Delayed"mode. By addingthe delayblockto the outputpath a fixeddelayof approximately400 ps isincurredinadditionto the delayshown inthetablebelow. CLKoutX_DLY[3:0] Delay (ps) 0 0 (default) 1 150 2 300 3 450 4 600 5 750 6 900 7 1050 8 1200 9 1350 10 1500 11 1650 12 1800 13 1950 14 2100 15 2250 CLKoutX_EN bit--Clock Output Enables These bitscontrolwhetheran individualclockoutputisenabledornot.IftheEN_CLKout_Globalbitissettozero orifGOE pinisheldlow,allCLKoutX_EN bitstateswillbe ignoredand allclockoutputswillbe disabled. CLKoutX_EN bit Conditions CLKoutX State

0 EN_CLKout_Globalbit= 1 Disabled(default)

GOE pin= High/No Connect11 Enabled REGISTER R9 R9 onlyneeds tobe programmed ifVboostissetto1.Program allotherbitsinR9 as indicatedinregistermap (See Section2.2) Vboost -VoltageBoost Bit Enablingthisbitsetsallclockoutputsinvoltageboostmode whichincreasesthevoltageattheseoutputs.This can improvethenoisefloorperformanceoftheoutput,butalsoincreasescurrentconsumption,and can cause theoutputstobe toohightomeet theLVPECL/LVDS specifications. Vboost bit fCLKoutX < 1300 MHz 1300 MHz ≤ fCLKoutX < 1500 1500 MHz ≤ fCLKoutX ≤ 1600 MHz MHz

0 Recommended tohitvoltagelevel InsufficientvoltagelevelforLVDS/LVPECL specifications,butsaves

specificationsforLVPECL/LVDS current

1 VoltageMay overdriveLVPECL/LVDS Voltageissufficientfor Insufficientvoltagefor

specifications,butnoisefloorisabout2-4dB LVDS/LEVPECL specifications.LVDS/LVPECL specifications,but betterand currentconsumptionisincreased Currentconsumptionis stillhigherthanwhen Vboost=0. increased,butnoiseflooris Increasedcurrentconsumption. aboutthesame. Copyright© 2008–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMK01000

OSCin* LEuWire Test Test VrefVCO VregBUF VregDIG 3.3 : 4.7 PF 10 nF 0.22 : 470 nF 0.22 : 470 nF 10 nF 10 nF VregPLL1 VregPLL2 CLKin1* 100 pF 3.0 V VregVCO VccVCO VccDIG VccBUF VccPLL Vtune CPout C1_LF C2_LFR2_LF 3.3 V Vcc1 Vcc13 Vcc14 CE Bias SYNC* GOE CLKout0 CLKout0* ... CLKout7 CLKout7* To Other Devices 100 nF LMK01000 SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com REGISTER R14 The LMK01000 familyrequiresregisterR14 tobe programmed as shown intheregistermap (See Section2.2). POWERDOWN Bit--Device Power Down Thisbitcan power down thedevice.Enablingthisbitpowers down theentiredeviceand allblocks,regardlessof thestateofany oftheotherbitsorpins. POWERDOWN bit Mode

0 Normal Operation(default)

1 EntireDevicePowered Down

EN_CLKout_Global Bit--GlobalClock Output Enable This bitoverridesthe individualCLKoutX_EN bits.When thisbitis set to 0, allclockoutputsare disabled, regardlessofthestateofany oftheotherbitsorpins. EN_CLKout_Global bit Clock Outputs

0 AllOff

1 Normal Operation(default)

CLKin_SELECT Bit--Device CLKin Select ThisbitdetermineswhichCLKin pinisused. CLKin bit Mode

0 CLKin1 (default)

1 CLKin0

The followingshows a typicalapplicationfora LMK01000 familydevice.Inthissetuptheclockmay be divided, skewed,and redistributed. Figure2. TypicalApplication

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www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 CURRENT CONSUMPTION /POWER DISSIPATION CALCULATIONS (Vcc = 3.3V,TA = 25° C) Current PowerPowerConsumption DissipatedinBlock Condition Dissipatedinat3.3V LVPECL emitterdevice(mW)(mA) resistors(mW) Core Current Alloutputsdisabled.Includesinputbuffercurrents. 19 62.7 - Low clockbuffer The lowclockbufferisenabledanytimeone ofCLKout0 through 9 29.7 -(internal) CLKout3 areenabled Highclock The highclockbufferisenabledanytimeone oftheCLKout4 9 29.7 -buffer(internal)throughCLKout7 areenabled LVDS output,Bypassed mode 17.8 58.7 - LVPECL output,Bypassed mode 40 72 60(includes120 Ω emitterresistors) Outputbuffers LVPECL output,disabledmode 17.4 38.3 19.1(includes120 Ω emitterresistors) LVPECL output,disabledmode. 0 0 -No emitterresistorsplaced;open outputs Additionalcurrentperchanneldue LVPECL Output 0.5 1.65 - Vboost tosettingVboostfrom0 to1. LVDS Output 1.5 5.0 Divideenabled,divide= 2 5.3 17.5 -Dividecircuitry peroutput Divideenabled,divide> 2 8.5 28.0 - Delayenabled,delay< 8 5.8 19.1 -Delaycircuitry peroutput Delayenabled,delay> 7 9.9 32.7 - Entiredevice LMK01000 85.8 223.1 60 CLKout0 & LMK01010 63.6 209.9 -CLKout4 enabledin LMK01020 108 236.4 120Bypassed mode Entiredevice LMK01000 323.8 768.5 300 alloutputs LMK01010 212.8 702.3 -enabledwithno delayand divide LMK01020 390.4 808.3 480valueof2 From theabove table,thecurrentcan be calculatedinany configuration.For example,thecurrentfortheentire devicewith1 LVDS (CLKout0)& 1 LVPECL (CLKout4)outputinBypassed mode can be calculatedby addingup thefollowingblocks:corecurrent,low clockbuffer,highclockbuffer,one LVDS outputbuffercurrent,and one LVPECL outputbuffercurrent.There willalsobe one LVPECL outputdrawingemittercurrent,butsome ofthe power from the currentdraw isdissipatedin the external120 Ω resistorswhich doesn'tadd to the power dissipationbudgetforthedevice.Ifdelaysordividesareswitchedin,thentheadditionalcurrentforthesestages needs tobe added as well. For power dissipatedby thedevice,thetotalcurrententeringthedeviceismultipliedby thevoltageatthedevice minus the power dissipatedin any emitterresistorsconnectedto any of the LVPECL outputs.Ifno emitter resistorsareconnectedtotheLVPECL outputs,thispower willbe 0 watts.For example,inthecase of1 LVDS (CLKout0)& 1 LVPECL (CLKout4)operatingat3.3voltsforLMK01000, we calculate3.3V × (10+ 9 + 9 + 17.8 + 40) mA = 3.3 V × 85.8 mA = 283.1 mW. Because the LVPECL output(CLKout4)has the emitterresistors hooked up and thepower dissipatedby theseresistorsis60 mW, thetotalpower dissipationis283.1mW -60 mW = 223.1mW. When theLVPECL outputisactive,~1.9V istheaveragevoltageon each outputas calculated from the LVPECL Voh & Vol typicalspecification.Thereforethe power dissipatedin each emitterresistoris approximately(1.9V)2 /120 Ω = 30 mW. When theLVPECL outputisdisabled,theemitterresistorvoltageis THERMAL MANAGEMENT Power consumption of the LMK01000 familydevice can be high enough to requireattentionto thermal management. For reliabilityand performancereasonsthe dietemperatureshouldbe limitedto a maximum of 125 °C. Thatis,as an estimate,TA (ambienttemperature)plusdevicepower consumptiontimesθJA shouldnot exceed 125 °C. Copyright© 2008–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMK01000

0.33 mm, typ 1.2 mm, typ 5.0 mm, min LMK01000 SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com The package ofthedevicehas an exposed pad thatprovidestheprimaryheatremovalpathas wellas excellent electricalgroundingtotheprintedcircuitboard.To maximize theremovalofheatfrom thepackage a thermal landpatternincludingmultipleviastoa groundplanemust be incorporatedon thePCB withinthefootprintofthe package.The exposed pad must be soldereddown toensureadequateheatconductionoutofthepackage.A recommended landand viapatternisshown inFigure3.More informationon solderingLLP packages can be obtainedatwww.national.com. Figure3. Recommended Land and ViaPattern To minimizejunctiontemperatureitisrecommended thata simpleheatsinkbe builtintothePCB (iftheground planelayerisnotexposed).Thisisdone by includinga copperarea ofabout2 squareincheson theopposite sideof the PCB from the device.Thiscopper area may be platedor soldercoatedto preventcorrosionbut shouldnot have conformalcoating(ifpossible),which couldprovidethermalinsulation.The viasshown in Figure3 shouldconnectthesetopand bottomcopperlayersand totheground layer.These viasactas “heat pipes” tocarrythethermalenergyaway from thedevicesideoftheboard towhere itcan be more effectively dissipated. TERMINATION AND USE OF CLOCK OUTPUTS When terminatingclockdriverskeep inmind theseguidelinesforoptimum phase noiseand jitterperformance:

• Transmissionlinetheoryshouldbe followedforgood impedance matchingtopreventreflections.
• Clockdriversshouldbe presentedwiththeproperloads. – LVDS driversarecurrentdriversand requirea closedcurrentloop. – LVPECL driversareopen emitterand requirea DC pathtoground.
• Receiversshouldbe presentedwitha signalbiasedtotheirspecifiedDC biaslevel(common mode voltage) forproperoperation.Some receivershave self-biasinginputsthatautomaticallybiasto the propervoltage level.Inthiscase,thesignalshouldnormallybe AC coupled. Itispossibletodrivea non-LVPECL ornon-LVDS receiverwitha LVDS orLVPECL driveras longas theabove guidelinesare followed.Check the datasheetof the receiveror inputbeing drivento determinethe best terminationand couplingmethod tobe surethereceiverisbiasedattheoptimum DC voltage(common mode voltage).For example,when drivingtheOSCin/OSCin* inputoftheLMK01000 family,OSCin/OSCin* shouldbe AC coupledbecause OSCin/ OSCin* biasesthesignaltotheproperDC level,see Figure2.Thisisonlyslightly differentfrom the AC coupledcases described(See Section3.4.2) because the DC blockingcapacitorsare placedbetween the terminationand the OSCin/OSCin* pins,but the conceptremainsthe same, which isthe receiver(OSCin/OSCin*)settheinputtotheoptimum DC biasvoltage(common mode voltage),notthedriver. TerminationforDC Coupled DifferentialOperation For DC coupledoperationofan LVDS driver,terminatewith100 Ω as closeas possibletotheLVDS receiveras shown inFigure4.To ensureproperLVDS operationwhen DC couplingitisrecommend touse LVDS receivers withoutfail-safeor internalinputbiassuch as NationalSemiconductor'sDS90LV110T. The LVDS driverwill providethe DC bias levelforthe LVDS receiver.For operationwithLMK01000 familyLVDS driversitis recommend to use AC couplingwithLVDS receiversthathave an internalDC biasvoltage.Some fail-safe circuitrywillpresenta DC bias (common mode voltage)which willpreventthe LVDS driverfrom working correctly.Thisprecautiondoes notapplytotheLVPECL drivers.

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CLKoutX* LVPECL Receiver 120: 100:Trace (Differential) 120: Vcc Vcc LVPECL Driver 82:82: CLKoutX CLKoutX* LVPECL Receiver 50: 100:Trace (Differential) 50: Vcc - 2 V Vcc - 2 V LVPECL Driver CLKoutX CLKoutX* LVDS Receiver 100:100:Trace (Differential) LVDS Driver LMK01000 www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 Figure4. DifferentialLVDS Operation,DC Coupling For DC coupledoperationof an LVPECL driver,terminatewith50 Ω to Vcc - 2 V as shown in Figure5. Alternativelyterminatewitha Theveninequivalentcircuit(120Ω resistorconnectedtoVcc and an 82 Ω resistor connectedto ground withthe driverconnectedto the junctionof the 120 Ω and 82 Ω resitors)as shown in Figure6 forVcc = 3.3V. Figure5. DifferentialLVPECL Operation,DC Coupling Figure6. DifferentialLVPECL Operation,DC Coupling,Thevenin Equivalent TerminationforAC Coupled DifferentialOperation AC couplingallowsforshiftingthe DC bias level(common mode voltage)when drivingdifferentreceiver standards.SinceAC couplingpreventsthedriverfromprovidinga DC biasvoltageatthereceiveritisimportant toensurethereceiverisbiasedtoitsidealDC level. When drivingLVDS receiverswithan LVDS driver,the signalmay be AC coupledby adding DC blocking capacitors,however theproperDC biaspointneeds tobe establishedatthereceiver.One way todo thisiswith theterminationcircuitryinFigure7. Copyright© 2008–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LMK01000

CLKoutX* 50: 50:Trace 50: Load Vcc - 2V Vcc - 2V LVPECL Driver CLKoutX CLKoutX* 120:120: 0.1 PF 0.1 PF LVPECL Reciever 100:Trace (Differential) LVPECL Driver 82: 120: Vcc 82: 120: Vcc CLKoutX CLKoutX* 0.1 PF 0.1 PF LVDS Receiver 50: 100:Trace (Differential) LVDS Driver 50: Vbias LMK01000 SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com Figure7. DifferentialLVDS Operation,AC Coupling LVPECL driversrequirea DC pathtoground.When AC couplingan LVPECL signaluse 120 Ω emitterresistors closetotheLVPECL drivertoprovidea DC pathtogroundas shown inFigure11.Forproperreceiveroperation, thesignalshouldbe biasedtotheDC biaslevel(common mode voltage)specifiedby thereceiver.The typical DC biasvoltage(common mode voltage)forLVPECL receiversis2 V. A Thevenin equivalentcircuit(82 Ω resistorconnectedtoVcc and a 120 Ω resistorconnectedtogroundwiththedriverconnectedtothejunctionof the82 Ω and 120 Ω resistors)isa validterminationas shown inFigure8 forVcc = 3.3V. Note:thisThevenin circuitisdifferentfromtheDC coupledexample inFigure6. Figure8. DifferentialLVPECL Operation,AC Coupling,Thevenin Equivalent TerminationforSingle-EndedOperation A baluncan be used witheitherLVDS or LVPECL driversto convertthe balanced,differentialsignalintoan unbalanced,single-endedsignal. Itispossibletouse an LVPECL driveras one ortwo separate800 mV p-psignals.When DC couplingone ofthe LMK01000 familyLVPECL drivers,theterminationshouldstillbe 50 Ω toVcc -2 V as shown inFigure9.Again theTheveninequivalentcircuit(120Ω resistorconnectedtoVcc and an 82 Ω resistorconnectedtogroundwith thedriverconnectedtothejunctionofthe120 Ω and 82 Ω resistors)isa validterminationas shown inFigure10 forVcc = 3.3V. Figure9. Single-EndedLVPECL Operation,DC Coupling

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0.1 PF 0.1 PF 50:Trace 50: LMK InputClock Source CLKoutX CLKoutX* 120:120: 0.1 PF 0.1 PF 50:Trace 50: Load 50: LVPECL Driver CLKoutX CLKoutX* 82: 50:Trace 120: Load Vcc 82: 120: Vcc LVPECL Driver LMK01000 www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 Figure10. Single-EndedLVPECL Operation,DC Coupling,Thevenin Equivalent When AC couplingan LVPECL driveruse a 120 Ω emitterresistortoprovidea DC pathtogroundand ensurea 50 Ω terminationwiththe properDC bias levelforthe receiver.The typicalDC bias voltageforLVPECL receiversis2 V (See Section3.4.1).Iftheotherdriverisnotused itshouldbe terminatedwitheithera properAC or DC termination.Thislatterexample ofAC couplinga single-endedLVPECL signalcan be used tomeasure single-endedLVPECL performanceusinga spectrumanalyzeror phase noiseanalyzer.When usingmost RF testequipment no DC bias point(0 V DC) is expected forsafe and properoperation.The internal50 Ω terminationthetestequipmentcorrectlyterminatestheLVPECL driverbeingmeasured as shown inFigure11. When usingonlyone LVPECL driverofa CLKoutX/CLKoutX* pair,be suretoproperlyterminatedtheunused driver. Figure11. Single-EndedLVPECL Operation,AC Coupling Conversion toLVCMOS Outputs To drivean LVCMOS inputwithan LMK01000 familyLVDS or LVPECL output,an LVPECL/LVDS toLVCMOS convertersuch as NationalSemiconductor'sDS90LV018A, DS90LV028A, DS90LV048A, etc.isrequired.For bestnoiseperformance,LVPECL providesa highervoltageswingintoinputoftheconverter. OSCin INPUT InadditiontoLVDS and LVPECL inputs,OSCin can alsobe drivenwitha sinewave. The OSCin inputcan be drivensingle-endedordifferentiallywithsinewaves.These configurationsareshown inFigure12 and Figure13. Figure12. Single-EndedSine Wave Input Copyright© 2008–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LMK01000

FREQUENCY (MHz) -10 -15 -20 POWER (dBm) 50 80 Minimum Recommended Power for Differential Operation 20 30 40 60 10090 Minimum Recommended Power for Single-Ended Operation 0.1 PF 0.1 PF LMK Input 100:100:Trace (Differential) Clock Source LMK01000 SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com Figure13. DifferentialSine Wave Input Figure14 shows the recommended power levelforsinewave operationforboth differentialand single-ended sourcesoverfrequency.The partwilloperateatpower levelsbelow therecommended power level,butas power decreasesthe PLL noiseperformancewilldegrade.The VCO noiseperformancewillremain constant.At the recommended power levelthePLL phase noisedegradationfromfullpower operation(8dBm) islessthan2 dB. Figure14. Recommended OSCin Power forOperationwitha Sine Wave Input MORE THAN EIGHT OUTPUTS WITH AN LMK01000 FAMILY DEVICE The LMK01000 familydevicecan be used inconjunctionwitha LMK02000, LMK03000, LMK04000, or even anotherLMK01000 deviceinordertoproducemore than8 outputs.When doingthis,attentionneeds tobe given tohow thefrequenciesare assignedforeach outputtoeliminatesynchronizationissues.RefertoAN-1864 for more details. GLOBAL DELAY THROUGH AN LMK01000 FAMILY DEVICE The delayfrom CLKin to CLKout isdeterminsic,but can varybased on the engaged delaysand dividesas discussedin Section2.3.2forthe CLKoutX_MUX bit.In addition,therecan be variationsbased on voltage, temperature,and frequency.AN-1864 discussesthisglobaldelayinmore detail.

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www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LMK01000ISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01000 I LMK01000ISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01000 I LMK01000ISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01000 I LMK01010ISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01010 I LMK01010ISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01010 I LMK01010ISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01010 I LMK01020ISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01020 I LMK01020ISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01020 I LMK01020ISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K01020 I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

www.ti.com 11-Apr-2013 Addendum-Page 2 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK01000ISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK01000ISQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK01000ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK01010ISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK01010ISQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK01010ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK01020ISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK01020ISQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK01020ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 2

www.ti.com SQA48A (Rev B)

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